DE102008056215A1 - Sensitive data protection, during scanning, uses a secure reset signal with a combined scanning mode signal and system reset signal to reset a register - Google Patents

Abstract

To protect sensitive data during a scanning mode, a reset generator resets at least one register in a register bank. A scanning mode input connection (204) transfers a scanning mode signal (501) to activate at least one register (101a). A system reset signal (506) is passed through an input connection (205) to reset at least one register. An additional secure reset signal (505) at the reset output connection (208) resets the register. A logic unit combines the scanning a reset signals either in a scanning mode or a normal mode where the secure and reset signals match. A reset control flip-flop (203) generates a scan reset signal (503) according to the system reset signal, to deactivate the secure reset signal when the system reset signal is deactivated.

Description

The The present invention relates generally to electronic test equipment for testing to be tested electronic Circuits and in particular a method and a circuit for Protect sensitive data during the scan mode of the test device. Electronic circuits that need to be tested can contain sensitive information the while a scan mode of such a test procedure can not be retrieved should. An unauthorized use of such a scan check operation The integrated circuit can lead to the loss or the unauthorized Use sensitive information.

In order to protect this kind of sensitive information, it has been proposed to insert a test isolation multiplexer in the chain of a protected register. 1 shows the string of a protected register, wherein an output of the string of the protected register can only be read out if not entering the scan mode. When entering the scan mode, ie scan mode = 1, the test isolation multiplexer M blocks the output signal O before the protected register string.

A major disadvantage of in 1 In the prior art configuration shown, registers are excluded from the scan mode so that their functionality can not be checked. The registers excluded by the test isolation multiplexer are thus disadvantageously not tested.

A The object of the present invention is therefore the provision a device for electronic testing of electronic circuit units to be tested and a method for testing, sensitive data being read before or during a test mode protected become.

Against this background, a reset generator is provided for resetting at least one register in a register bank according to independent claim 1. Furthermore, a protective device for protecting confidential data with the features of independent claim 15 is provided. Furthermore, a method for protecting confidential data stored in a register bank comprising at least one register to be checked according to the independent method claim 20 and a method for checking at least one register according to the independent method claim 34 provided. The claims are a first non-binding attempt to describe the invention in general terms.

Further preferred developments of the present invention are according to the dependent claims and the description.

According to one Aspect of the present invention is a reset generator for resetting at least a register provided in a register bank, the reset generator comprising: a Scan mode input port for inputting a scan mode signal for activating the scan mode of the at least one register; one System reset input connector for inputting a system reset signal to reset the at least one register; a secure reset output port for issuing a secure reset signal for resetting the at least one register; and a logic unit for linking to Link or combining the scan mode signal and the system reset signal, wherein the logic unit designed for it is to switch between the following: operation (i) in a scan mode, in which the scan mode signal a reset of the at least one register, and (ii) in a normal mode, in which the secure reset signal corresponds to the system reset signal.

According to one second aspect of the present invention is a protective device to protect provided confidential data, wherein the protective device comprising: a register bank with at least one register to be audited, the at least one register contains confidential data; and a reset generator with a scan mode input terminal to enter a scan mode signal for activating the scan mode of the at least one register; a system reset input port for inputting a system reset signal for resetting the at least one register; a secure reset output port for outputting a Secure reset signal for reset the at least one register; and a logic unit for linking or Combining the scan mode signal and the system reset signal, wherein the logic unit designed for it is, between operation in a scan mode where the scan mode signal a reset ensures the at least one register, and in a normal mode, where the secure reset signal corresponds to the system reset signal to switch, wherein the Secure Reset output terminal of the reset generator with at least one register reset input terminal of at least connected to a register.

Further provided is a method for protecting confidential data stored in a register bank including at least one register to be checked, the method comprising the fol These steps include:
Inputting a scan mode signal into a scan mode input terminal of a reset generator for activating the scan mode of the at least one register; Inputting a system reset signal into a system reset input terminal of the reset generator for resetting the at least one register; Combining the scan mode signal and the system reset signal to provide a secure reset signal, by means of a logic combiner unit configured to operate in a scan mode in which the scan mode Mode signal ensures a reset of at least one register, and to switch in a normal mode in which the Secure Reset signal corresponds to the system reset signal; and outputting the Secure Reset signal via a Secure Reset output port for resetting the at least one register.

Further will be a method of testing provided at least one register, the method the following steps include: Enter a scan mode signal into a scan mode input port a deactivated reset generator to activate the scan mode the at least one register; Output the content of at least a register; Activating the reset generator; Enter a Scan mode signal into a scan mode input port of the activated Reset generator for activating the scan mode of the at least one register; Enter a system reset signal into a system reset input port of the activated reset generator to reset the at least one register; Link or combining the scan mode signal and the system reset signal, to provide a secure reset signal, by means of a logic unit, the one for that is designed to operate between a scan mode in which the Scan mode signal on reset ensures the at least one register, and in a normal mode, where the secure reset signal corresponds to the system reset signal, switch; and issuing the reset reset signal of the at least one register a secure reset output port.

embodiments The present invention is illustrated in the drawings and explained in the following description.

It demonstrate:

1 a block diagram of a conventional protective device for protecting sensitive data contained in registers to be protected;

2 a timing diagram of a reset procedure when the reset generator is turned off according to the present invention;

3 a block diagram of a first embodiment of a protective device according to the present invention;

4 a table illustrating the correspondence of a secure scan signal, a scan mode signal, a scan reset signal, and a secure reset signal;

5 a timing diagram of in the block diagram of 3 occurring logic signals;

6 a block diagram of a second preferred embodiment of a protective device according to the present invention; and

7 a timing diagram in the block diagram of 6 occurring signals.

In In the figures, like reference numerals designate the same or similar ones Parts or steps.

confidential Information or confidential data to be protected in Registers are included immediately after being in the scan mode for this Register is entered, deleted. advantageously, The present invention provides a reset generator that provides an instant reset signal for the the ones to be tested Register-containing register bank upon activation of a scan mode signal generated. After this reset, confidential data is deleted and the ones to be tested Registers can using a scan mode procedure and a reset procedure be examined by a system reset signal.

According to one first embodiment The present invention is a reset generator for resetting at least one register in a register bank designed so that a scan mode input port to enter a scan mode signal to activate the scan mode of the at least one register, a system reset input terminal for inputting a System reset signal for reset of the at least one register, a secure reset output port for issuing a secure reset signal of the at least one register and a linking unit for linking or combining the scan mode signal and the system reset signal are provided.

Another advantage of the present invention is that registers to be protected are deleted immediately after entering the scan mode so that sensitive information or confidential data is no longer accessible. After this first reset, it is preferred that upon activation of the scan mode, a check of the registers contained in the register bank can be made. The logic combiner unit for combining the scan mode signal and the system reset signal provides an active secure reset signal for resetting the at least one register at a time when the scan mode of the at least one register is activated , ready. The combination of the scan mode signal and the system reset signal is thus such that when the scan mode of the at least one register is activated, the secure reset signal is immediately activated to reset the at least one register. Activation of the Secure Reset signal is independent of the System Reset signal.

Then The Secure Reset signal is disabled when the system reset signal is deactivated, and finally The Secure Reset signal follows the activation / deactivation cycles the system reset signal. After resetting the at least one Register immediately after the scan mode is initiated the secure reset signal preferably the system reset signal.

According to one preferred development of the present invention is a reset Steuerflipflop to Generating a scan reset signal in response to the system reset signal to disable the Secure Reset signal when the system reset signal is disabled will be provided. Preferably, a control cell for generating a gate control signal in dependence provided by the scan mode signal and the scan reset signal.

According to one Another preferred development of the present invention a reset gating cell for generating the secure reset signal dependent on provided by the gate control signal and the system reset signal. Preferably, the reset gate cell is an AND gate.

According to one another embodiment The present invention is a reset generator for resetting provided at least one register in a register bank. The reset generator includes a scan mode input port for inputting a scan mode signal for activating the scan mode of the at least one register, a Kernel reset input connector for inputting a kernel reset signal to reset the at least one register, a scan release input port to enter a secure scan release signal, a secure reset output port to Issuing a Secure Reset signal to reset the at least one Register and a logic unit for linking to Link or Combine the scan mode signal and the kernel reset signal. This type of link is designed so that when the scan mode of the at least one register is activated, the Secure Reset signal immediately to reset the at least one Register is activated. Activation of the Secure Reset signal is from independent of the kernel reset signal.

Farther The Secure Reset signal is disabled when the Secure Scan Release signal input in the scan release input port. Then follows the Secure Reset signal indicates the cycles of activation / deactivation the kernel reset signal.

According to one Another development of the present invention is a reset Steuerflipflop to Generating a scan reset signal in response to the secure scan release signal to disable the secure reset signal.

According to one Further development of the present invention is a control cell for generating a gate control signal in response to the scan mode signal and the scan reset signal provided.

Preferably a reset gating cell is generated to generate the secure reset signal provided by the gate control signal and the kernel reset signal.

According to one another preferred embodiment According to the present invention, a protection device for protecting is more confidential Provided data, the protective device comprising: a Register bank comprising at least one register to be checked, wherein the at least one register contains confidential data, and a reset generator, with the secure reset output connector of the reset generator with at least one register reset input terminal the at least one register is connected.

According to one Another preferred development of the present invention in the protection device to provide a secure-scan signal to activate the reset generator as a whole a one-time programmable Element provided.

According to another preferred development of the present invention, the one provided for activating the reset generator becomes unique realized programmable element as a laser fusion or laser fuse or an electrical fuse or electrical fuse.

confidential Data that protect are, are encryption data and / or electronic keys and / or secure information and / or sensitive information.

According to one another preferred embodiment The present invention provides a method for protecting provided confidential data stored in a register bank which are at least one to be tested Register includes. The Method includes the following steps: Enter a scan mode signal to activate scanning the at least one register via a scan mode input port of a reset generator, enter a reset system reset signal of the at least one register via a System reset input terminal of the reset generator, linking or Combine the scan mode signal and the system reset signal to to provide a secure scan mode signal by means of a logic unit.

The through the logic unit provided link is designed so that when the scan mode of the at least one register is activated, the Secure Reset signal immediately to reset the at least one Register is activated. Activation of the Secure Reset signal is independent of the system reset signal. The secure reset signal will be disabled when the system reset signal is disabled is, and finally follows the Secure Reset signal indicates the cycles of activation / deactivation the system reset signal. Further, the step of outputting becomes the Secure Reset signal to reset of the at least one register provided a secure reset output port.

According to one Another preferred development of the present invention a scan reset signal depending from the system reset signal to disable the secure reset signal, when the system reset signal is deactivated, generated by means of a reset control flip-flop.

Preferably becomes a gate control signal in response to the scan mode signal and the scan reset signal generated by means of a control cell. It is advantageous that the secure reset signal dependent on from the gate control signal and the system reset signal by means of a reset gating cell is produced.

According to one another preferred embodiment The present invention provides a method for protecting provided confidential data stored in a register bank which are at least one to be tested Register includes.

The Method includes the following steps: Enter a scan mode signal to activate the scan mode of the at least one register via a scan mode input port of a reset generator, inputting a kernel reset signal to Reset to default of the at least one register a kernel reset input terminal of the reset generator, enter a secure scan release signal through a scan release input connector of the reset generator, linking or Combine the scan mode signal and the kernel reset signal to provide a secure reset signal, by means of a logic link in such a way that when the scan mode of the at least one register is activated, the Secure reset signal immediately to reset the at least one Register is activated. Activation of the Secure Reset signal is independent of the kernel reset signal. The secure reset signal will be disabled when the Secure Scan Release signal is activated and the Secure Reset signal follows the activation / deactivation cycles of the kernel reset signal, and issuing the reset secure reset signal of the at least one register a secure reset output port.

According to one Another preferred development of the present invention a scan reset signal depending from the Secure Scan Release signal to disable the Secure Reset signal generated by means of a reset control flip-flop.

It is preferred that a Gate control signal in dependence from the scan mode signal and the scan reset signal is generated by means of a control cell. Preferably, the secure reset signal becomes dependent on the gate control signal and the kernel reset signal by means of a reset gating cell generated.

3 shows a block diagram of a secure reset generator 200 and a register bank 100 according to a first preferred embodiment of the present invention. The reset generator 200 essentially has two input terminals 204 and 205 and an output terminal 208 , A first input terminal is a scan mode input terminal 204 for receiving a scan mode signal 501 ,

The scan mode signal 501 is activated (logic "1") when entering a scan mode of the circuitry, at logic "0" the scan mode signal is disabled 501 the Scan mode, ie the functional mode of the circuit arrangement is established.

A second input terminal is a system reset input terminal 205 to which the system reset signal 506 is created. The system reset signal 506 provides a system reset and in accordance with a preferred embodiment of the present invention, this signal is in the reset generator 200 processed. The secure reset generator 200 can also be a one-time programmable element 300 to provide a secure-scan signal 508 include.

According to a further preferred development of the present invention, this is a one-time programmable element 300 from the reset generator 200 disconnected and the secure-scan signal 508 is created externally. As in 3 Shown to be the Secure Scan signal 508 , the scan mode signal 501 and a scan reset signal 503 , which will be described below, to a control cell 201 which is essentially realized as a NAND gate. The output signal of the control cell 201 ie the gate control signal 504 , is sent to a following reset gating cell 202 created, which consists essentially of a NAND gate. The at the system reset input port 205 applied system reset signal 506 is called a function reset signal 502 an input terminal of the reset gate cell 202 fed. A second input terminal of the reset gate cell 202 becomes the gate control signal 504 fed.

The following is the function of the Secure Reset Generator 200 described in more detail. When the gate control signal 504 whose generation will be described later, has a logic "1" level, the system reset signal applied to the system reset input terminal becomes 506 through the reset generator 200 and appears on the secure reset output port as a reset signal for the register bank 100 ,

The register bank 100 consists of registers 101 - 101n to be tested. The registers receive a system clock signal at clock input CK 507 , It is noted that in 3 only two registers to be checked 101 . 101b are shown, but the number of registers n is not limited. When the gate control signal 504 logic equal to "1" is the system reset signal 506 with a secure reset signal 505 identical, as in 3 shown to the register reset input terminals 102 - 102n is created. This mode is referred to as the "normal scan mode" and its timing diagram is in 2 shown.

In 2 are respective signals 501 . 502 . 503 . 504 and 505 as a function of time t 500 shown. As already explained, is in the pulse diagram of 2 it can be seen that the function reset signal 502 the Secure Reset signal 505 equivalent. The gate control signal 504 is logic "1" during the entire period of the normal scan mode, the scan reset signal 503 and its timing are explained below. As in 2 is apparent, the scan mode signal affects 501 not on the output signal of the reset generator 200 ie the Secure Reset signal 505 , out.

The in 2 Normal scan mode shown has the main disadvantage that a system clock 507 after entering the scan mode and before the functional reset signal 502 the register reset input terminals 102 - 102n the respective register to be audited 101 - 101n reached, to the registers 101 - 101n the register bank 100 can be created. Thus, it is possible in principle, sensitive information, eg. Confidential information, from the registers to be audited 101 - 101n to extract before these registers 101 - 101n be reset by a reset signal.

The novel solution according to the first embodiment of the present invention solves this problem by using the secure reset generator 200 , As in 3 In addition, the secure reset generator further includes a reset control flip flop 203 , which is realized as a D flip-flop known in the art. The D input of the reset control flip flop 203 is continuously fed logic "1", so that a positive edge of the system reset signal 506 to the clock input (CK) of the reset control flip-flop 203 and to a switchover of the reset control flip-flop 203 is applied so that its Q output changes to logic "1." It is noted that when entering the scan mode, the scan mode signal 501 logic "1", so that a reset input of the Reset Steuerflipflops 203 is disabled, and before entering the scan mode, the reset control flip flop 203 is reset.

During the scan mode, therefore, a positive edge of the system reset signal results 506 to a logic level of "1" of the scan reset signal 503 , When the scan reset signal 503 from logic "0" to logic "1", the control cell switches 201 change its output from logical "0" to logical "1".

The previous output of the control cell 201 of logic "0" is due to the fact that all for the control cell 201 previously provided logical "1." That is, the Secure Scan signal 508 is logically "1" because the one time programmable element 300 has melted, the scan mode signal 501 is logical "1" because the scan mode was entered and the scan reset signal 503 is logically "1" until a first positive edge of the system reset signal 506 through the reset control flip flop 203 is detected.

In other words, when entering the scan mode (the scan mode signal 501 turns from logic "0" to logic "1") the gate control signal 504 logic "0", so that also the secure reset signal 505 is logical "0", which means that in the register bank 100 provided registers 101 - 101n reset immediately after entering the scan mode. In the 3 logic shown is "active low", that is, a logic level of "0" of the Secure Reset signal 505 to activate the resetting of the registers to be checked 101 - 101n leads. Thus, it is impossible to extract any information as soon as the scan mode has been entered.

To solve the reset signal, ie a logical "1" of the Secure Reset signal 505 provide the switching of the reset control flip-flop 203 introduced. After the first positive edge of the system reset signal 506 provides the Q output terminal of the reset control flip-flop 203 a logical "1" for the scan reset signal 503 , so that the respective input terminal of the control cell 201 logic "0." Thus, the control cell switches 201 its output from logic "0" to logic "1" and it is entered as previously explained in the situation of the normal scan mode.

The difference from the situation described above is that the normal scan mode now without any possibility of sensitive information from the registers 101 - 101n can be applied, because the sensitive information already immediately after entering the scan mode (immediately after switching the scan mode signal 501 from logic "0" to logical "1") from the registers 101 - 101n were deleted.

To further explain the timing of the respective reset signals during the scan mode, shows 4 a table of correspondence for the scan mode signal 501 , the secure-scan signal 508 , the scan reset signal 503 and the secure reset signal 505 , As in 4 shown determines the Secure Scan signal 508 the functionality of the reset generator 200 , If the secure-scan signal 508 logic is "0", the normal scan mode is turned on, ie, whether the scan mode is on or off, corresponds to the Secure Reset signal 505 exactly the system reset signal 506 ,

This is the case when the once programmable element 300 not melted, so that the secure-scan signal 508 is equal to logic "0". When the fuse element 300 has melted (last three lines of in 4 shown table, ie when the secure scan signal 508 is logic "1"), Secure Scan mode is turned on 4 shown table shows that when the secure-scan signal 508 is equal to logic "1" and the scan mode signal 501 equal to logic "0" (ie the scan mode is not activated), the secure reset signal 508 still exactly the system reset signal 506 equivalent.

However, if, as in line 3, the in 4 As shown in the table shown, the scan mode signal is logic "1" and the scan reset signal is logic "0", which is the secure reset signal 505 equal to logic "0". That is, immediately after entering a scan mode (ie, the scan mode signal 501 is equal to logical "1") the registers 101 - 101n the register bank 100 be reset.

in the Generally, a one-time programmable element can only be done once be melted through, d. H. the element has a default value, if it is not melted (usually, but not necessarily "0"). It is then possible to do it once melt through (this inverts the stored value), but it is generally not possible to go to the previous value come back. Consequently, it is still possible Use the scan mode to get the sensitive information to extract, before the once programmable element melted so that the Using the scan mode to debug the theme (for example, on a Test chip) including the protected Information becomes possible. Only after the once programmable element has melted is, the information is no longer accessible and therefore is the chip safe and can now safely delivered to external customers and end users become.

After this kind of resetting of the registers to be checked 101 - 101n any confidential information contained in the registers is deleted. As in the last line of the in 4 Thus, the scan mode is continued (ie, the scan mode signal 501 is equal to logical "1" and the secure-scan signal 508 is equal to logic "1") and results in a scan reset signal of logic "1", so that the secure reset signal 505 exactly the system reset signal 506 corresponds to, as in the case of the normal scan mode line 1 of in 4 shown table.

Unlike the in 1 shown registers that are excluded from the scan chain are thus the in 3 included registers in the scan chain without sacrificing the sensitive information. This improves the overall test coverage.

5 is a timing diagram of a timing between those in the reset generator 200 present signals, ie the scan mode signal 501 , the function reset signal 502 , the scan reset signal 503 , the gate control signal 504 and the secure reset signal 505 , As soon as the scan mode is entered (scan mode signal 501 is equal to logic "1"), as shown in the timing diagram of 5 shown the gate control signal 504 a transition from logic "1" to logical "0", so that the secure reset signal 505 from logical "1" to logical "0".

This circumstance leads to a reset of the registers to be checked 101 - 101n the register bank 100 , This switching situation is shown by the arrows A1 and A2. After a positive edge of the function reset signal 502 indicates the scan reset signal 503 as indicated by the arrow B1 indicated a transition from logic "0" to logical "1". At this point, the gate control signal is pointing 504 a transition from logic "0" to logic "1", so that the secure reset signal 505 through the reset gate cell 202 to the secure reset output port 208 of the reset generator 200 is directed. Starting from the moment indicated by the arrow B1 corresponds to the Secure Reset signal 505 thus exactly the function reset signal 502 ,

6 shows a block diagram of a secure reset generator 200 together with a register bank 100 according to a second preferred embodiment of the present invention. It is noted that parts and operational steps as well as signals, the respective parts, operation steps or signals described hereinabove with reference to FIG 3 are not explained again to simplify the explanation. The main difference of in 6 shown reset generator 200 compared to the in 3 shown reset generator 200 is that a third input terminal to the reset generator 200 is provided. The third input terminal is a kernel reset input terminal 206 , which is a kernel reset signal 606 receives. It is thus possible to supply a separate signal as a reset signal, one by a secure scan release signal 602 provided scan share to the scan release input connector 207 is created.

Of the Advantage of the second embodiment according to the present Invention in comparison with the first embodiment is in principle the Circumstance that no There is a need for a functional reset signal to control the secure reset. This actually facilitates the Design process for a test pattern generation, since it is easier to control a separate signal than the functional reset, which is usually a time-critical signal, which is also on the rest of the entire circuitry. A difference the second embodiment in comparison to the first embodiment The present invention is the fact that a third input signal is available separately.

To work in 6 shown second embodiment of the present invention further shows 7 a timing diagram of the most important of the reset generator 200 according to the second embodiment of the present invention supplied signals. The momentum diagram of 7 thus shows the scan mode signal 601 , the secure scan release signal 602 , the kernel reset signal 606 , the scan reset signal 603 , the gate control signal 604 and the secure reset signal 605 ,

As before, the scan mode signal indicates 601 as indicated by an arrow C in 7 show a transition from logic "0" to logic "1". Immediately after entering the scan mode becomes the gate control signal 604 forced to provide a logical transition from logical "1" to logical "0" so that the secure reset signal 605 also provides a transition from logical "1" to logical "0". Because the secure reset signal 605 is a signal of the type "active low", thus become the registers 101 - 101n the register bank 100 reset immediately. After a transition from a logical "0" to a logical "1" at the scan release input port 207 of the reset generator 200 provided secure scan release signal 602 follows the Secure Reset signal 605 then the kernel reset signal 606 as a function of time 500 ,

100

register bank

101a-101n

To be tested register

102a-102n

Register reset input terminal

200

Reset generator

201

control cell

202

Reset gating cell

203

Reset control flip flop

204

Scan mode input terminal

205

System reset input terminal

206

Kernel reset input terminal

207

Scan release input terminal

208

Secure reset output terminal

300

unique programmable element

500

timing (Time t)

501

Scan mode signal

502

Function Reset signal

503

Scan reset signal

504

Gate control signal

505

Secure reset signal

506

System reset signal

507

System clock signal

508

Secure scan signal

601

Scan mode signal

602

Secure scan release signal

603

Scan reset signal

604

Gate control signal

605

Secure reset signal

606

Kernel reset signal

607

Kernel clock signal

608

Secure scan signal

Claims (35)

A reset generator for resetting at least one register in a register bank, the reset generator comprising: a) a scan mode input port ( 204 ) for inputting a scan mode signal ( 501 ) for activating the scan mode of the at least one register ( 101 ); b) a system reset input port ( 205 ) for inputting a system reset signal ( 506 ) for resetting the at least one register ( 101 ); c) a secure reset output port ( 208 ) is set up to output a secure reset signal ( 505 ) for resetting the at least one register ( 101 ); and d) a logic unit for combining the scan mode signal ( 501 ) and the system reset signal ( 506 ), wherein the logic unit is arranged to switch the operation between the following: (i) a scan mode in which the scan mode signal ( 501 ) resetting the at least one register ( 101 ) and (ii) a normal mode in which the Secure Reset signal ( 505 ) the system reset signal ( 506 ) corresponds. The reset generator of claim 1, further comprising a reset control flip-flop (10). 203 ) configured to generate a scan reset signal ( 503 ) in response to the system reset signal ( 506 ) to disable the Secure Reset signal when the system reset signal is disabled. The reset generator of claim 2, further comprising a control cell ( 201 ) arranged to generate a gate control signal ( 504 ) depending on the scan mode signal ( 501 ) and the scan reset signal ( 503 ). The reset generator of claim 3, further comprising a reset gating cell ( 202 ) for generating the secure reset signal ( 505 ) in response to the gate control signal ( 504 ) and the system reset signal ( 506 ). Reset generator according to one of claims 1 to 4, wherein the reset generator ( 200 ), the secure reset signal ( 505 ) immediately when the scan mode of the at least one register ( 101 ) is activated so that the at least one register is independent of the system reset signal ( 506 ) is reset. Reset generator according to one of claims 1 to 5, wherein the reset generator ( 200 ), the secure reset signal ( 505 ) when the system reset signal ( 506 ) is disabled. Reset generator according to one of claims 1 to 6, wherein the reset generator ( 200 ), the secure reset signal ( 505 ) in normal mode, the cycles of activating / deactivating the system reset signal ( 506 ) follows. The reset generator of any one of claims 1 to 7, further comprising: - a kernel reset input port ( 206 ) for inputting a kernel reset signal ( 606 ) for resetting the at least one register ( 101 ); and a scan release input port ( 207 ) for entering a secure scan release signal ( 602 ), wherein the logic unit is adapted to operate in the normal mode in which the secure reset signal corresponds to the kernel reset signal. Reset generator according to claim 8, wherein the reset generator ( 200 ) is enabled to immediately activate the Secure Reset signal when the scan mode of the at least one register ( 101 ) is activated so that the at least one register is reset independently of the kernel reset signal. Reset generator according to claim 8 or 9, wherein the reset generator ( 200 ) is set to disable the Secure Reset signal when the Secure Scan Release signal is activated. Reset generator according to one of claims 8 to 10, with the reset generator adapted, the secure reset signal in the normal mode, the cycles of activation / deactivation the kernel reset signal follows. The reset generator of any one of claims 8 to 11, further comprising a reset control flip flop ( 203 ) configured to generate a scan reset signal ( 603 ) depending on the secure scan release signal ( 602 ) to deactivate the Secure Reset signal. Reset generator according to claim 12, wherein a control cell ( 201 ) for generating a Gate control signal in response to the scan mode signal and the scan reset signal is present. The reset generator of claim 13, further comprising a reset gating cell (10). 202 ) configured to generate the secure reset signal in response to the gate control signal and the kernel reset signal. Protective device for protecting confidential data, comprising: a) a register bank ( 100 ) containing at least one register to be checked ( 101 ), the at least one register containing confidential data; and b) a reset generator ( 200 ), comprising: b1) a scan mode input port ( 204 ) for inputting a scan mode signal for activating the scan mode of the at least one register ( 101 ); b2) a system reset input terminal ( 205 ) for inputting a system reset signal for resetting the at least one register ( 101 ); b3) a Secure Reset output port ( 208 ) arranged to output a secure reset signal for resetting the at least one register ( 101 ); and b4) a link logic unit configured to combine the scan mode signal and the system reset signal, the link logic unit being adapted to switch between the following modes of operation: (i) a scan mode in which the scan mode Ensures a reset of the at least one register, and (ii) a normal mode in which the secure reset signal corresponds to the system reset signal, wherein c) the secure reset output port ( 208 ) of the reset generator ( 200 ) with at least one register reset input terminal ( 102 ) of the at least one register ( 101 ) connected is. Apparatus according to claim 15, further comprising a one-time programmable element ( 300 ) adapted to provide a secure-scan signal for activating the reset generator. Device according to claim 16, wherein the one-time programmable element (14) provided for activating the reset generator ( 300 ) is realized as a laser fusion connection or laser fuse. Device according to claim 16, wherein the one-time programmable element (14) provided for activating the reset generator ( 300 ) is realized as an electrical fuse or electrical fuse. Device according to one of claims 15 to 18, wherein the confidential ones Data encryption data and / or electronic keys and / or secure information and / or sensitive information are. Procedure for protecting confidential data stored in a register bank ( 100 ) containing at least one register to be checked ( 101 ) comprising: a) inputting a scan mode signal ( 501 ) for activating the scan mode of the at least one register ( 101 ) into a scan mode input port ( 204 ) of a reset generator ( 200 ); b) inputting a system reset signal ( 506 ) for resetting the at least one register into a system reset input terminal ( 205 ) of the reset generator ( 200 ); c) Combining or Combining the Scan Mode Signal ( 501 ) and the system reset signal ( 506 ) to send a secure reset signal ( 505 ) by means of a logic unit that is adapted to switch between modes of operation: c1) a scan mode in which the scan mode signal ( 501 ) resetting the at least one register ( 101 ) and (c2) a normal mode in which the Secure Reset signal ( 505 ) the system reset signal ( 506 ) corresponds; and d) issuing the Secure Reset signal ( 505 ) for resetting the at least one register ( 101 ) via a secure reset output port ( 208 ). The method of claim 20, wherein the reset generator is adapted to provide the secure reset signal ( 505 ) immediately when the scan mode of the at least one register is activated, so that the at least one register is independent of the system reset signal ( 506 ) is reset. The method of claim 20 or 21, wherein the reset generator is adapted to the secure reset signal ( 505 ) when the system reset signal ( 506 ) is disabled. Method according to one of claims 20 to 22, wherein the reset generator is adapted, the secure reset signal ( 505 ), which in normal mode follows the cycles of activating / deactivating the system reset signal ( 506 ). Method according to one of claims 20 to 23, wherein a scan reset signal ( 503 ) in response to the system reset signal ( 506 ) to disable the Secure Reset signal ( 505 ), if that System reset signal is disabled by means of a reset control flip-flop ( 203 ) is produced. The method of claim 24, wherein a gate control signal ( 504 ) depending on the scan mode signal ( 501 ) and the scan reset signal ( 503 ) by means of a control cell ( 201 ) is produced. The method of claim 25, wherein the secure reset signal ( 505 ) in response to the gate control signal ( 504 ) and the system reset signal ( 506 ) by means of a reset gating cell ( 202 ) is produced. The method of any of claims 20 to 26, further comprising: inputting a kernel reset signal ( 606 ) for resetting the at least one register via a kernel reset input port ( 206 ) of the reset generator; and entering a Secure Scan Release signal ( 602 ) via a scan release input connector ( 207 ) of the reset generator, wherein the logic unit is adapted to operate in a normal mode where the secure reset signal ( 605 ) the kernel reset signal ( 606 ) corresponds. The method of claim 27, wherein the reset generator is adapted to provide the secure reset signal ( 605 ) immediately when the scan mode of the at least one register ( 101 ) is activated so that the at least one register is reset independently of the system reset signal. The method of claim 27 or 28, wherein the reset generator is adapted to the secure reset signal ( 605 ) when the Secure Scan Release signal ( 602 ) is activated. Method according to one of claims 27 to 29, wherein the reset generator ( 200 ), the secure reset signal ( 605 ), which in normal mode resets the cycles of activating / deactivating the kernel reset signal ( 606 ) follows. Method according to one of claims 26 to 30, wherein a scan reset signal ( 603 ) in response to the Secure Scan Release signal for deactivating the Secure Reset signal ( 605 ) is generated by means of a reset control flip-flop. A method according to claim 31, wherein a gate control signal ( 604 ) depending on the scan mode signal ( 501 ) and the scan reset signal ( 603 ) by means of a control cell ( 201 ) is produced. The method of claim 32, wherein the secure reset signal ( 605 ) in response to the gate control signal ( 604 ) and the kernel reset signal ( 606 ) by means of a reset gating cell ( 202 ) is produced. A method of checking at least one register, comprising: a) inputting a scan mode signal ( 501 ) for activating the scan mode of the at least one register ( 101 ) via a scan mode input port ( 204 ) of a deactivated reset generator ( 200 ); b) outputting the content of the at least one register ( 101 ); c) activating the reset generator ( 200 ); d) inputting a scan mode signal ( 501 ) for activating the scan mode of the at least one register ( 101 ) into a scan mode input port ( 204 ) of the activated reset generator ( 200 ); e) inputting a system reset signal ( 506 ) for resetting the at least one register ( 101 ) via a system reset input terminal ( 205 ) of the activated reset generator ( 200 ); f) Combining or Combining the Scan Mode Signal ( 501 ) and the system reset signal ( 506 ) to send a secure reset signal ( 505 ) by means of a link logic unit adapted to switch modes of operation: (f1) a scan mode in which the scan mode signal (FIG. 501 ) resetting the at least one register ( 101 ) and (f2) a normal mode in which the Secure Reset signal ( 505 ) the system reset signal ( 506 ) corresponds; and g) outputting the Secure Reset signal ( 505 ) for resetting the at least one register via a secure reset output terminal ( 208 ). The method of claim 34, wherein the reset generator ( 200 ) by melting a one-time programmable element ( 300 ) is activated.