DE102008018955B4 - Measurement architecture tailored to the current range for multi-level phase change memory - Google Patents

Abstract

A memory device comprising: a memory cell (46) coupled to a bit line (60, 62) and a word line (56, 58) and comprising a phase change material (98, 100), the memory cell having a first cell state in which it has a high resistance, at least a second cell state in which it has a medium resistance, and a third cell state in which it has a low resistance, the high resistance being higher than the mean resistance and the mean resistance being higher than that low resistance; a sense amplifier (118) having a reference input for receiving a reference voltage (VREF) and coupled to a sense node (116) for sensing a voltage at the sense node (116) relative to the reference voltage (VREF); a Circuit for applying the reference voltage (VREF) to the reference input, the reference voltage in a sequence of a first value (VREF1) which is used to switch between the ers th cell state and the second cell state, and a second value (VREF3), which is used to distinguish between the second cell state and the third cell state, is changed; a circuit (18) to the bit line (60, 62) selectively in signal communication with the measurement node (116); a power source (114) to generate a read current; a switch (112) coupled to selectively apply the read current to the measurement node (116); and a circuit (100, 112) coupled to the switch (112) for controlling the length of a read current pulse, wherein the circuit (110, 112), in response to a detection of a threshold voltage at the measuring node (116), the switch (112) such controls that the electrical connection between the current source (114) and the measuring node (116) is terminated so that the resistance state of the memory cell does not change due to the read current pulse, the threshold voltage being switched in such a way that it corresponds to the reference voltage that occurs in a read cycle the reference input is applied.

Description

BACKGROUND OF THE INVENTION

Field of invention

The present invention relates to high density memory devices based on phase change memory materials, and in particular to readout or measurement circuits for such devices

Description of the related art

From the pamphlet US 2006/0146600 A1 a phase change memory and a method for reading out the same are known, read disturbances in the phase change memory being reduced by progressively reducing the falling edges of the read pulse. This can reduce the possibility of deletion and inadvertent amorphization of at least a portion of the phase change material.

Phase change storage materials are used extensively in read / write optical storage disks. These materials have at least two solid phases including e.g. B. a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read / write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change of phase change materials, such as chalcogenide based materials and similar materials, can also be induced by applying electrical power to them at levels suitable for implementation in integrated circuits. The generally amorphous phase is characterized by higher resistivity than the generally crystalline phase, which can be measured to display data. These properties make the use of programmable resistive material for the formation of non-volatile memory circuits, which can be read and written with random access, of interest.

The phase change between amorphous and crystalline phases is achieved by controlling the thermal energy to which the phase change material is exposed. For example, the phase change of the phase change material from the amorphous phase to the crystalline phase is achieved by heating it to a temperature between the glass transition temperature of the phase change material and the melting temperature. This is known as "setting" and occurs during relatively low current operation. The phase change from the crystalline phase to the amorphous phase, the so-called "reset", takes place during operation with a relatively high current, during which a melting of the phase change material takes place, followed by its rapid cooling to below its glass transition temperature at a rate that one Nucleation and the growth of crystallites are reduced or even prevented. For this purpose, the phase change material can be subjected to a short pulse of high current density in order to break the crystal structure by melting, so that at least part of the phase change structure stabilizes in the amorphous phase at ambient temperatures. By controlling the respective proportion of the crystalline and amorphous phases of the material in a phase change element, it is possible to set up multiple storage states in the element, including a reset state that comprises an essentially completely amorphous phase of the material, one or more intermediate states in which mixtures are formed from an amorphous phase and a crystalline phase of the material, and a set state comprising a substantially completely crystalline phase of the material.

During a read operation, the phase change material is subjected to a read pulse to determine the resistance of the memory element, which indicates whether the phase change material is in a set state, a reset state, or an intermediate state. However, it is desirable to select a suitable read pulse so that the respective proportions of the amorphous and crystalline phases of the phase change material are not changed during the read operation.

SUMMARY OF THE INVENTION

The object of the invention is achieved by a memory device according to the main claim 1 and by a method for reading a memory cell according to the independent patent claim 7. Further developments of the invention are specified in the subclaims.

Figure list

• 1 Figure 3 is a block diagram of an integrated switch device in accordance with the present invention.
• 2 FIG. 13 is a partial schematic view of a memory cell array as in FIG 1 shown.
• 3 Fig. 13 is a perspective view showing the structure of a pair of memory cells which for use in the memory cell array of 2 suitable.
• 4th Figure 3 is a circuit diagram of a measurement architecture in accordance with an embodiment of the present invention.
• 5 FIG. 13 is a timing diagram showing the relative timing of a read enable signal, a bit line voltage signal, and a bit line read current for four different data states of a phase change element for embodiments of a measurement architecture as in FIG 4th shown shows.
• 6th Figure 3 is a circuit diagram of a measurement architecture according to a first alternative embodiment.
• 7th Figure 3 is a circuit diagram of a measurement architecture in accordance with a second alternative embodiment of the present invention.
• 8th Figure 3 is a circuit diagram of a measurement architecture in accordance with a third alternative embodiment of the present invention.
• 9 Fig. 13 is a graph showing a relationship between a change in a voltage drop across a phase change element and the change in resistance thereof for various read currents
• 10 Fig. 13 is a graph showing a relationship between time and voltage drop across a phase change element for phase change elements of different resistance.
• 11th Fig. 13 is a graph showing a relationship between time and voltage change for bit lines of different capacities.
• 12th is a block diagram for an interconnection of a memory cell shown in 2 is shown in accordance with a fourth alternative embodiment of the present invention.

DETAILED DESCRIPTION

In 1 Figure 3 is a simplified block diagram of an integrated circuit 10 in which the present invention may be implemented. The circuit 10 closes a memory cell array 12th one implemented using phase change memory cells (not shown) on a semiconductor substrate, as discussed in more detail below. A word line decoder 14th electrically communicates with a plurality of word lines 16 . A bit line decoder 18th electrically communicates with a plurality of bit lines 20th to read data from the phase change memory cells (not shown) in the memory cell array 12th to read out or to write in this. Addresses are on a bus 22nd to word line decoders and drivers 14th and to the bit line decoder 18th delivered. Sense amplifier and data input structures in one block 24 are via a data bus 26th with the bit line decoder 18th tied together. Data is received via a data entry line 28 of input / output ports on the integrated circuit 10 or from other data sources inside or outside the integrated circuit 10 to data entry structures in the block 24 delivered. Other switching devices 30th can in the integrated circuit 10 be included, for example a general purpose processor or a special purpose circuit or a combination of modules that provide a one-chip system functionality that is supported by the memory cell array 12th is supported. Data are sent via a data output line 32 from the sense amplifiers in the block 24 to input / output ports on the integrated circuit 10 or other data destinations inside or outside the integrated circuit 10 delivered.

One controller 34 , implemented in this example, which uses a bias array state machine, controls the application of bias supply voltages 36 such as read, program, erase, erase verify, and program verify voltages. One controller 34 can be implemented using special purpose circuitry as known in the art. In alternative embodiments, the controller comprises 34 a general purpose processor that may be implemented on the same integrated circuit to execute a computer program for controlling the functions of the device. In another embodiment, a combination of a special purpose logic circuit and a general purpose processor can be used to implement the controller 34 be used.

As in 2 shown, each of the memory cells of the memory cell array closes 12th an access transistor (or other access device such as a diode), four of which are used as 38 , 40 , 42 and 44 are shown, as well as a phase change element shown as 46 , 48 , 50 and 52 is shown. Source terminals of each of the access transistors 38 , 40 , 42 and 44 are shared with a source line 54 connected in a source line termination 55 ends. In another embodiment, the source lines of the selection devices are not electrically connected, but can be controlled independently of one another. A multitude 16 of word lines, including word lines 56 and 58 , runs parallel in a first direction. The word lines 56 and 58 communicate electrically with a word line decoder 14th . The gate connections of access transistors 38 and 42 are with a common word line, for example a word line 56 , connected, and the gate Connections of the access transistors 40 and 44 are common to a word line 58 tied together. A multitude 20th of bit lines, including bit lines 60 and 62 , have one end at which phase change elements 46 and 48 with the bit line 60 are connected. More precisely is the phase change element 46 between the drain connection of the access transistor 38 and the bit line 60 switched and is the phase change element 48 between the drain connection of the access transistor 48 and the bit line 60 switched. Likewise is the phase change element 50 between the drain connection of the access transistor 42 and the bit line 62 switched, and is the phase change element 52 between the drain connection of the access transistor 44 and the bit line 62 switched. It should be noted that, to simplify the discussion, four memory cells are shown and that the memory cell array 12th can have billions of such memory cells in practice. Other memory cell array structures can also be used, e.g. B. the phase change memory element could be connected to a source connection.

Regarding 3 becomes a basic structure of an example of an implementation of access transistors 38 , 40 , 42 and 44 and phase change elements 46 , 48 , 50 and 52 in memory cells of the memory cell array 12th with reference to access transistors 38 and 40 and phase change elements 46 and 48 discussed. This example uses access transistors 38 and 40 formed using standard semiconductor processes such as those used for producing circuits on a p-type semiconductor substrate 64. For this purpose, an n-type region 66 defines a common source region, and n-type regions 68 and 70 define the drain regions of access transistors 38 respectively. 40 . Polysilicon layers 72 and 74 form word lines 56 and 58 and define the gate connections of access transistors 38 respectively. 40 . A dielectric fill layer (not shown) is over polysilicon layers 72 and 74 educated. The fill layer (not shown) is patterned, and conductive structures, including a common source line 78 and contact structures 80 and 82 are trained. The conductive material can be tungsten or consist of other materials and combinations that are suitable for the contact and line structures. In other embodiments, the common source line may comprise a buried diffusion with a silicide layer or other conductive line structures. The common source line 78 communicates electrically with the connector 66 that functions as a source region and corresponds to a source line 54 of the memory cell array 12th . Any of the contact structures 80 and 82 is electric with areas 68 respectively. 70 tied together. The filler layer (not shown), the common line 78 and the contact structures 80 and 82 In the example shown, they have a generally planar upper side, which is suitable for the formation of an electrode layer 84 suitable.

The electrode layer 84 has electrode elements 86 , 88 and 90 on that by electrically insulating walls 92 and 94 held by an electrically insulating base element 96 go out, are isolated from each other. The basic element 96 may be thicker than the walls in the embodiment of the structure 92 and 94 and separates the electrode element 88 from common source line 78

A thin film bridge 98 made of storage material such as Ge ₂ Sb ₂ Te ₅ (GST) lies over the electrode layer 84 , and extends from the electrode member 88 starting over the wall 92 (including the element 35A) away, in a direction away from the electrode member 90 to over the electrode element 86 . This is how the thin film bridge defines 98 a phase change element 46 . A thin film bridge 100 made of storage material, such as GST, lies over the electrode layer 84 , and extends from the electrode member 88 starting over the wall 94 (including the element 35B) away, in a direction away from the electrode member 86 to over the electrode element 90 . This is how the thin film bridge defines 100 a phase change element 48 .

A dielectric filler layer (not shown) overlies the thin film bridges 98 and 100 . The dielectric fill layer (not shown) comprises one or more layers of silicon dioxide, a polyimide, a silicon nitride, or other protective and dielectric fill materials. In embodiments, the filling layer provides thermal and electrical insulation for the thin-film bridge 98 and the thin film bridge 100 . A tungsten contact 102 electrically communicates with the electrode element 88 . A patterned conductive layer 104 , comprising metal or other conductive material, including bit lines in a memory cell array structure, overlies the dielectric fill layer (not shown). The patterned conductive layer 104 is electrical with the contact 102 connected to access those with the thin film bridges 98 and 100 to enable implemented memory cells. The drain connection of the access transistor is more precise 38 electrically with the electrode element 86 connected, in turn via the thin-film bridge 98 electrically with the electrode element 88 connected is. Likewise is the drain connection of the access transistor 40 electrically with the electrode element 90 connected, in turn via the thin-film bridge 100 electrically with the electrode element 88 connected is. The electrode element 88 is electrical with a bit line 60 tied together. By doing schematic circuit diagram in 2 is the electrode element 88 in separate locations on the bit line 60 shown. It should be made clear that in other embodiments separate electrode elements can be used for the separate memory cell bridges. The thin film bridge memory elements in the illustrated embodiment can in the example circuit by a number of other memory element structures, including columnar memory elements between electrode elements, conventional bottom electrode heater type elements comprising small electrodes connected to a larger block of phase change material, and so-called "pores" -Cells in which the contact area between an electrode and the phase change material is formed in a small pore in an intermediate layer.

Is in operation with each phase change element 46 , 48 , 50 and 52 associated with a data state. The data state can be determined by comparing the bit line voltage of a bit line for a selected memory cell, which is coupled to a measurement node, with a suitable reference voltage. The reference voltage can be set up in such a way that a predetermined range of bit line voltage levels corresponds to a logical value “00”, a different range of bit line voltage levels corresponds to a logical value “01”, and a different range of bit line voltage levels corresponds to a logical value “10” corresponds to and a different range of bit line voltage levels corresponds to a logic value “11” in order to create four states corresponding to two bits of information. In another embodiment, any number of states greater than two can be used to store more than one bit of information in the memory cell. Logical values of the individual memory cells are established as a function of the physical properties of the phase change element. As stated above, the resistance of each phase change element can be 46 , 48 , 50 and 52 by controlling the relative proportions of amorphous and crystalline phases of the material in the volume of the phase change element. More precisely, the material from which the phase change elements 46 , 48 , 50 and 52 are formed, are changed so that it is present in a highly amorphous phase, a highly crystalline phase and in one or more intermediate forms which have mixtures of amorphous and crystalline phases. The term crystalline phase is used to denote a relatively ordered structure and a lower electrical resistance compared to the amorphous state.

In the highly amorphous phase there is a voltage drop across the phase change elements 46 , 48 , 50 and 52 , which corresponds to a predetermined data state, e.g. B. can correspond to a logical “11” or a logical “00”. In the highly crystalline phase is the voltage drop across the phase change elements 46 , 48 , 50 and 52 less than in the amorphous phase, and this may correspond to a data state that is different from the data state associated with the highly amorphous phase. It is often desirable to have intermediate states with the phase change elements 46 , 48 50 and 52 are associated. This is achieved by providing the phase change elements with different ratios of crystalline to amorphous phase. As a result, each of the intermediate phases, as well as the highly amorphous and highly crystalline phases, have different ratios of crystalline and amorphous material associated with them, and therefore different resistance ranges corresponding to the different data states. Thin-film bridges are usually used for this purpose 98 and 100 formed from chalcogenides or chalcogenide alloys.

Chalcogenides comprise compounds of chalcogen with a more strongly electropositive element or radical, it being agreed that chalcogens are any of the four elements oxygen (O), sulfur (S), selenium (Se) and tellurium (Te) that are part of the group VI of the Periodic Table of the Elements. Chalcogenide alloys include combinations of chalcogenides with other materials, such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the Periodic Table of the Elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations with one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change storage materials have been described in the technical literature, including the alloys: Ga / Sb, Ge / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te, Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te and Te / Ge / Sb / S. A wide range of alloy compositions can be useful in the Ge / Sb / Te alloy family. The compositions can be characterized as Te _a Ge _b Sb _{100- (a + b)} .

One researcher has described the most suitable alloys as having an average Te concentration in the deposited material of well below 70%, usually below 60% and generally in a range of as little as about 23% to about 58%. Te and most preferably have about 48% to 58% Te. Ge concentrations ranged above about 5% and ranged from as little as 8% to about 30% in the material, generally remaining below 50%. Most preferred were the Ge concentrations at about 8% to about 40%. The remainder of the main constituent elements in this composition was Sb. These percentages are atomic percentages that make up 100% of the atoms of the constituent elements as a whole. Specific alloys that have been evaluated by another researcher include Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te _4, and GeSb ₄ Te ₇ ( Noboru Yamada "Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-Rate Recording", SPIE v. 3109, pp. 28-37, 1997 ). More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof can be combined with Ge / Sb / Te to form a phase change alloy that has programmable resistive properties.

An example method for the formation of chalcogenide material uses a PVD sputtering or magnetron sputtering method with Ar, N ₂ and / or He etc. as the source gas (s) at a pressure of 1 mTorr ~ 100 mTorr.

Phase change alloys can be changed from one resistance state to another resistance state by the application of electrical pulses. It has been observed that shorter, higher amplitude pulses are more likely to change the phase change material to a generally amorphous phase. A longer, lower amplitude pulse is more likely to change the phase change material to a generally crystalline phase. The energy in a shorter, higher amplitude pulse is high enough to break bonds in the crystalline structure and short enough to keep the atoms from realigning themselves in a crystalline phase. Suitable pulse profiles that are specially designed for a certain phase alloy can be determined without unreasonable experimentation.

Reading or writing from or into a memory cell of the memory cell array 12th is therefore achieved by having a suitable selection voltage on one of the word lines 56 or 58 is applied and one of the bit lines 60 and 62 is connected to a power source. The level and duration of the current flowing on one of the connected bit lines 60 and 62 depends on the operation being performed, e.g. B. a read operation or a write operation, if it is assumed that a logical “1” is the data state for one of the phase change elements 46 , 48 , 50 and 52 is. The change in the state of the data associated with one of the phase change elements 46 , 48 , 50 and 52 associated with a logical “1” would be the crystallization of a desired part of the volume of the thin-film bridge 98 require. The word line decoder 14th would supply the word line 56 with a suitable voltage level to an access transistor 38 to activate, enable. The bit line decoder 18th would be the supply of a current pulse to the bit line 60 with suitable amplitude and duration to the temperature of the active region in the thin film bridge 98 between the glass transition temperature and the melting temperature of the material from which it is made to increase sufficiently to increase a desired part of the volume of the thin-film bridge 98 to crystallize, allow. This would become the phase change element 46 associate with a data status of a logical "0". The bit line decoder enables this 18th the supply of a current of suitable magnitude and duration to control the temperature of the active region of the thin film bridge 98 about increasing the melting temperature of the material from which it is made, while allowing its rapid cooling, allowing recrystallization of the thin-film bridge 98 to prevent while this reaches a temperature below the glass transition temperature. The intermediate data states are created by varying the amplitude and / or duration of the write pulse to achieve a desired ratio of crystalline component to amorphous component in the individual phase change elements 46 , 48 , 50 and 52 to get achieved.

4th Figure 3 is a simplified schematic of a measurement architecture for controlling the total energy fed into a multibit cell during a read cycle. In the simplified scheme, an access device and a phase change element for a memory cell are provided by a transistor 38 , the one with a word line 56 connected, or by a variable resistor 46 (which represents the phase change element) is modeled. The bit line circuit is created by the resistor / capacitor network 60 modeled. A bit line decoder 18th serves to connect a selected bit line to a measurement node in response to address signals. The measuring node 116 is via a switching transistor 112 with a power source 114 tied together. The measuring node 116 is also with the input of a sense amplifier 118 connected, which is used to compare the voltage of the measuring node with a reference voltage V _REF , which is applied by a reference voltage circuit, not shown, and to generate _{a data output signal D OUT.} The switching transistor 112 is made by a logic circuit 110 controlled (modeled by an AND gate in the figure), which has a first input coupled to a read enable signal 108 , and one with the output of a detector 121 having coupled second active-low input. The entrance of the detector 121 is with the measuring node 116 tied together. The detector 121 outputs a logic high level when the measuring node 116 its ignition or release voltage crosses. Thus there is a current pulse from the power source 114 to a measuring node 116 applied and from the measuring node 116 through the decoder 18th and the bit line circuit 60 to a selected memory cell 46 delivered. The current pulse has a strength that is determined by the current source 114 is controlled, and is substantially constant in embodiments of the technique described herein. The current pulse has a pulse width determined by the logic circuit 110 in response to the read enable signal at the input 108 which is an output from the detector 121 acts, is controlled. A time lapse for the operation of the measurement architecture of 4th is in 5 shown. Thus, as in 4th and 5 shown, during a read operation, a read current pulse IBL is applied to the selected bit line, which has a suitable amplitude and duration to the sense amplifier 118 to enable it to measure a voltage on the selected bit line. The voltage level which is present on the selected bit line depends on the resistance of the phase change element of the selected memory cell and thus on the data state associated therewith. For example, reading a data state associated with the phase change element is obtained from the resistor 46 is modeled, achieved by having a control signal, such as a read enable signal 106 , at an entrance 108 a logical one

circuit 110 and also a word line address signal to a word line decoder 14th applies to a selected word line 56 and a bit line address signal to the bit line decoder 18th applied to a selected bitline 60 with the measuring node 116 connect to. A control signal 106 leads to activation of a switching transistor 112 having a power source 114 electrically with the measuring node 116 connects. One input of a sense amplifier 118 is connected to a voltage at the measuring node 116 and to compare it to a reference voltage VREF to provide a required output to DOUT which is a data state of the phase change element 46 is equivalent to. In a multi-bit cell, the reference voltage VREF is determined by reference voltage sequencing circuits 119 so that they are supplied in a sequence from a first value V _REF1 , which is used to distinguish between the phase with the lowest resistance and a first intermediate phase, a second value V _REF2 , which is used to distinguish between the first intermediate phase and a second intermediate phase, and a third value V _REF3 , which is used to distinguish between the second intermediate phase and a phase with the highest resistance, is changed. Such sequencing circuits 119 can be implemented using voltage dividers and switches under the control of a read state machine or other techniques. The detector 121 has a normally low output signal in the illustrated embodiment, which rises to a high level when the measuring node 116 a release voltage is reached. When the detector 121 When a high output signal is generated, the switching transistor is turned off, reducing the power source 114 from the measuring node 116 is disconnected and the read cycle is ended. In one embodiment the detector operates 121 with a trigger level that is switched to match the reference voltage applied during the read cycle, as in FIG 5 is shown. In one example, three detectors are connected in parallel with respective trip levels and are activated in the same sequence that the reference voltage is applied. The detector operates with trigger levels that ensure that the voltage drop across the phase change element that occurs during reading never exceeds the threshold value of the phase change material in the amorphous state.

und
wo P die Leistung in Watt ist, I der Strom in Ampere ist und R der Widerstand in Ohm ist. Es ist ersichtlich, dass die Leistung P, der die Phasenänderungselemente 46, 48, 50 und 52 ausgesetzt werden, quadratisch mit dem Strom zunimmt. Unter der Annahme einer konstanten Stromstärke bestimmen die Zeit, über welche die Phasenänderungselemente 46, 48, 50 und 52 dem konstanten Strom ausgesetzt werden, und der Widerstand der Elemente die Energiemenge, der die Phasenänderungselemente 46, 48, 50 und 52 ausgesetzt werden. Um die Energie zu steuern, der die Phasenänderungselemente 46, 48, 50 und 52 während eines Lesezyklus ausgesetzt werden, werden die Dauer und die Stärke des Stroms in der hierin beschriebenen Messarchitektur gesteuert.One problem that is overcome by the present invention relates to the data state consistency of the phase change elements 46 , 48 , 50 and 52 in the presence of the reading stream. The resistance of the phase change elements 46 , 48 , 50 and 52 in the intermediate state can change in the presence of a read current. The read current can generate enough heat in the phase change element in each read cycle to cause a portion of the amorphous region of the phase change element to crystallize, thereby lowering the resistance of the phase change element. This requires the use of a large voltage range for each data state, which reduces the read range and in some cases causes the cell to switch to a different, undesired data state. The heat generated on the phase change element is due to the total energy to which the phase change element is exposed. The energy is the power integrated over time to which the phase change element is exposed. Therefore, it is determined by the resistance of the phase change element, the strength of the read current and the pulse width of the read current. The applied power is determined by the following known relationship: $$\text{P.}={\text{I.}}^2\text{R.};$$

and
where P is the power in watts, I is the current in amps, and R is the resistance in ohms. It can be seen that the power P, which the phase change elements 46 , 48 , 50 and 52 exposed, increases quadratically with the current. Assuming a constant current strength determine the time over which the phase change elements 46 , 48 , 50 and 52 be exposed to the constant current, and the resistance of the elements is the amount of energy that the phase change elements 46 , 48 , 50 and 52 get abandoned. To control the energy of the phase change elements 46 , 48 , 50 and 52 are suspended during a read cycle, the duration and magnitude of the current are controlled in the measurement architecture described herein.

For this purpose is the power source 114 In the embodiment shown, it is designed as a constant current source. The constant current source supplies to the selected bit line, for example 1 Microamps of current with a fluctuation of no more than ± 5%. Alternatively, the power source 5 Provide microamps of current with a fluctuation of no more than ± 5%. In addition, the power source 10 Provide microamps of current with a fluctuation of no more than 5%. For this purpose, the in 4th Current source shown is a current mirror 214 who is in 6th is shown, or a field effect transistor 314 who is in 7th and which is biased to operate at a constant current source. It should be understood that any other constant current source may be provided, including circuits including JFETs and bipolar transistor circuits as are known in the art. The strength of the constant current source is selected depending on the properties of the memory cell, the properties of the memory cell array, the speed requirements for the operation of the device and other design parameters. In this embodiment, the pulse of the read current in response to the read enable signal RE has an essentially constant strength 147 and ends in response to the output of the detector 121 .

For example, the read enable signal rises during the duty cycle DC 106 who is in 5 shown is the bit line voltage signal 136 a bit line 60 at the measuring node 116 , indicated by the rising edge 136 , to an amplitude, which is referred to herein as the stabilization voltage 13th referred to as. The rise time of the rising edge of the voltage signal 136 depends on the strength of the current pulse in the read cycle, the physical parameters of the bit line 60 and the resistance of the phase change element. The stabilization tension 138 on the bit line 60 is shown to be below the reference voltage V REF1 and thus below a _{read termination voltage V RT1} that the detector 121 for the entire duty cycle DC of the read enable control signal 106 controls. The amplitude of the stabilization voltage 138 remains below the read termination voltage V _RT1 as the phase change element 46 is in the highly crystalline state with the lower resistance, which leads to a lower voltage drop. As a result, the read current pulse keeps 147 of the read signal for the duration of the duty cycle of the read control signal 106 a constant level.

The timing for the measurement of a first intermediate state is with reference to the graph of a bit line voltage signal 146 shown. This corresponds to the phase change element 46 in an intermediate state with a higher resistance than a cell in a highly crystalline phase, but a relatively lower resistance than another intermediate state. As in 5 shown, the bit line voltage signal 146 a peak voltage 148 which is greater than the read termination voltage V _RT1 . When the first final reading voltage is reached, the reading current pulse is 150 ended, so that the amount of energy that is supplied to the memory cell is limited during the measurement of the intermediate state.

The timing for the measurement of a second intermediate state is with reference to the graph of the bit line voltage 170 shown. The bit line voltage 170 is shown so that it reaches a peak voltage during the read current pulse 172 runs up through a second _{read termination voltage} V RT2 that is higher than the first read termination voltage. The second _{read termination voltage} V RT2 is selected to ensure that the measurement node 116 exceeds the second reference voltage V _{RT2 in} order to enable an exact acquisition of the data on the bit line. It can be seen that the bit line voltage is ramping up 170 until the _{final reading voltage V RT2 is reached} , the read current 155 ends before the duty cycle of the read enable signal ends, as a result of which the amount of energy which is supplied to the memory cell during the measurement of the second intermediate state is limited.

The timing for the measurement of a high impedance condition is with reference to the graph of the bit line voltage 175 shown. The bit line voltage 175 is shown in such a way that it is during the read current pulse 176 runs up until it reaches a third read termination voltage V _RT3 . The third _{read termination voltage V RT3} is selected to ensure that the measurement node 116 the third reference voltage V _RT3 exceeds, so that an exact detection of the data on the bit line is possible. After reaching the third final reading voltage, the reading current pulse is 160 ended, ending the read cycle.

In an alternative embodiment, the detector is 121 configured to detect only the third read termination voltage V _RT3 . In this alternative embodiment, the pulse width of the read current is nevertheless controlled in a similar manner. Measuring the state of the memory cell can be based on time, with the Read termination voltage V _{RT3 is} reached faster for higher resistance states.

8th shows an alternative embodiment of the measurement architecture in which the output signal of the sense amplifier is on a line 120 to the logic circuit 122 is fed back, which is used to make the switching transistor 112 to control. In the embodiment of 8th the function of the detector in 4th is shown, from the sense amplifier 118 Fulfills. Otherwise the implementations are similar. Thus, as in 5 and 8th shown to regulate the time the phase change element is exposed to the sense current, a feedback line 120 used by what DOUT from the sense amplifier 18th with a logic circuit 122 is connected. The feedback line 120 has the function of sending a read completion signal to the logic circuit 122 to send. The read completion signal terminates the control voltage to the switching transistor 112 . In response to this, the logic circuit operates 122 termination of the pulse of the read current on the selected bit line.

It should be made clear that a minimum duty cycle exists for the read current in order to determine the data state for one of the phase change elements 46 , 48 , 50 and 52 to capture exactly and to meet reading speed restrictions in a construction. For example, in a representative example, it is desired that the voltage level at the measuring node 116 is measured differs by at least 50 millivolts for any two data states. The amount of change in resistance required in the phase change element to make the 50 millivolts difference is a function of the read current. With reference to the diagram of 9 the voltage drop across the phase change element of approximately 50 millivolts for a read current of approximately 1 microamp indicates that the phase change element has undergone a change in resistance of approximately 50,000 ohms. As expected, however, a higher read current, for example 5 microamps and 10 microamps, as in the diagram of FIG 9 may require a lower resistance for a 50 millivolt change in voltage drop across the phase change element. However, before a low resistance condition is detected, sufficient time must be allowed to ensure that the sense node 116 has reached a stabilization voltage, ie a voltage the strength of which is substantially stable. This depends in part on the read current, as well as the resistance of the phase change element and therefore the data state of the phase change element. As with the curve in 10 It can be seen that with a 5 microampere read current, it takes about 20 nanoseconds for the phase change element to stabilize at about 10,000 ohms in voltage. For a phase change element of approximately 20,000 ohms, it takes nearly 40 nanoseconds for voltage stabilization to take place. Thus, the read cycle duration, which is determined by the read enable signal in the embodiment described above, must be long enough so that the cell with the lowest resistance can be read.

As in 4th shown, the bit line 60 be modeled by an RC circuit that has a capacitance and a resistance that is determined by a resistor 126 and from a capacitor 128 being represented. 11th shows a graph in which the slope of the lines 230 , 232 and 234 corresponds to a read current of about 5 microamps, and demonstrates that a bit line with a capacitance of 500 femtofarads takes at least 10 nanoseconds longer to reach a stabilization voltage than a bit line with a capacitance of 300 femtofarads, and at least five times longer than a bit line with a capacity of 100 femtofarads. The lines 236 , 238 and 240 correspond to a read current of approximately 10 microamps. As expected, it can be seen that the time for voltage stabilization is shorter, the stronger the read current. For example, a comparison of the line shows 234 with the line 240 that a bit line with a capacitance of 500 femtofarads compared to that of a 5 microampere read current reaches a stabilization voltage for a 10 microampere read current in less than half the time. This is also true for bit lines, which have a lower capacitance, as by comparing the slope of the lines 232 and 238 and the slope of the lines 230 and 236 evident.

12th Figure 12 shows a comparative example of a measurement architecture for controlling the amount of total energy applied to the phase change cell during a read cycle. The comparative example from 12th however, it is not covered by the wording of the claims. In the in 12th The comparative example shown have components that are also the embodiment of 4th has the same reference numerals. Thus, a memory cell and a bit line are passed through the components 38 , 46 and 60 modeled. A bit line decoder 18th serves to select a selected bit line 62 with a measuring node 116 connect to. The power source 114 delivers a read pulse through the switching transistor 120 to the measuring node 116 . The logic circuit 122 responds to a read enable signal at the input 108 and for a read complete signal on the line 220 to send a control signal to the gate of the switching transistor 112 to put on. In the in 12th illustrated embodiment are a plurality of sense amplifiers 221 , 222 , 223 operated in parallel, with respective reference voltages V _REF , V _REF2 and V _REF3 for a high speed measurement. Outputs D1 , D2 and D3 are applied in parallel to a logic (not shown) which decodes the multiple data states in a measured memory cell. The function of the detector 121 from 4th is by reporting back the output of the sense amplifier 223 on the line 220 to the logic circuit 122 provided. Thus, the read termination voltage for all data states in the in 12th illustrated embodiment V _REF3 .

Although the present invention is disclosed with reference to its preferred embodiments and examples set forth above, it should be understood that these examples are only intended to be illustrative and not to be construed as limitations. It is contemplated that modifications and combinations will be obvious to one skilled in the art, such modifications and combinations being within the spirit of the invention and within the scope of the following claims.

Claims (10)

A storage device comprising: a memory cell (46) which is coupled to a bit line (60, 62) and a word line (56, 58) and which comprises a phase change material (98, 100), the memory cell having a first cell state in which it has a high resistance having at least a second cell state in which it has a medium resistance and a third cell state in which it has a low resistance, the high resistance being higher than the medium resistance and the medium resistance being higher than the low resistance; a sense amplifier (118) having a reference input for receiving a reference voltage (VREF) and coupled to a sense node (116) for sensing a voltage at the sense node (116) relative to the reference voltage (VREF); a circuit for applying the reference voltage (VREF) to the reference input, the reference voltage in a sequence of a first value (VREF1), which is used to distinguish between the first cell state and the second cell state, and a second value (VREF3) used to distinguish between the second cell state and the third cell state; circuitry (18) for selectively bringing the bit line (60, 62) into signal communication with the sense node (116); a current source (114) to generate a read current; a switch (112) coupled to selectively apply the read current to the sense node (116); and a circuit (100, 112) which is coupled to the switch (112) for controlling the length of a read current pulse, the circuit (110, 112), in response to a detection of a threshold voltage at the measuring node (116), the switch (112) in such a way controls that the electrical connection between the current source (114) and the measuring node (116) is terminated so that the resistance state of the memory cell does not change as a result of the read current pulse, wherein the threshold voltage is switched in such a way that it corresponds to the reference voltage which is applied to the reference input in a read cycle. Storage device according to Claim 1 wherein the circuit comprises a detector coupled to the measurement node to detect a voltage at the measurement node, and logic that causes the switch to terminate electrical communication of the power source with the measurement node when the detected voltage at the measurement node the threshold voltage is reached. Storage device according to Claim 1 the circuit including logic responsive to a read enable signal indicative of a start of the read cycle to control the switch to selectively bring the power source into electrical communication with the sense node, the logic being responsive to an output from the sense amplifier to cause the switch to terminate electrical communication of the power source with the measurement node. Storage device according to Claim 1 , the circuit comprising a detector coupled to the sense node to detect a voltage at the sense node and logic responsive to a read enable signal indicating the start of a read cycle to control the switch to operate the Selectively bringing the power source into electrical communication with the measurement node, the logic being responsive to an output from the detector to cause the switch to terminate electrical communication of the power source with the measurement node when the sensed voltage at the measurement node reaches the threshold voltage. Storage device according to Claim 1 wherein the current source comprises a current mirror. Storage device according to Claim 1 wherein the current source comprises a field effect transistor which is biased to act as a constant current source. A method for reading a memory cell (46) which is coupled to a bit line (60, 62) and a word line (56, 58) and which comprises a phase change material (46, 48, 50, 52), wherein the Memory cell (46) has a first cell state in which it has a high resistance, at least a second cell state in which it has a medium resistance, and a third cell state in which it has a low resistance, the high resistance being higher than the medium Resistance and the mean resistance is higher than the low resistance, and the method comprising: coupling the memory cell (46) to a sense node by selectively establishing signal communication of the bit line (60,62) with the sense node (116); Applying a read current to the memory cell (46) to read the cell state, the application including connecting a current source (114) to the sense node (116); Detection of a voltage at the measuring node relative to a reference voltage (VREF) by a sense amplifier, the reference voltage in a sequence of a first value (VREF1), which is used to distinguish between the first cell state and the second cell state, and a second value (VREF3), which is used to distinguish between the second cell state and the third cell state; and controlling the length of a read current pulse, wherein the controlling includes detecting a voltage at the measuring node (116) and, in response to detecting a threshold voltage at the measuring node (116), separating the current source (114) from the measuring node so that the cell state of the memory cell is through the Read current pulse does not change, the threshold voltage being switched in such a way that it corresponds to the reference voltage that is applied to the reference input in a read cycle. Procedure according to Claim 7 wherein a strength of the current is further controlled to predetermined level ranges for a predetermined period of time. Procedure according to Claim 7 wherein the strength of the read current pulse is controlled in such a way that crystallization of a volume of the phase change material to an extent that would result in a change in a data state derived from the resistance state of the memory cell is prevented. Procedure according to Claim 7 wherein the strength of the read current is kept essentially constant during the reading of the memory cell.

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