DE102008011926B4 - A method of making a high-k layer of lesser thickness for patterning a dielectric material in the fabrication of transistors - Google Patents

Abstract

Method with:
Forming a dielectric layer having an ε greater than 10 (331) over a first transistor (350a) and a second transistor (350b) of a semiconductor device (300);
Forming a first strain-inducing layer (330) on the dielectric layer having an ε greater than 10 (331), the first strain-inducing layer (330) deforming in a channel region (353) of the first and second transistors (250, 350a, 350b) generated;
Removing a portion of the first strain-inducing layer (330) from above the second transistor (350b) using the dielectric layer having an ε greater than 10 (331) as an etch-stop material,
Forming an opening (322) in the first strain-inducing layer (330) and
Removing a portion of the dielectric layer having an ε greater than 10 exposed through the opening (322) by performing a sputter etch process (306).

Description

Field of the present invention

in the In general, the present invention relates to the field of integrated Circuits and in particular relates to field effect transistors and Manufacturing method based on dielectric layers, in the fabrication of modern transistor structures, such as transistors, which require high strain levels in the channel region.

Description of the state of the technology

integrated Circuits are typically constructed from a large number of circuit elements, on a given chip area according to a specified circuit configuration are arranged, wherein in complex circuits of the field effect transistor represents an essential circuit element. In general will be a variety of process technologies for modern semiconductor devices currently used, where for complex circuits based on field effect transistors, in microprocessors, memory chips and the like, the CMOS technology currently one of the most promising solutions due to the good Properties with regard to the working speed and / or Power consumption and / or cost efficiency is. During the Production of complex integrated circuits using the CMOS technology becomes millions of complementary transistors, i. H. n-channel transistors and p-channel transistors made on a substrate containing a crystalline semiconductor layer having. A field effect transistor includes, regardless of whether an n-channel transistor or a p-channel transistor is considered, so-called pn junctions by an interface heavily doped drain and source regions with one inverse or weak doped channel area formed between the drain area and the source region. The conductivity of the channel region, i. H. the forward current of the conductive channel is through a gate electrode controlled, over the channel region and formed by a thin insulating layer is disconnected. The conductivity of the channel region in the construction of a conductive channel due to the Applying a suitable control voltage to the gate electrode depends on the dopant concentration, the mobility of the majority carriers - and for a given Dimension of the channel region in the transistor width direction - of the Distance between the source area and the drain area, which also as channel length referred to as. Thus, in conjunction with the ability rapidly a conductive channel under the insulating layer at Establish concerns of the control voltage at the gate electrode, the conductivity of the channel region substantially the performance of the MOS transistors. This is the reduction of the channel length - and linked to the Reduction of channel resistance - an essential design criterion, an increase in the working speed of integrated circuits to reach.

However, the reduction in transistor dimensions entails a number of associated problems that need to be addressed so as not to undesirably cancel out the benefits achieved by steadily reducing the channel length of MOS transistors. A problem in this regard is that the small-sized features are to be patterned based on modern lithography techniques in conjunction with complex etching processes. That is, typically, material layers, such as dielectric materials, semiconductive materials; Metals and the like, and subsequently patterned into device features using appropriate etch masks. For example, photoresist material is often used as an etch mask, which in turn is patterned by utilizing the photochemical properties of the paint material to create a latent image in the paint which is then "etched" or developed to remove unwanted areas of the paint material. The resulting mask is then used as a template for the etching of the underlying material so as to transfer the mask feature into the underlying material layer with a high degree of precision, which depends on the etching environment used for the etching process. In order to enable reproduction of the mask feature with an adjustable sidewall angle of the etched feature, plasma enhanced "dry etch" techniques have been developed in which a plasma environment based on a reactive gas component is established. The particles react with the surface to be etched, typically with the environment giving a different rate of removal for different materials in contact with the reactive plasma environment. Furthermore, ions are accelerated in the direction of the surface to be etched, which likewise achieves a "physical" component with regard to the removal rate, which contributes to an increased directional dependence of the ablation process. Furthermore, suitable polymer substances are added which also allow an adjustment of the directional dependence of the etching front, thereby enabling a very "anisotropic" etching behavior. The mechanism of plasma etching depends on the ability of the reactive component to form a volatile etch byproduct that is released into the environment to increasingly remove material from the exposed surface. Often, it is important to lower underlying materials before Einwir The plasma environment must be protected or a defined depth must be maintained to complete the etching process over the entire substrate, which is typically achieved by providing an etch stop layer, which is to be understood as a material having a significantly lower removal rate compared to the material owns that is actually to be etched in the plasma environment.

By the ever smaller feature sizes require the deposition of material layers over pronounced Surface topographies, if applicable also a smaller layer thickness of the actual material layers and in particular the etch stop layers.

One Another problem associated with the smaller gate lengths is the occurrence so-called short channel effects leading to a lower controllability the channel conductivity to lead can. Short channel effects can be compensated by certain design techniques, of which, however some are associated with a reduction in channel conductivity, which Sometimes the benefits are eliminated by reducing the critical dimensions are achieved.

in view of This situation has been suggested that the device performance the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region at a given channel length, thereby also the forward current and thus the transistor performance increases. For example For example, the lattice structure in the channel region can be modified by For example, a tensile deformation or a compressive deformation therein be generated, resulting in a modified mobility for electrons or holes leads. For example, increased generating a tensile strain in the channel region a silicon layer, the one standard crystal configuration possesses the mobility of electrons, which in turn directly in a corresponding increase in the conductivity of the n-type transistors effect. On the other hand, a compressive deformation in the channel region can Agility of holes improve, eliminating the possibility is created to improve the performance of p-type transistors.

A Efficient approach in this regard is a technique that producing desired Stress conditions within the channel region different Allows transistor elements, by the stress properties of a dielectric layer stack be set over the basic transistor structure is formed. The dielectric Layer stack contains typically one or more dielectric layers that are close are arranged on the transistor and also for controlling a corresponding etching process can be used around contact openings to create the gate and the drain and source terminals. Thus, can an effective control of the mechanical stress in the channel areas, d. H. an effective bracing technology, be realized by adjusting the internal tension of these layers individually which is also referred to as a contact etch stop layer and by using a contact etch stop layer with an internal compressive strain across a p-channel transistor is arranged while a contact etch stop layer with an inner tensile deformation over an n-channel transistor is arranged, whereby in the respective Channel areas a compressive deformation or a tensile deformation is produced.

typically, becomes the contact etch stop layer by plasma-assisted chemical vapor deposition processes (PECVD) formed over the transistor, d. H. above the gate structure and the drain and source regions, such as silicon nitride due to its high etch selectivity with regard to is used on silicon dioxide, which is a well-established dielectric Interlayer material is. Furthermore, PECVD silicon nitride may be used with a high internal strain of, for example, up to 2 gigapascals (GPa) or significantly higher at compressive tension and up to a GPa and clearer higher in tension are deposited, with the nature and size of the internal tension efficient by selecting suitable deposition parameters can be set. For example are the ion bombardment, the deposition pressure, the substrate temperature, the gas flow rates and the like corresponding parameters, to achieve the desired inner tension can be used.

During the fabrication of these two types of strained layers, conventional techniques may show lower efficiency as component dimensions are increasingly reduced by using 45 nm technology and even more sophisticated solutions, due to the limited conformal deposition capabilities of the deposition processes involved may result in corresponding process non-uniformities during subsequent process steps to pattern the strained layer and to form contact openings, as described in more detail below with reference to FIGS 1a and 1b in which an in-house state of the art is shown.

1a schematically shows a cross-sectional view of a semiconductor device 100 in a certain manufacturing phase for the production of stress-inducing layers over several first transistors 150a and second transistors 150b , The transistors 150a . 150b are over a substrate 101 formed, over which a semiconductor layer 102 is provided, such as a silicon-based layer of the substrate 101 may be separated by a buried insulating layer when considering an SOI (silicon on insulator) configuration. In the example shown, the transistor elements 150a . 150b a gate electrode 151 on top of a gate insulation layer 152 is formed, which is the gate electrode 151 from a canal area 153 separates. The channel region is between drain and source regions 154 arranged by a suitable dopant type and a dopant profile according to the design requirements for the transistors 150a . 150b are constructed. For example, the transistors represent 150a Transistor elements formed in a high density package device area, such as RAM (random access memory) areas in modem semiconductor devices, may represent transistors of the same conductivity type, such as n-channel transistors, while the transistor 150b represents a transistor of a different conductivity type, such as a p-channel transistor. Thus, there are corresponding design rules during the fabrication of the semiconductor device 100 apply it to the transistors 150a . 150b to obtain suitable dimensions in order to achieve the desired overall performance of the device 100 as previously explained. For example, one gate length, ie, in 1a the horizontal dimension of the gate electrodes 151 , about 50 nm or less in demanding applications. Depending on the overall component configuration, the transistors may 150a Further, a spacer structure 155 have, on the side walls of the gate electrodes 151 is trained. Furthermore, metal silicide regions may be present in the drain and source regions and possibly in the gate electrodes 151 , depending on the overall structure of the transistors 150a . 150b be formed.

As previously discussed, transistor performance for a given design length of the transistor dimensions can be improved by providing a special type of strain in the respective channel regions 153 which is often achieved by providing a highly strained dielectric material over the transistor base structure as shown in FIG 1a is shown is provided. For this purpose, in the manufacturing stage shown, a dielectric layer 130 over the transistors 150a . 150b formed, with a high internal stress level of the layer 130 is chosen so that, for example, the performance of the transistors 150a is improved. If, for example, the transistors 150a represent n-channel transistors, a high internal stress level in the layer 130 generated, which then also in the channel areas 153 is transmitted, whereby a desired tensile deformation in the transistors 150a and in the transistor 150b is generated in which, however, a corresponding tensile deformation is not desired. Consequently, a part of the layer becomes 130 that is above the transistor 150b is located on the basis of modern plasma-based etching techniques removed. As previously discussed, efficient control of the respective plasma assisted etch processes and protection of sensitive device areas in the transistor 150b an etch stop layer 131 usually provided, the lower etch rate with respect to a particular plasma-based etch recipe compared to the material of the layer 130 having. With a view to suppressing unwanted damage to the transistor 150b becomes a thickness of the etching stopper layer 131 chosen so that a reliable stopping of the etching front within the layer 131 can be realized, which also has sufficient process tolerance ranges with respect to etching irregularities across the substrate 101 during a plasma assisted etch process.

During a process sequence for manufacturing the semiconductor device 100 , in the well-established process techniques for making the transistors 150a . 150b According to standard CMOS processes involved, the etch stop layer 131 For example, based on plasma-enhanced CVD (chemical vapor deposition), wherein a thickness is selected so that the desired Ätzstoppeigenschaft is achieved. For example, silica is a well-established stopping material with respect to a silicon nitride material during well-established plasma enhanced etching recipes, with a thickness set to 20 nm or more depending on the desired amount of process variations to be considered. Next, the strain-inducing layer 130 deposited, for example, as a silicon nitride material having the desired high internal stress level. However, it turns out that for demanding component geometries caused by the height of the gate electrodes 151 and the distance between dense gate electrode structures are created, demanding boundary conditions for the respective Abscheiderezepte be created. That is, process parameters for the plasma assisted CVD process to make the film 130 must be adjusted so that the desired high internal stress level is achieved and also the gap filling properties are provided, so that a spatial area 157 between adjacent transistor elements, ie between the corresponding gate electrode structures reliably with the material of the layer 130 is filled. A reliable filling of the room area 157 is not just in terms of the whole deformation-inducing mechanism important because a larger deformation in the channel region 153 is caused when a higher amount of strained material is sufficiently close to the channel region 153 but also with regard to the further processing steps in which a further dielectric material is deposited in a highly strained state, followed by the deposition of an interlayer dielectric material which in turn is patterned to be contact elements for the transistor elements 150a . 150b to accomplish. During the patterning process, irregularities, such as voids, caused by the deposition are generated, preferably in critical areas, such as an area 132 , and may represent the major contribution to significant yield losses in the manufacture of contact elements in modern semiconductor devices. Thus, in the deposition of the layer requires 130 the aspect ratio of the space area 157 a suitable adjustment of the layer thickness, whereby the amount of highly strained material is reduced, in the immediate vicinity of the transistors 150a can be arranged. Furthermore, the aspect ratio of the space area 157 be further increased by the etch stop layer 131 is provided in a moderately large thickness, thereby increasing the integrity of the transistor 150b in the subsequent structuring of the layer 130 sure.

1b schematically shows the semiconductor device 100 in a more advanced manufacturing stage, in which an etching mask 103 over the transistors 150a is formed while the transistor 150b the effect of the plasma-assisted etching environment 103 is exposed. Thus, during a final phase of the etching process 104 the etch stop layer 131 exposed and also subject to some degree of material removal, but at a significantly lower erosion rate, with some post etch time being applied to reliably remove unwanted areas of the layer 130 over the entire substrate 101 away. Consequently, by providing a sufficient thickness for the etch stop layer 131 a high degree of integrity of the transistor 150 achieved during the etching process 104 achieved, but which also deformation transfer mechanism in the transistors 150a is compromised because the thickness on the resulting surface topography after deposition of the layer 131 must be adjusted. As the component sizes continue to decrease, the ratio between the stop material and the highly strained dielectric material in the vicinity of the transistors may increase even further, further affecting the overall efficiency of the strain inducing mechanism. Thus, during the fabrication of the interlayer dielectric material over the completed transistor base configuration, a series of patterning processes based on plasma enhanced etching techniques must be performed, and the provision of an etch stop material will increasingly reduce the overall performance of the transistor elements, especially if strain-inducing mechanisms are considered.

The publication US 2007/0262391 A1 describes a semiconductor device with a field effect transistor having a piezoelectric layer over the gate electrode. The piezoelectric material is used as a stress-generating layer, which is patterned with an interlayer dielectric by ion etching.

The publication US 7 141 511 B2 describes a semiconductor device in which dielectric etch stop materials, e.g. B. Al ₂ O ₃ or HfO ₂ , are used in memory elements to prevent electrical connection to a buried conductive layer.

in view of The situation described above relates to the present invention Methods and semiconductor devices in which a suitable Ätzstoppverhalten while training is provided at the contact level, with some or Several of the problems identified above can be reduced or avoided.

Overview of the invention

The Task is solved by methods according to claims 1 and 9th

Brief description of the drawings

Further embodiments The present invention is defined in the dependent claims and / or in the following detailed description, the better can be understood when reference is made to the accompanying drawings, in which:

1a and 1b schematically show cross-sectional views of a semiconductor device during various manufacturing stages in the production of a strain-inducing material over the transistor base configuration according to an in-house state-of-the-art process;

2a and 2 B schematically cross-sectional views of a transistor element during various manufacturing stages in the production of a contact level of a transistor element using a high-k dielectric material as an etching stopper, they show examinating examples; and

3a to 3g schematically show cross-sectional views of a semiconductor device during various manufacturing stages in the generation of stress-inducing layers of different types of internal stress across transistors of different conductivity type based on one or more high-k dielectric etch stop materials according to illustrative embodiments of the invention.

Detailed description

In general, the present invention relates to the problem of structuring materials in the contact level of modern semiconductor devices, wherein the properties of conventional etch stop materials, such as silicon dioxide, silicon nitride, and the like, may result in lower performance of transistor elements because of a required thickness for providing the necessary Etch stop properties can negatively affect the transistor properties, or if the thickness of the etch stop material is reduced, the further processing of the device is adversely affected. In view of this situation, the present invention provides techniques in which high-k dielectric materials are used as efficient etch stop materials, which are later patterned by sputtering techniques, which materials have significantly different etching characteristics with respect to a variety of plasma assisted etch recipes , as typically used in the machining of state-of-the-art semiconductor devices. For example, tantalum oxide (Ta ₂ O ₅ ), strontium titanium oxide (SrTiO ₃ ), hafnium oxide (HfO ₂ ), hafnium silicon oxide, zirconium oxide (ZrO ₂ ) are increasingly used, for example, as gate dielectrics and the like. In one illustrative embodiment, hafnium oxide is used as a very efficient etch stop material because of its property that it does not generate volatile byproducts during well-established plasma assisted fluoro and chlorine based etch processes typically used for etching silicon nitride materials and the like.

It It should be noted that in the context of the present invention a high-k dielectric material as a dielectric material it should be understood that a dielectric constant of about 10 or larger.

By Take advantage of the lower removal rate and the higher stability of the dielectric Material with large ε during the Production of the contact level of semiconductor devices can be significant Advantages with regard to the overall production sequence and / or the Performance behavior of the semiconductor devices can be achieved. For example provides the provision of a thin but still very efficient etch stop material layer the possibility, a subsequent material in terms of its deposition properties rather than a moderately thick etch stop material must be provided, as it is to structure the actual dielectric interlayer material is required. Ie., because a reliable Control of the etching process for the contact openings on the basis of a high-k dielectric material can, is a subsequent material layer with improved gap filling properties formed to allow the entire surface topography for modern Reduce semiconductor devices, eliminating the overall process flow is improved. In other cases may be the amount of strained dielectric material for each Transistor element increases without the integrity the transistor base structures during structuring the strained dielectric materials different internal stress levels is impaired. Consequently, you can the stress inducing mechanisms during further size reduction be used by component dimensions, without affecting the overall efficiency these mechanisms unnecessarily reduced becomes.

Related to the 2a and 2 B Illustrative examples are described and in the 3a to 3g Then, illustrative embodiments will be described in more detail.

2a schematically shows a cross-sectional view of a semiconductor device 200 in an advanced manufacturing stage, in which an interlayer dielectric material is to be formed and patterned. The half conductor component 200 includes a substrate 201 , which is provided in the form of any suitable carrier material, about it a semiconductor layer 202 which may represent a suitable material to have a transistor therein and above 250 to build. The semiconductor layer 202 may represent a silicon-based material since many complex integrated circuits are fabricated based on silicon, whose charge carrier mobility properties can be modified by creating a corresponding strain, as previously explained. It should be noted, however, that in other embodiments other semiconductor materials may be used, such as germanium, mixtures of silicon and germanium, silicon and carbon or other semiconductor compounds. Furthermore, a buried insulating layer (not shown) may be interposed between the substrate 201 and the semiconductor layer 202 be provided, at least in some component areas of the component 200 depending on the entire transistor architecture. In the manufacturing stage shown, the transistor comprises 250 a gate electrode 251 coming from a canal area 253 through a gate insulation layer 252 is disconnected. The gate electrode 251 is made of any suitable material, such as polysilicon, a metal-containing material, a mixture of polysilicon and metal, wherein the metal is up to the insulating layer 252 can extend down, and the like. Similarly, the gate insulation layer is 252 constructed of any suitable material, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. In demanding applications, the gate insulation layer contains 252 a high-k dielectric material, for example in the form as previously specified. Furthermore, the transistor 250 Drain and source areas 254 with a suitable vertical and lateral dopant profile, as for the high performance of the transistor 250 is required. A spacer structure 255 may be on sidewalls of the gate electrode 251 be provided with a suitable configuration. Furthermore, if necessary, contact areas 256 in the drain and source areas 254 Metal, for example in the form of metal silicide to reduce the contact resistance. Similarly, metal silicide 256 also in the gate electrode 251 be formed when this has a part of polysilicon. Furthermore, the semiconductor device comprises 200 a dielectric layer 231 with big ε, which over the transistor 250 is formed. In this example, the dielectric layer is 231 with large ε, during further processing of the device 200 can serve as an etch stop layer on the transistor 250 trained, ie the layer 231 is with the contact areas 256 in contact, which may be composed of, for example, metal silicide, as previously explained. In other examples, the dielectric layer is 231 with large ε disposed at any suitable position within a dielectric interlayer material. One or more further dielectric layers with a high ε may be provided, as explained below. The dielectric layer 231 with large ε has a thickness of about 10 nm or less, while in some applications the thickness of the layer 231 is about 5 nm or less. The layer 231 is constructed of any suitable material, as previously explained, while in one example the layer 231 Hafnium, for example in the form of hafnium oxide (HfO ₂ ).

This in 2a shown semiconductor device 200 can be made on the basis of the following processes. After forming respective isolation structures (not shown), for example, by lithography, deposition and planarization techniques, the gate insulation layer becomes 252 and the gate electrode 251 formed by oxidation and / or deposition, followed by a structuring process using modern lithography followed. After that, the drain and source areas become 254 or at least a part thereof, produced by ion implantation, wherein respective regions of the spacer structure 255 as an efficient implantation mask in conjunction with the gate electrode 251 serve. After heating the device 200 for activation of the dopants and for recrystallization of damaged areas become the contact areas 256 in the form of metal silicide, for example, based on well-established recipes. It becomes a process of separation 233 based on a suitable technique, such as CVD, PVD, and the like, to provide the high-k dielectric material of suitable thickness, for example, in the aforementioned specified range, typically significantly lower in value compared to conventional dielectric etch stop materials, such as silicon dioxide; Silicon nitride and the like is applied. Therefore, if the layer 231 is formed with a smaller thickness, a very compliant deposition behavior can be achieved, whereby the influence of the layer 231 in view of the resulting surface topography of the device 200 which also relaxes the requirements for the deposition behavior of subsequent deposition processes to be performed for depositing further dielectric materials. For example, in some illustrative embodiments, another dielectric material may be formed based on a deposition technique that provides improved gap fill performance without the need for additional etch stop materials because of the layer 231 Although this is provided with a smaller thickness, a sufficient Ätzstoppwirkung unfolds during the structuring of contact openings.

2 B schematically shows the semiconductor device 200 in a more advanced manufacturing stage, in which another dielectric material 221 on the etch stop layer 231 is formed, wherein the material 221 may comprise a plurality of different materials, this being the desired structure of a dielectric interlayer material 220 depends on the etch stop material 231 and the material 211 is formed. For example, the material 221 of silicon dioxide with regard to efficient deposition processes with a high gap filling behavior, for example with regard to plasma-assisted CVD and sub-atmospheric CVD based on TEOS. In other cases, the material becomes 221 with greater flexibility in terms of deposition techniques and material composition, since the desired material is close to the transistor 250 can be arranged without this Ätzstoppeigenschaften with regard to the structuring of the material 221 must show. For example, any suitable strain-inducing materials, such as silicon nitride, nitrogen-containing silicon carbide, highly strained silica, and the like, may be included in the material 221 at different component areas within the material 221 be provided because possible differences in the etching properties by the very efficient Ätzstoppmaterial 231 Be "compensated". That is, in some examples, a highly strained silicon dioxide material is placed close to one transistor, while a silicon nitride material is placed close to another transistor, without substantially the overall uniformity during a subsequent patterning process for making the contact openings 222 is affected, as indicated by the dashed lines.

Thus, after the deposition of the dielectric material 221 suitable lithography methods to form a mask over the dielectric interlayer material 220 to form and through the material 221 etch, wherein the etch stop layer 231 is used as an efficient etch stop due to less volatile by-product formation, as previously explained.

Related to the 3a to 3g Illustrative embodiments of the invention will now be described in which strain-inducing materials are formed in the contact plane for different types of transistors based on a high-k dielectric etch stop material.

3a schematically shows a cross-sectional view of a semiconductor device 300 with a substrate 301 over which a semiconductor layer 302 is formed. With regard to these components, the same criteria apply as they did before with respect to the components 100 and 200 are explained. Furthermore, the component comprises 300 one or more transistors 350a that can represent the same or different types of conductivity. That is, one of the transistors 350a optionally represents a p-channel transistor, while the other represents an n-channel transistor, wherein a suitable isolation structure (not shown) is formed between these devices. In the embodiment shown, it is assumed that the transistors 350a Transistors of the same conductivity type, which in a high density package area, such as a RAM area, as well as with respect to the device 100 is described, are formed. On the other hand, the one or more transistors 350b represent a transistor, one compared to the transistors 350 different deformation mechanism needed. For example, the transistor represents 350b a p-channel transistor, while the transistors 350a form n-channel transistors. In the manufacturing stage shown are the transistors 350a . 350b essentially completed and therefore contain a gate electrode 351 coming from a canal area 353 through a gate insulation layer 352 is disconnected. With regard to the gate electrode 351 and the gate insulation layer 352 apply the same criteria as previously related to the components 100 and 200 are described. Furthermore, there are drain and source regions 254 in the semiconductor layer 302 formed, if necessary, a spacer structure 355 on sidewalls of the gate electrode 351 is trained. If necessary, a metal material is in contact areas 356 intended. With regard to dimensions of the transistors 350a . 350b Apply the same criteria as before with respect to the device 100 are explained. That is, the transistors 350a . 350b may have a gate length of about 50 nm or less, including a distance between adjacent gate electrodes of the high-density transistors 350a may be 100 nm or less.

The transistors 350a . 350b can be formed on the basis of process techniques such as those related to the semiconductor device 200 The corresponding design rule may lead to sophisticated surface topographies caused by the gate electrodes 351 and the small pitch of the transistors 350a is caused. Thereafter, an etch stop layer 331 having similar characteristics as previously described with respect to the high-k dielectric layer 231 are explained. Thus, the etch stop layer is 331 of any suitable high-k dielectric material having a large etch resistance with respect to well established plasma assisted etch recipes. In some illustrative embodiments, the layer has 331 Hafnium, for example in the form of hafnium oxide on. A thickness of the layer 331 is about 10 nm or less in some illustrative embodiments, it being understood that greater thickness may be used if desired, while in other embodiments even smaller thickness, for example 5 nm, 3 nm and less is used. The layer 331 can be made on the basis of any suitable deposition technique, such as CVD, and the like. Next, a first strain-inducing layer 330 which may be constructed of a suitable material, such as silicon nitride, nitrogen-containing silicon carbide, silicon dioxide and the like, over the transistors 350a . 350b educated. In the embodiment shown Form is assumed that the layer 330 is provided with a high internal strain, which for improving the performance of the transistors 350a is suitable, while possibly the performance of the transistor 350b is negatively influenced. It should be noted, however, that the layer 330 has an internal stress level, which is suitable in other cases, the performance of the transistor 350b to improve. As previously explained, the deposition parameters are for producing the layer 330 is chosen so that the desired internal stress level is achieved, whereby the gap filling properties are taken into account so that the layer 330 essentially without deposition-related irregularities, such as cavities and the like provided. Due to the smaller thickness of the etch stop layer 331 can the layer 330 be applied by less demanding conditions, whereby the deposition of a greater thickness compared to a conventional strategy is possible, as previously with reference to the 1a and 1b which explains greater amounts of highly strained dielectric material in the immediate vicinity of the transistors 350a can be provided without increasing the likelihood that further yield losses will occur.

3b schematically shows the semiconductor device 300 in a more advanced manufacturing stage. As shown, covers an etching mask 303 the transistors 350a while the transistor 350b the action of a plasma-assisted etching environment 304 exposed, which is designed so that the area of the layer 330 that is above the transistor 350b is arranged, etched. The improved etch stop properties of the high-k dielectric material in the layer 331 Thus, the integrity of the underlying transistor areas of the device 350 while still maintaining sufficient process tolerance ranges during the final stage of the etch process 304 is taken care of.

3c schematically shows the semiconductor device 300 according to further illustrative embodiments, in which a further dielectric layer 331 with large ε on the strain-inducing layer 330 is formed. For example, the layer 331a made of the same material as the layer 331 whereas in other cases another high-k dielectric material is used, and also a thickness of the layer 331a may be in the range of about 10 nm or less. For example, the layer becomes 331a at the end of the etching process 304 or after removing the etching mask 303 formed, whereby also the layer 331a over the exposed area of the layer 331 in the transistor 350b is deposited. In other illustrative embodiments, the layer has become 331 as shown after deposition of the layer 330 and before performing the etching process 304 educated. In this case, the etching process includes 304 a suitable ablation process, for example, based on a sputter etch process, in which a suitable heavy species, such as argon, is directed onto the exposed surface area around the material of the layer 331a physically abzutra. Thereafter, a conventional etching recipe can be used to the exposed portion of the layer 330 to remove, as previously explained.

Thus, the dielectric material 331 with large ε as an efficient yet thin etch stop material during further processing of the device 300 serve.

3d schematically shows the semiconductor device 300 after the deposition of the layer 330 according to still further illustrative embodiments. As shown, a plasma assisted oxidation process 305 executed to a surface area of the layer 330 to convert into an oxidized region, for example made of silicon dioxide, with a thickness of a few nanometers depending on the parameters of the plasma environment 305 is. Thus, also in this case, an efficient etch stop or etching control layer 335 for further processing of the device 300 be provided. In still other illustrative embodiments, the plasma treatment becomes 305 after the etching process 304 and removing the etch mask 303 wherein the exposed area of the etch stop layer 331 for the desired integrity of the transistor 350b provides.

Thereafter, further processing is continued, for example, by depositing another strain-inducing material having an internal stress level to thereby enhance the performance of the transistor 350b to improve.

3e schematically shows the semiconductor device 300 in a manufacturing phase, in which a second deformation-inducing layer 340 selectively across the transistor 350b is provided. For this purpose, the layer 340 deposited and then selectively from above the transistors 350a in some illustrative embodiments, the additional etch stop or etch control layers 331a or 335 for controlling the respective etching process and a moderately thin etch stop or etch control layer material, for example in the form of the layers 331a . 335 provide, resulting in lower deposition caused by surface irregularities, as well as the deposition of the material 340 in challenging surface topographies in particular, the ablation process over the transistors 350a can lead to irregularities that can cause a loss of contact at a later stage of production. Thus, also in this case provides a smaller thickness of an etch stop material, such as the layers 331a . 335 , for an overall higher process efficiency.

3f schematically shows the semiconductor device 300 in a more advanced manufacturing phase. As shown, is another dielectric material 321 over the layers 330 and 340 formed, which in conjunction with the layers 330 . 340 and the dielectric etch stop material 331 with high ε a dielectric interlayer material 320 is formed. It should be noted that the material 321 may have two or more different materials and that also other Ätzstopp- or Ätzsteuermaterialien may be present, for example in the form of layers 331a . 335 locally over the transistors 350a are formed. Furthermore, first areas of contact openings 322 in the material 321 formed, with an area 322 to a greater or lesser degree in the layers 330 . 340 depending on the overall material composition of the materials 322 . 330 and 340 extends. That is, in some cases, one of the layers has or has both layers 330 . 340 Similar etch characteristics, which provide reduced etch stop characteristics, but this is acceptable because the integrity of the transistor devices through the dielectric material 331 is ensured with a large ε. Thus, in contrast to conventional solutions, a high degree of flexibility in the selection of suitable materials for the layer 330 . 340 and 322 be achieved. The material 321 and the contact openings 322 can be formed on the basis of any suitable deposition and patterning scheme, as previously explained.

3g schematically shows the semiconductor device 300 in a more advanced manufacturing stage. As shown, the openings extend 322 down to the dielectric 331 with large ε, which can be achieved on the basis of any suitable recipe, for example with a recipe designed to etch through silicon nitride material when the layers 330 . 340 are essentially constructed of strained silicon nitride material. In other cases, as previously explained, the openings 322 are formed in a single etch sequence so as to pass through the material 321 and the layers 330 . 340 to etch on the basis of a substantially non-selective etch recipe. Furthermore, the component 300 an etching process 306 having been designed, the high-k dielectric-stoppage material 331 to open the openings 322 down to the contact areas 356 to deepen, which are arranged at different height levels, for example, according to the height of the gate electrodes 351 and the drain and source regions 354 , The etching process 306 is provided in the form of a sputter etching process in which a suitable species, such as argon, is used to expose exposed areas of the dielectric material 331 with large ε to remove. During the sputtering process 306 the corresponding species will release the sputtering environment or may be on sidewalls of the contact openings 322 sputter again, but the further processing is not affected undesirable. It should be noted that the process 306 can be performed on the basis of an etching mask if necessary, while in other cases due to the small thickness of the layer 331 an etch damage in the material 321 is acceptable. After that, the contact openings 322 filled with a desired conductive material, such as tungsten, copper, aluminum, and the like, depending on the overall process strategy, with typically a suitable barrier material also being provided. Well-established process techniques can be used for this purpose.

It Thus, the present invention provides techniques in which high-k dielectric materials for producing a contact plane a semiconductor device used and then by Sputter processes are structured, d. H. these materials will be for producing a dielectric interlayer material and corresponding contact openings used, the high Ätzstoppvermögen the high-k dielectric materials provide the etch stop materials with a smaller thickness compared to conventional strategies enable, whereby the deposition of subsequent materials is improved and causing a higher Measure flexibility in providing interlayer dielectric materials is created. In some illustrative embodiments, a dielectric is used High ε material with hafnium as an efficient etch stop layer used.

Claims (14)

Method comprising: forming a dielectric layer having an ε greater than 10 ( 331 ) over a first transistor ( 350a ) and a second transistor ( 350b ) of a semiconductor device ( 300 ); Forming a first strain-inducing layer ( 330 ) on the dielectric layer with an ε greater than 10 ( 331 ), wherein the first strain-inducing layer ( 330 ) a deformation in a channel region ( 353 ) of the first and the second transistor ( 250 . 350a . 350b ) generated; Removing part of the first deformation inductive layer ( 330 ) from above the second transistor ( 350b ) using the dielectric layer with an ε greater than 10 ( 331 ) as an etch stop material, forming an opening ( 322 ) in the first strain-inducing layer ( 330 ) and removing a portion of the dielectric layer having an ε greater than 10 passing through the opening ( 322 ) is exposed by a sputter etching process ( 306 ) is performed. The method of claim 1, wherein forming the dielectric Layer with an ε greater than 10 includes: deposition the dielectric layer having an ε greater than 10 with a thickness of 10 nm or less. The method of claim 1, wherein the dielectric Layer with an ε greater than 10 hafnium and / or Tantalum and / or strontium and / or zirconium has. The method of claim 3, wherein the dielectric Layer having a ε greater than 10 hafnium oxide. The method of claim 1, further comprising: forming a second dielectric layer having an ε greater than 10 ( 331a ) on the first strain-inducing layer ( 230 . 330 ) before removing the part of the first strain-inducing layer. The method of claim 5, further comprising: forming a second strain-inducing layer ( 340 ) over the first and second transistors ( 350b ) and removing a part of the second strain-inducing layer ( 340 ) from above the first transistor ( 350a ) using the second dielectric layer with an ε greater than 10 ( 331a ) as an etch stop. The method of claim 5, wherein for the second dielectric layer with ε greater than 10 the thickness 10 nm or less. The method of claim 5, wherein the second dielectric Layer with an ε greater than 10 hafnium and / or Tantalum and / or strontium and / or zirconium has. Method with: forming a dielectric interlayer ( 320 ) over a transistor ( 350a . 250b ) of a semiconductor device ( 300 ) and a contact opening ( 322 ) in the dielectric interlayer by performing a plurality of deposition processes and a plurality of etching processes including a sputtering etching process ( 306 ), the dielectric interlayer material ( 320 ) a dielectric material layer with an ε greater than 10 ( 331 ) having; Using the dielectric material layer with an ε greater than 10 ( 331 ) as an etch stop material during at least one ( 304 ) of the plurality of etching processes and etching through the dielectric material layer having an ε greater than 10 by performing the sputtering etching process (FIG. 306 ). The method of claim 9, further comprising: forming the dielectric material layer with an ε greater than 10 on the transistor and Depositing one or more further dielectric materials, to form the dielectric interlayer. The method of claim 9, further comprising: forming a strain-inducing layer ( 330 . 340 ) as part of the interlayer dielectric, wherein the strain-inducing layer generates a strain in a channel region of the transistor. The method of claim 11, further comprising: removing a portion of the strain-inducing layer by at least one ( 304 ) of the multiple etching processes. The method of claim 12, further comprising: forming a second strain-inducing layer ( 340 ) as part of the dielectric interlayer, the second strain-inducing layer causing a different type of deformation as compared to the first strain-inducing layer. The method of claim 13, further comprising: forming a second dielectric material layer having an ε greater than 10 ( 331a ) and using the second dielectric material layer having an ε greater than 10 as an etching control material for patterning the second strain-inducing layer (FIG. 340 ) during one of the multiple etching processes.