DE102008011757B4 - Method for maintaining lowest doping levels in semiconductor fabrication - Google Patents
Method for maintaining lowest doping levels in semiconductor fabrication Download PDFInfo
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- DE102008011757B4 DE102008011757B4 DE102008011757.9A DE102008011757A DE102008011757B4 DE 102008011757 B4 DE102008011757 B4 DE 102008011757B4 DE 102008011757 A DE102008011757 A DE 102008011757A DE 102008011757 B4 DE102008011757 B4 DE 102008011757B4
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002019 doping agent Substances 0.000 claims abstract description 50
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000011109 contamination Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 description 55
- 235000012431 wafers Nutrition 0.000 description 20
- 238000000137 annealing Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Verfahren zur Aufrechterhaltung niedrigster Dotierstoffkonzentration in der Halbleiterfertigung durch Verhindern einer Kontamination mit Dotierstoff von außen, bei dem – ein Substrat (1) aus Halbleitermaterial mit einem dotierten Bereich einer Dotierstoffkonzentration von höchstens 1013 cm–3 versehen wird, – eine ganzflächige Oxidschicht (7) aufgebracht wird, mit der der dotierte Bereich bedeckt wird, – eine ganzflächige Nitridschicht (8) auf die Oxidschicht (7) aufgebracht wird und – das Substrat einer erhöhten Temperatur ausgesetzt wird, so dass ein Ausheilen oder Eintreiben von Dotierstoff erfolgt, wobei die Dotierstoffkonzentration in dem dotierten Bereich auf 1013 cm–3 begrenzt bleibt.Method for maintaining the lowest dopant concentration in semiconductor production by preventing contamination with dopant from the outside, in which - a substrate (1) made of semiconductor material is provided with a doped region with a dopant concentration of at most 1013 cm -3, - a full-surface oxide layer (7) is applied with which the doped region is covered, - a full-area nitride layer (8) is applied to the oxide layer (7) and - the substrate is exposed to an elevated temperature, so that dopant is cured or driven in, the dopant concentration in the doped area remains limited to 1013 cm – 3.
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Aufrechterhaltung niedrigster Dotierlevel bei der Herstellung von Halbleiterbauelementen mit Bereichen niedriger Dotierstoffkonzentration, insbesondere mit einer Dotierstoffkonzentration von weniger als 1013 cm–3.The present invention relates to a method for maintaining lowest doping levels in the manufacture of semiconductor devices having low dopant concentration regions, in particular having a dopant concentration of less than 10 13 cm -3 .
Bei der Integration von Bauelementen in integrierten Schaltungen auf einem Halbleiterchip werden mitunter Bereiche von Dotierstoffkonzentrationen bis höchstens 1013 cm–3 benötigt. Üblicherweise bei der Herstellung von Halbleiterchips verwendete Wafer, zum Beispiel aus Silizium, können eine sehr hohe Grunddotierung von typisch etwa 1019 cm–3 aufweisen. Bei CMOS-Prozessen und BiCMOS-Prozessen werden dotierte Wannen beider Vorzeichen der Leitfähigkeit implantiert. Die Implantate werden bei erhöhter Temperatur in eigens dafür vorgesehenen Öfen ausgeheilt, wobei eine Diffusion des Dotierstoffes auftritt und der Dotierstoff in den Wafer eingetrieben wird. Vor diesem Verfahrensschritt wird ein vorzugsweise ebenfalls thermischer Oxidationsschritt durchgeführt, mit dem eine dünne oberflächliche Oxidschicht auf dem Halbleiterwafer hergestellt wird, die ein Ausdiffundieren des Dotierstoffes in die Gasphase und damit eine Verarmung der oberflächennahen Waferbereiche an Dotierstoff verhindern soll.When integrating components in integrated circuits on a semiconductor chip, sometimes ranges of dopant concentrations up to at most 10 13 cm -3 are required. Wafers commonly used in the manufacture of semiconductor chips, for example silicon, may have a very high fundamental doping of typically about 10 19 cm -3 . In CMOS processes and BiCMOS processes, doped wells of both signs of conductivity are implanted. The implants are annealed at elevated temperature in dedicated ovens where diffusion of the dopant occurs and the dopant is driven into the wafer. Prior to this process step, a preferably likewise thermal oxidation step is carried out, with which a thin surface oxide layer is produced on the semiconductor wafer, which is intended to prevent outdiffusion of the dopant into the gas phase and thus a depletion of the near-surface wafer regions to dopant.
Wenn die Implantate eines Wafers mit niedrig dotierten Bereichen auf diese Weise ausgeheilt werden, genügt die oberseitige Oxidschicht nicht, die Dotierstoffkonzentration in den niedrig dotierten Bereichen auf Werten unterhalb von 1013 cm–3 zu halten. Wenn der Ofen kostengünstig betrieben wird und Wafer mit niedrig dotierten Bereichen zusammen mit üblichen Wafern mit Dotierstoffkonzentrationen von typisch etwa 1015 cm–3 ausgeheilt werden, machen sich unterschiedliche Kontaminationsquellen, die nicht beseitigt werden können, negativ bemerkbar. Im Ergebnis besitzen alle Wafer an den Oberseiten nur dotierte Bereiche, in denen die Dotierstoffkonzentrationen mindestens 1015 cm–3 betragen, was nicht für alle vorgesehenen Anwendungen geeignet ist.When the implants of a wafer are annealed with low doped regions in this manner, the top-side oxide layer is not sufficient to maintain the dopant concentration in the lightly doped regions on values below 10 13 cm -3. If the furnace is operated cost-effectively and wafers with low doped areas are annealed together with conventional wafers with doping concentrations of typically about 10 15 cm -3 , different sources of contamination that can not be eliminated, adversely affect. As a result, all wafers on the tops have only doped areas in which the dopant concentrations are at least 10 15 cm -3 , which is not suitable for all intended applications.
In der
In der
In der
In der
In der
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Aufrechterhaltung niedrigster Dotierlevel in der Halbleiterfertigung anzugeben, mit dem es möglich ist, niedrig dotierte Bereiche während eines thermischen Ausheilschrittes auf Werten der Dotierstoffkonzentration von höchstens 1013 cm–3 zu halten.The object of the present invention is to specify a method for maintaining the lowest doping levels in semiconductor production, with which it is possible to keep low-doped regions at values of the dopant concentration of at most 10 13 cm -3 during a thermal annealing step.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.This object is achieved by the method having the features of
Die Beseitigung des Kontaminationsproblems gelingt mit einer Abfolge von Verfahrensschritten, in denen zuerst auf der mit den Bereichen niedriger Dotierstoffkonzentration versehenen Oberseite des Wafers eine Oxidschicht ausgebildet wird und anschließend eine Nitridschicht auf die Oxidschicht abgeschieden wird. Danach erfolgt der Verfahrensschritt bei erhöhter Temperatur zum Eintreiben beziehungsweise Ausheilen des Dotierstoffes, während dessen die Bereiche niedriger Dotierstoffkonzentration von der Oxidschicht und der Nitridschicht geschützt bleiben. Nach dem Temperschritt können die Nitridschicht und die Oxidschicht entfernt werden.The elimination of the contamination problem succeeds with a sequence of method steps in which an oxide layer is first formed on the upper side of the wafer provided with the regions of low dopant concentration, and then a nitride layer is deposited on the oxide layer. Thereafter, the process step is carried out at elevated temperature for driving or annealing the dopant, during which the regions of low dopant concentration remain protected by the oxide layer and the nitride layer. After the annealing step, the nitride layer and the oxide layer can be removed.
Das geschieht zum Beispiel durch eine trocken- oder nasschemische Rückätzung.This happens, for example, by a dry or wet chemical etching back.
Es folgt eine genauere Beschreibung von Beispielen des Verfahrens anhand der beigefügten Figuren.The following is a more detailed description of examples of the method with reference to the attached figures.
Die
Die
Die
Die
An der Oberseite
In dem dargestellten Beispiel ist das Substrat
Die
Die
Es wurde nachgewiesen, dass mit der Doppelschicht bestehend aus einer ganzflächigen Oxidschicht und einer darauf aufgebrachten wesentlich dickeren ganzflächigen Nitridschicht eine wirkungsvolle Abschirmung der niedrig dotierten Bereiche an der Oberseite des Wafers oder in der niedrig dotierten Epitaxieschicht gegen Kontaminationen erzielt werden kann. Mit Verwendung nur einer Oxidschicht oder nur einer Nitridschicht kann diese Wirkung nicht in dem erwünschten Umfang erreicht werden. Die Verwendung beider Schichten ermöglicht es jedoch, die Dotierstoffkonzentration in Oberflächenbereichen des Wafers oder in der Epitaxieschicht auf Werten von weniger als 1013 cm–3 zu halten. Das gilt auch dann, wenn als Substrat
Die in den Figuren dargestellten dotierten Wannen
Das beschriebene Verfahren ermöglicht es, Halbleiterwafer mit Bereichen unterschiedlicher Dotierstoffkonzentrationen an der Oberseite derart zu schützen, dass für besondere Anwendungen, zum Beispiel zur Integration von PIN-Fotodioden, niedrigst dotierte Bereiche an der Oberseite des Substrates erhalten bleiben. Die Dotierstoffkonzentration kann dadurch in einem ursprünglich entsprechend niedrig dotierten Bereich einer Epitaxieschicht insbesondere auf Werten unterhalb 1013 cm–3 gehalten werden. Wenn entweder die Oxidschicht
BezugszeichenlisteLIST OF REFERENCE NUMBERS
- 11
- Substratsubstratum
- 22
- Epitaxieschichtepitaxial layer
- 33
- n-Wannen-well
- 44
- p-Wannep-well
- 55
- OxidverkapselungOxidverkapselung
- 66
- Oberseitetop
- 77
- Oxidschichtoxide
- 88th
- Nitridschichtnitride
Claims (9)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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DE102008011757.9A DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
PCT/EP2009/050950 WO2009106400A1 (en) | 2008-02-28 | 2009-01-28 | Method for maintaining lowest doping levels in semicondcutor production |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE102008011757.9A DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
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DE102008011757A1 DE102008011757A1 (en) | 2009-09-10 |
DE102008011757B4 true DE102008011757B4 (en) | 2014-11-20 |
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DE102008011757.9A Expired - Fee Related DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
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WO (1) | WO2009106400A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US20030008524A1 (en) * | 2001-07-04 | 2003-01-09 | Karsten Wieczorek | Method of forming a thin oxide layer having improved reliability on a semiconductor surface |
US20030059985A1 (en) * | 2001-09-27 | 2003-03-27 | Adkisson James W. | Method of fabricating lateral diodes and bipolar transistors |
US20060024929A1 (en) * | 2004-07-27 | 2006-02-02 | Samsung Electronics Co., Ltd. | Method of forming a well in a substrate of a transistor of a semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4662956A (en) * | 1985-04-01 | 1987-05-05 | Motorola, Inc. | Method for prevention of autodoping of epitaxial layers |
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- 2008-02-28 DE DE102008011757.9A patent/DE102008011757B4/en not_active Expired - Fee Related
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- 2009-01-28 WO PCT/EP2009/050950 patent/WO2009106400A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US20030008524A1 (en) * | 2001-07-04 | 2003-01-09 | Karsten Wieczorek | Method of forming a thin oxide layer having improved reliability on a semiconductor surface |
US20030059985A1 (en) * | 2001-09-27 | 2003-03-27 | Adkisson James W. | Method of fabricating lateral diodes and bipolar transistors |
US20060024929A1 (en) * | 2004-07-27 | 2006-02-02 | Samsung Electronics Co., Ltd. | Method of forming a well in a substrate of a transistor of a semiconductor device |
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WO2009106400A1 (en) | 2009-09-03 |
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