DE102007040148B4 - Microprocessor with a circuit for evaluating a large number of program counter (PC) values for generating breakpoint control signals for a program logging unit - Google Patents

Abstract

Microprocessor, with a program logging unit which has a circuit for evaluating a plurality of program counter (PC) values for generating breakpoint control signals for the program logging unit, the circuit examining whether at least one program counter (PC) value from the A large number of program counters (PC) values which form a second value range lie within a predetermined first value range (BND ... BND + RNG), the first value range and the second value range being continuous value ranges, and the second value range being the Range ip_ref_r ... ip_ref_r + cur_inc_r forms, where ip_ref_r represents the old PC value of the previous clock cycle, and cur_inc_r represents the maximum increment of the current clock cycle, and wherein the circuit comprises: a first subtractor (401) which is the lower limit of the first value range (BND) and the lower limit of the second value range (ip_ref_r) receiving signals, and for generating a first subtraction result signal representing a first subtraction result signal subtracts the lower limit value of the second value range (ip_ref_r) from the lower limit value of the first value range (BND); a second subtractor (431) which subtracts the first subtraction result signal representing the first subtraction result receives the first subtractor (401), and subtracts the received maximum increment of the second value range cur_inc_r from the first subtraction result to generate a second subtraction result signal representing a second subtraction result; a first comparator (432), which represents the second subtraction result signal (431) representing the second subtraction result ), and examines whether the second subtraction result from the second subtractor (431) is less than or equal to zero, and if so, an S representing a true value signal, and if no, outputs a signal representing a false value; an adder (402) which receives the first subtraction result signal representing the first subtraction result from the first subtraction member (401) receives a signal (RNG) representing the width of the second value range , and outputs a signal representing a sum value of the first subtraction result and the width of the second value range; a second comparator (433) which receives the signal representing the sum value from the adder (402) and examines whether the sum value is greater than or equal to zero, and if yes, outputs a signal representing a true value, and if no, outputs a signal representing a false value; and an AND circuit (409) which receives the signals representing a true or false value from the first (433) and second comparator (432) and outputs a result signal representing a true value when the signal from the first (433) and second comparator (443) received signals both represent a true value, and otherwise outputs a result signal representing a false value.

Description

BACKGROUND OF THE INVENTION

The invention relates generally to circuits and methods for comparing values, particularly in a microprocessor.

In particular, the invention relates to circuits and methods for comparing numbers given as an output value and a sequence of increments in digital circuits.

For example, there are applications in which it must be determined at a certain point in time whether a signal reaches or exceeds a value range.

By way of example, signal transitions in the range from, for example, 10,050 to 10,060 are to be examined, the values which can be observed and which are provided by, for example, a stimulating circuit, for example in succession 10,000 . 10040 and 10,080 are present in start / increment pairs {10000, -}, {-, 40}, {-, 40}. A simple set of two comparators ( 10050 ≤ signal ≤ 10.060), on the other hand, misses the transition in the above range, since the signals provided do not have its grain size. (It is assumed that all (other) values from 10,050 to 10,060 are also valid when stimulating with the stated values.)

The above type of comparison / determination is of interest, for example, when logging a program counter (PC) of a microprocessor. A PC circuit generates an address to control the order of execution of a group of instructions, which indicates a location of any instruction code stored on a storage medium. Control can be done in such a way that the command codes are executed in an order prescribed by a program. The command codes are identified by specifying addresses that indicate their location. The PC circuit generates such addresses and outputs the addresses as PC values.

In general, the program counter automatically counts up on each instruction cycle so that the instructions are normally retrieved sequentially from the storage medium. However, certain commands such as jumps and subroutine calls and jumps interrupt the sequence by inserting a new value in the program counter.

With a superscalar CPU, for example, the logging hardware only receives the absolute PC value under certain circumstances, for example when logging begins or after a program jump, and the code execution is otherwise displayed by the CPU in the form of PC increments, with each increment indicates that one or more commands have been executed.

A typical task of the logging hardware is to evaluate the received PC values to generate control signals, e.g. B. Breakpoints. A set of comparators can be used to determine whether the CPU has executed commands in a particular PC area, or even whether it has only executed a particular command at a particular PC location.

Continuing with the example above and assuming the stimulating circuit can provide increments from 2 to 40 in steps of 2, the logging hardware or comparison hardware must compare all values from 10,040 to 10,080 in steps of 2 if the value 10,080 (actually the increment "{-, 40}") in a second step after receiving the value 10040 Will be received. This multitude of comparison processes must be performed in the same clock cycle or sequentially, but with the following problems: On the one hand, performing the comparison completely is expensive for each calculated value (usually PC values are shown with 24 to 32 or even more bits) and on the other hand using additional clock cycles is extremely detrimental to processor performance, especially when the CPU provides the increments over a wide bandwidth. For these and other reasons, there is a need for the present invention.

In Croad, JG: Range Comparator. IBM Technical Disclosure Bulletin, Vol. 7, May 12, 1965, pages 1158 1159 , a range comparator is disclosed which compares a discrete individual value with a predetermined range of values.

In Tietze, U., Schenk, Ch .: Semiconductor circuit technology, 9th edition, Springer Verlag 1989 , Pages 603 - 613 , basics of circuit technology are disclosed.

It is a specific technical task to provide an efficient evaluation of current program counter values in order to generate breakpoint control signals.

BRIEF SUMMARY OF THE INVENTION

The object is achieved by the subject matter of patent claim 1. Another embodiment is described in dependent claim 2.

According to one aspect of the invention, there is provided a method of examining a section of a first range of values and a second range of values, each of which includes a lower limit and an upper limit, in a microprocessor, the method of examining whether a value of the range is greater than or equal to is the lower limit of the second range of values, and examining whether the lower limit of the first range of values is less than or equal to the upper limit of the second range of values.

According to a further aspect of the invention, there is provided a circuit for examining a section of a first range of values and a second range of values, each of which includes a lower limit and an upper limit, the circuit comprising first means for examining whether a value of the range of values is greater than or equal to is the lower limit of the second range of values, and second means for examining whether the lower limit of the first range of values is less than or equal to the upper limit of the second range of values.

Further features, aspects and advantages of the present invention will become apparent in the following detailed description with reference to the accompanying drawings.

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• 1 zeigt eine schematische, beispielhafte Darstellung eines Schnitts einer Programmprotokolliereinheit, die mindestens eine Schaltung nach Ausführungsbeispielen der Erfindung umfasst;
• 2 zeigt eine grafische Darstellung einer Ungleichung, die von der in 1 gezeigten Schaltung zu untersuchen ist;
• 3 zeigt ein Schemadiagramm einer Schaltung nach einem Ausführungsbeispiel der Erfindung; und
• 4 zeigt ein Schemadiagramm einer Schaltung nach einem weiteren Ausführungsbeispiel der Erfindung.

The accompanying drawings are included to provide a better understanding of the present invention and are incorporated in and constitute a part of this description. The drawings show exemplary embodiments of the present invention and, together with the description, serve to explain the basic ideas of the invention. Other embodiments of the present invention and many of the intended benefits of the present invention are easy to assess because they can be better understood with reference to the following detailed description.

• 1 shows a schematic, exemplary representation of a section of a program logging unit, which comprises at least one circuit according to embodiments of the invention;
• 2 shows a graphical representation of an inequality derived from that in 1 circuit shown is to be examined;
• 3 shows a schematic diagram of a circuit according to an embodiment of the invention; and
• 4 shows a schematic diagram of a circuit according to a further embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which, by way of illustration, specific exemplary embodiments are shown in which the invention can be carried out. It should be noted that other exemplary embodiments can be used and structural or other changes can be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

1 shows a schematic, exemplary representation of a section of a program logging unit (Program Trace Unit, PTU) according to an embodiment of the invention, for example the PTU of a superscalar CPU. A typical task of the PTU is, for example, evaluating the received PC values to generate control signals, e.g. B. Breakpoints.

As in 1 shown, the PTU comprises at least one comparator circuit 11 ,

bzw.: $$\begin{array}{c}\text{BND}\le \text{ip\_ref\_r}+{\text{inc}}_{\text{i}}\le \text{BND}+\text{RNG}\\ {\text{bei beliebigem inc}}_{\text{i}}\text{ in }0\dots \text{cur\_inc\_r Ungleichung}\end{array}$$

The comparator circuit 11 receives the input signals valid_I 13, ip_ref_I 14 and cur_inc_I 15. The input signal valid_I 13 indicates whether the received command pointer increments are "currently valid" or not. Only if the logged program sequence is currently linear can the command pointer increments be evaluated directly and in parallel for the at least one comparator circuit 11 to be provided. However, if the logged program flow is currently not linear, for example because the PTU is waiting for a jump destination to occur, the PTU must temporarily save the received increments until the destination address occurs, since the received increments have to be interpreted in relation to this destination address. If the input signal valid_I 13 thus indicates “not currently valid” increments, the at least one comparator circuit remains 11 on standby until the input signal valid_I 13 shows "currently valid" increments. An input from the pre-trigger 12 is with an output of the at least one comparator circuit 11 for providing a comparator signal 17 connected. Based on the comparator signal 17 from the at least one comparator circuit 11 the pre-trigger provides a hit (e.g. activation of a pre-trigger signal 12 ) if at least one of the program counter (PC) values contained in the ip_ref_I 14 and cur_inc_I 15 inputs is within the programmed range, described by inequality 1: $$\text{BND}\le \text{PC}\le \text{BND}+\text{RNG}$$

respectively.: $$\begin{array}{c}\text{BND}\le \text{ip\_ref\_r}+{\text{inc}}_{\text{i}}\le \text{BND}+\text{RNG}\\ {\text{with any inc}}_{\text{i}}\text{in}0...\text{cur\_inc\_r inequality}\end{array}$$

• BND ist der untere Grenzwert des programmierten Bereichs;
• RNG ist die Breite des programmierten Bereichs;
• PC ist der aktuelle Programmzählerwert;
• ip_ref_r ist der „alte PC-Wert“ vom vorhergehenden Taktzyklus;
• inci sind eine Vielzahl von Inkrementen (0...cur_inc_r), wobei cur_inc_r das maximale Inkrement des aktuellen Taktzyklus ist.

The following applies:

• BND is the lower limit of the programmed range;
• RNG is the width of the programmed area;
• PC is the current program counter value;
• ip_ref_r is the "old PC value" from the previous clock cycle;
• inci are a variety of increments ( 0 ... cur_inc_r), where cur_inc_r is the maximum increment of the current clock cycle.

2 shows a graphic representation of inequality 1. The upper diagram shows inequality 1 in the case of cur_inc_r = 0. In this case inequality 1 is only true ("hit") if ip_ref_3 is within the limits BND and BND + RNG (interval 22 ) lies or corresponds to these. Otherwise, inequality 1 is untrue ("no hit", interval 21 and 23 ).

The lower diagram shows a general case of inequality 1. In this case, the interval of values for ip_ref_r for which inequality 1 is fulfilled ("hit") is larger: in addition to the interval 25b (BND ... BND + RNG), the interval 22 of the diagram above, also meet values for ip_ref_r in the adjacent interval 25a the inequality 1. For values of ip_ref_r within this interval 25a the current PC value (PC = ip_ref_r + inc _i ) - for corresponding values of inci - is within the programmed range (BND ... BND + RNG). Since inci are increasing values with a maximum value of cur_inc_r, interval has 25a a width of cur_inc_r and is below the interval 25b ,

Values of ip_ref_r in the intervals 24 and 26 do not meet inequality 1 ("no hit").

und $$\begin{array}{cc}\text{ip\_ref\_r}+{\text{inc}}_{\text{i}}\le \text{BND}+\text{RNG}& {\text{bei beliebigem inc}}_{\text{i}}\text{ in }0\dots \text{cur\_inc\_r}\end{array}$$

To examine inequality 1, which is actually a "double inequality", inequality 1 is divided into two inequalities 2 and 3 divided up: $$\begin{array}{cc}\text{BND}\le \text{ip\_ref\_r}+{\text{inc}}_{\text{i}}& {\text{with any inc}}_{\text{i}}\text{in}0...\text{cur\_inc\_r}\end{array}$$

and $$\begin{array}{cc}\text{ip\_ref\_r}+{\text{inc}}_{\text{i}}\le \text{BND}+\text{RNG}& {\text{with any inc}}_{\text{i}}\text{in}0...\text{cur\_inc\_r}\end{array}$$

Assuming that it is not important to know exactly which value of inci meets inequality 1, ie inequality 2 and 3, inequality 3 can be simplified based on the following considerations: To examine whether any of the values of ip_ref_r + inci is less than or equal to BND + RNG, an investigation is sufficient to determine whether ip_ref_r is less than or equal to BND + RNG: If the smallest value of ip_ref_r + inci, ie ip_ref_r (inc _i = 0), is already greater than BND + RNG, no other value is obtained of ip_ref_r + inc _{i be} less than or equal to BND + RNG, which leads to simplified inequality 3a: $$\text{ip\_ref\_r}\le \text{BND}+\text{RNG}$$

3 shows a circuit according to an embodiment of the invention, which represents a hardware implementation of an investigation of inequality 2 and 3a. The circuit of 3 includes a subtractor 301 , which receives the digital values of BND and ip_ref_r as input and generates a differential digital value BND-ip_ref_r as output, which comprises a sign bit, m most significant bits (MSBs) and n least significant bits (LSBs), below which Assume that ip_ref_r includes m + n digits and cur_inc_r n digits.

The sign bit of BND-ip_ref_r is "0" if BND-ip_ref_r is positive or equal to 0, and is "1" if BND-ip_ref_r is negative.

The n LSBs of BND-ip_ref_r include the n lowest digits of the digital value of BND-ip_ref_r.

In addition, the m MSBs of BND-ip_ref_r include the remaining m (highest) digits of BND-ip_ref_r.

The output of the subtractor 301 is the first input to the adder 302 about the connection 320a provided and also over the connection 320b transferred which into three separate connections 321 . 322 and 323 branched. The connection 321 transmits the sign bit of BND-ip_ref_r as a first input to the OR circuit 311 , the connection 322 transmits the m most significant bits as the first input to the equality comparator 303 , and the connection 323 transfers the n least significant bits to a variety of equality comparators 304a - 304k.

The equality comparator 303 examines whether each of the m MSBs of BND-ip_ref_r is zero (provided for a second input from comparator 303 ) and represents the result as a logical bit ( 1 = true, 0 = false) for a first input of the AND circuit 308 ready.

The equality comparators 304a - 304k investigate whether the n LSBs of BND-ip_ref_r are equal to any possible increments inci, ie with any inc _i in 0 max (cur_inc_r). The equality comparators 304b - 304k put their corresponding results as logical bits ( 1 = true, 0 = untrue) for the first inputs of the AND circuits 306b - 306k via the corresponding connections 326b - 326K ready, the output of the equality comparator 304a directly with an input of the OR circuit 310 about the connection 327a connected is.

Each of the size comparators 305b - 305k receives the digital value from cur_inc_r as a first input and examines whether cur_inc_r is greater than or equal to one of the possible increments inci, starting with the value 2 up to max (cur_inc_r),; (The possible increments inci are used as corresponding second inputs for the comparators 305b - 305k provided). The results are presented as logical bits ( 1 = true, 0 = false) for the respective second inputs of the corresponding AND circuits 306b - 306k about the respective connections 325b - 325k provided.

Each of the respective outputs of the AND circuits 306b - 306k is used as another input for the OR circuit 310 about the connections 327b - 327k provided.

The AND circuit 308 receives (as described) the output of the equality comparator 303 as the first input and in addition to this the output of the OR circuit 310 as a second input and provides its generated output as a second input for the OR circuit 311 about the connection 328 ready.

The OR circuit 311 receives (as described) the sign bit from BND-ip_ref_r and the output of the AND circuit 308 as inputs and puts the generated output over the connection 329 as the first input for the AND circuit 309 ready.

The adder 302 adds the output of the subtractor 301 to digital value RNG (received as second input on adder 302 ) and outputs a sum digital value of BND-ip_ref_r + RNG, comprising a sign bit, m MSBs and n LSBs.

The AND circuit 309 receives the minus sign bit from BND-ip_ref_r + RNG over the connection 330 as the second input and (as described) the output of the OR circuit 311 about the connection 329 as the first entry. The output bit of the AND circuit 309 that the final edition of the circuit in 3 indicates that at least one of the plurality of values of ip_ref_r + inci satisfies inequalities 2 and 3a when it is “1” (1 = true), and indicates that no value of the plurality of values of ip_ref_r + inci fulfills inequalities 2 and 3a if it is "0" (0 = untrue).

In the following, the investigation of inequality 1 is viewed from a slightly different perspective. Since in many applications, such as the logging of PC values, it is not essential to know exactly which value, for example a PC value, in a predetermined area, for example a programmed area (BND ... BND + RNG ), the investigation of inequality 1 can be simplified as follows: inequality 1 can be reformulated to a simple problem of set theory: since the PC values examined also have a range or an interval of discrete values (ip_ref_r ... ip_ref_r + inc _i ), the investigation of inequality 1 can each be viewed as an examination of the intersection of two sets of values or two ranges of values. Accordingly, inequality 1 is true if the intersection of the two value ranges comprises at least one value; however, inequality 1 is untrue if the intersection of the two value ranges is empty.

However, it should be noted that the last conclusions, strictly speaking, are only valid for two continuous ranges of values. Otherwise, if a range of values is discrete, the intersection of the two ranges of values may be empty, even if the lower / upper limit of one range of values is in each case smaller / larger than the lower / upper limit of the other range, an increment of the discrete range of values being greater than the entire other range of values.

However, in certain applications, such as when logging a PC value in a microprocessor, it may be desirable to consider the discrete range of increments as an actually continuous range that includes all valid values between the corresponding increments.

Accordingly, a solution to the above problem may include examining the thresholds of the two ranges. If the lower limit of one value range is greater than the upper limit of the other value range, the intersection of the two value ranges is empty.

Otherwise, the cut includes at least one value.

und $$\text{ip\_ref\_r}\le \text{BND}+\text{RNG}$$

Inequality 1 can thus be simplified if it is divided into two partial inequalities: $$\text{BND}\le \text{ip\_ref\_r}+\text{cur\_inc\_r}$$

and $$\text{ip\_ref\_r}\le \text{BND}+\text{RNG}$$

However, if the values to be examined have a high absolute value, a hardware solution to accurately implement the above approach requires large and expensive size comparators to compare high values (e.g. 24 or 32 bit values or even higher values).

und $$\text{0}\le \text{BND}-\text{ip\_ref\_r}+\text{RNG}$$

For this reason, ip_ref_r is subtracted on both sides of inequalities 2b and 3b and inequalities 2b and 3b are as follows: $$\text{BND}-\text{ip\_ref\_r}\le \text{cur\_inc\_r}$$

and $$\text{0}\le \text{BND}-\text{ip\_ref\_r}+\text{RNG}$$

In this way, only significantly smaller values have to be compared in order to examine inequalities 2b 'and 3b'.

Inequality 2b 'can be further simplified for hardware implementation as follows: $$\text{BND}-\text{ip\_ref\_r}-\text{cur\_inc\_r}\le \text{0}$$

Thus, only two sign studies need to be performed to examine inequalities 2b "and 3b ': for equation 2b", the sign of the value of BND-ip_ref_r-cur_inc_r must be examined, and for equation 3b', the sign of the value of BND-ip_ref_r + RNG are examined. A corresponding embodiment of the invention is subsequently described in detail with reference to FIG 4 described.

4 shows a circuit according to an embodiment of the invention, which represents a hardware implementation of an investigation of inequalities 2b "and 3b '.

The circuit of 4 includes a subtractor 401 , which receives the values of BND and ip_ref_r as first and second input and generates a difference value BND-ip_ref_r.

The output of the subtractor 401 , BND-ip_ref_r, is used as a first input for the subtractor 431 about the connections 440 and 440a and also as a first input for the adder 402 about the connections 440 and 440b provided.

The subtractor 431 additionally receives the value of cur_inc_r (as a second input) and subtracts cur_inc_r from the output of the subtractor 401 , BND-ip_ref_r to generate a difference value BND-ip_ref_r-cur_inc_r. The comparator 432 receives the difference value and examines whether the difference value of BND-ip_ref_r-cur_inc_r is less than or equal to zero. If the difference value of BND-ip_ref_r-cur_inc_r is less than or equal to zero, the comparator provides 432 a logical "1" (true) for a first input of the AND circuit 409 about the connection 443 and a logical "0" (false) ready if the difference value of BND-ip_ref_r-cur_inc_r is greater than zero.

The adder 402 receives the output of the subtractor as described 401 BND-ip_ref_r as a first input and the value of RNG as a second input and gives a sum value BND-ip_ref_r + RNG for the comparator 433 about the connection 442 out.

The comparator 433 examines whether the total value of BND-ip_ref_r + RNG is greater than or equal to zero. If the total value of BND-ip_ref_r + RNG is greater than or equal to zero, the comparator provides 433 a logical “1” (true) for a second input of the AND circuit 409 about the connection 444 and a logical "0" (false) ready if the total value of BND-ip_ref_r + RNG is less than zero.

The AND circuit 409 receives the outputs of the comparators as described 432 and 433 as inputs and provides a logical "1" (true) only if the outputs of the comparators 432 and 433 both are true; otherwise it provides a logical "0" (false).

The output of the AND circuit 409 which is also the final edition of the circuit of 4 is therefore true ("0") if both inequalities 2b "and 3b 'are fulfilled and otherwise false (" 1 ").

11 comparator circuit 12 pretrigger 13 input 14 input 15 input 16 input signals 17 comparator 21 value range 22 value range 23 value range 24 value range 25a value range 25b value range 26 value range 301 subtractor 302 adder 303 equality comparator 304a-k Gleichheitskomparatoren 305b-k magnitude comparators 306b-k AND circuits 308 AND circuit 309 AND circuit 310 OR circuit 311 OR circuit 320a connection 320b connection 321 connection 322 connection 323 connection 324 connection 325b-k links 326b-k links 327a-k links 328 connection 329 connection 330 connection 401 subtractor 402 adder 409 AND circuit 431 subtractor 432 magnitude 433 magnitude 440 connection 440a connection 440b connection 441 connection 441 connection 443 connection 444 connection

Claims (2)

Microprocessor, with a program logging unit which has a circuit for evaluating a multiplicity of program counter (PC) values for generating breakpoint control signals for the program logging unit, the circuit examining whether at least one program counter (PC) value from the multiplicity of Program Counter (PC) - values which form a second value range lie within a predetermined first value range (BND ... BND + RNG), the first value range and the second value range being continuous value ranges, and the second value range covering the range ip_ref_r ... ip_ref_r + cur_inc_r, where ip_ref_r represents the old PC value of the previous clock cycle, and cur_inc_r represents the maximum increment of the current clock cycle, and wherein the circuit comprises: a first subtractor (401) which receives signals representing the lower limit value of the first value range (BND) and the lower limit value of the second value range (ip_ref_r), and for generating a first subtraction result signal representing the first limit value of the second value range (ip_ref_r) subtracted from the lower limit of the first range of values (BND); a second subtractor (431) which receives the first subtraction result signal representing the first subtraction result from the first subtractor (401) and subtracts the received maximum increment of the second value range cur_inc_r from the first subtraction result to generate a second subtraction result signal representing a second subtraction result; a first comparator (432) which receives the second subtraction result signal representing the second subtraction result from the second subtractor (431) and examines whether the second subtraction result from the second subtractor (431) is less than or equal to zero, and if so, a true value outputs a signal representing, and if not, outputs a signal representing a false value; an adder (402) which receives the first subtraction result signal representing the first subtraction result from the first subtractor (401), receives a signal (RNG) representing the width of the second range of values, and a signal representing a sum value of the first subtraction result and the width of the second range of values outputs; a second comparator (433), which receives the signal representing the sum value from the adder (402), and examines whether the sum value is greater than or equal to zero, and if so, outputs a signal representing a true value, and if no, a one Outputs a false value signal; and an AND circuit (409) which receives the signals representing a true or false value from the first (433) and second comparator (432), and outputs a result signal representing a true value when the signal from the first (433) and second comparator (443) received signals both represent a true value, and otherwise outputs a result signal representing a false value. Microprocessor after Claim 1 , wherein the microprocessor is designed as a superscalar processor.

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