DE102007035857A1 - Fabricating an integrated circuit with a resistance change memory device, comprises forming a second conducting layer on or above a first conducting layer of a compound structure, and structuring the second conducting layer - Google Patents

Abstract

The method for fabricating an integrated circuit with a resistance change memory device, comprises forming a second conducting layer on or above a first conducting layer of a compound structure, which comprises a resistance change layer and a first conducting layer, which is intended on or above the resistance change layer, and structuring the second conducting layer in such a manner that a part of the structured second conducting layer is useful as via for contacting the first conducting layer. An insulating layer is intended on the structured second conducting layer. The method for fabricating an integrated circuit with a resistance change memory device, comprises forming a second conducting layer on or above a first conducting layer of a compound structure, which comprises a resistance change layer and a first conducting layer, which is intended on or above the resistance change layer, and structuring the second conducting layer in such a manner that a part of the structured second conducting layer is useful as via for contacting the first conducting layer. An insulating layer is intended on the structured second conducting layer, and the thickness of the insulating layer is reduced using a chemical-mechanical polishing process, until the vertical level of the top side of the second insulating layer is same or lower than the vertical level of the top sides of the structured second conducting layer. The compound structure is structured, after the second conducting layer is structured. The second conducting layer is separated using a physical vapor deposition-process at 300[deg] C. The structuring of the second conducting layer is implemented, in that a first mask layer is formed on the second conducting layer and is structured using a lithography process. The second conducting layer is structured, where the structured first mask layer acts as mask for structuring the second conducting layer. The structuring of the compound structure is carried out, in which a second mask layer is deposited on the compound structure and is structured using a lithography process. The compound structure is structured, where the structured second mask layer acts as mask for structuring the compound structure. The second mask layer consists of an insulating material. The second mask layer and the insulating layer are made of same material. The insulating layer is formed on the structured second mask layer. Independent claims are included for: (1) an integrated circuit with a memory device; (2) a cell with a compound structure and a conducting via; (3) a memory module; and (4) a computer system.

Description

The The invention relates to a method for producing a memory device, a memory device, a cell, an integrated circuit, a memory module and a computer system.

Of the Invention underlying task is a method for manufacturing an integrated circuit having a resistance change memory device indicate that it allows integrated circuits with increased reliability manufacture.

to solution To this end, the invention provides a method for the production an integrated circuit according to claim 1 ready. Furthermore, the invention provides a method for manufacturing an integrated circuit according to claim 14 ready. Furthermore, the invention provides an integrated circuit according to claim 19 and a cell according to claim 29 ready. After all the invention provides a memory module according to claim 30 and a Computer system according to claim 32 ready. Advantageous embodiments or further developments of The idea of the invention can be found in the subclaims.

Of the For the sake of simplicity, it is assumed below that the resistance change memory device a solid state electrolyte storage device, and the resistance change layer a Solid electrolyte layer is. However, the invention is also applicable to other resistance change memory devices and resistance change layers applicable.

According to one embodiment The invention relates to a method for producing a solid state electrolyte storage device provided, the method comprising: providing a Composite structure with a solid electrolyte layer and a first conductive layer disposed on or above the solid electrolyte layer is provided; Forming a second conductive layer on or above the first conductive layer; and structuring the second conductive layer such that at least a part of the structured second conductive layer is usable as a via for contacting the first conductive layer.

According to one embodiment The invention will integrate a method for producing a Circuit with a solid state electrolyte storage device provided, the method comprising: providing a Composite structure with a solid electrolyte layer and a first conductive layer disposed on or above the solid electrolyte layer is provided; Forming a second conductive layer on or above the first conductive layer; and structuring the second Conductive layer such that at least a part of the structured second conductive layer as a via for contacting the first conductive layer is usable.

According to this embodiment vias are formed for contacting the first conductor layer, by placing the second conductor layer on top of the first conductor layer was applied, is structured. Then areas between the remaining Parts of the second conductive layer are filled with insulating material. Compared with standard methods for creating vias (according to standard methods an insulating layer is deposited on the first conductive layer; then trenches are generated within the isolation layer; finally become the trenches filled with conductive material, with the filled trenches representing the vias) has the method of generating the vias according to this embodiment the effect that delamination of the solid electrolyte layer due the generation of vias is less likely. So that can quality and the reproducibility of solid state electrolyte storage devices, the according to the procedure this embodiment can be improved.

According to one embodiment The invention provides an insulating layer on the structured second Provides conductive layer. The thickness of the insulation layer is reduces until the vertical level of the top of the second insulation layer below the vertical level of the top of the textured second conductive layer falls or matches.

According to one embodiment of the invention, the composite structure after structuring the second Structured conductor layer. In this way the danger can be a delamination of the solid electrolyte layer be further reduced.

According to one embodiment the invention, the second conductive layer tungsten (W) on or consists of this.

According to one embodiment According to the invention, the second conductive layer is deposited under Using a PVD (Physical Vapor Deposition) process. However, you can also other deposition methods such as CVD (chemical vapor deposition) be used.

According to one embodiment The invention is the PVD process carried out at temperatures below 300 ° C.

According to one embodiment The invention has the solid electrolyte layer Chalcogenide on or consists of this.

According to one embodiment The invention reduces the thickness of the insulating layer Use of a chemical-mechanical polishing process (CMP).

According to one embodiment According to the invention, the material of the second mask layer is insulating Material on or consists of, for example, oxide.

According to one embodiment According to the invention, the material of the second mask layer is the same Material on like that of the insulation layer or consists of it.

According to one embodiment the invention, the insulating layer on the structured second Mask layer formed.

According to one embodiment The invention is the structuring of the second conductive layer executed by forming a first mask layer on the second conductor layer is the first mask layer using a lithography process is structured, and the second conductive layer is structured, wherein the structured first mask layer as a mask for structuring the second conductive layer is used.

According to one embodiment According to the invention, the structuring of the composite structure is carried out by a second mask layer is deposited on the composite structure The second mask layer is patterned using a lithography process, and the composite structure structured with the structured second mask layer as mask for Structuring the composite structure is used.

According to one embodiment The invention relates to a method for producing a solid electrolyte memory cell provided comprising: providing a composite structure with a solid electrolyte layer and a first conductive layer disposed on or above the solid electrolyte layer is arranged; Forming a second conductive layer on or above the first conductive layer; Depositing a first mask layer on or above the second mask layer; Structuring the first Masking layer (eg, using a lithography process); Structure the second conductive layer such that at least a part of structured second conductive layer as a via for contacting the first conductive layer is usable, wherein the structured first mask layer as a mask for patterning the second conductive layer is used; Removing the patterned first mask layer, depositing a second mask layer on or above the composite structure, Patterning the second mask layer (using, for example, a lithography process); Structuring the composite structure, wherein the structured second mask layer as a mask for structuring the composite structure is used; Depositing an insulation layer on or above the structured composite structure; and reduce the Thickness of the insulation layer until the vertical level of the top the second insulating layer is equal to or lower than that vertical level of the top of the structured second conductive layer.

According to one embodiment The invention relates to a method for producing an integrated Circuitry provided, which is a solid state electrolyte storage cell includes. The method comprises: providing a composite structure with a solid electrolyte layer and a first conductive layer disposed on or above the solid electrolyte layer is arranged; Forming a second conductive layer on or above the first conductive layer; Depositing a first mask layer on or above the second mask layer; Structuring the first Masking layer (eg, using a lithography process); Structure the second conductive layer such that at least a part of structured second conductive layer as a via for contacting the first conductive layer is usable, wherein the structured first mask layer as a mask for patterning the second conductive layer is used; Removing the patterned first mask layer, depositing a second mask layer on or above the composite structure, Patterning the second mask layer (using, for example, a lithography process); Structuring the composite structure, wherein the structured second mask layer as a mask for structuring the composite structure is used; Depositing an insulation layer on or above the structured composite structure; and reduce the Thickness of the insulation layer until the vertical level of the top the second insulating layer is equal to or lower than that vertical level of the top of the structured second conductive layer.

According to one embodiment According to the invention, the thickness reduction is carried out using a chemical mechanical Polishing process (CMP).

According to one embodiment the invention, the second conductive layer tungsten on or consists of this.

According to one embodiment According to the invention, the second conductive layer is deposited under Using a PVD process.

According to an embodiment of the invention The PVD process is carried out at temperatures below 300 ° C.

According to one embodiment The invention is a solid state electrolyte storage device provided comprising: a composite structure having a solid electrolyte layer and an electrode layer on or above the solid electrolyte layer is arranged; and at least one conductive via, above the electrode layer is arranged, wherein the at least one conductive Directly contacted via the electrode layer.

Of the Expression "direct" means that no interlayer conductive material between the at least one via and the electrode layer and / or between the at least one via and insulating material, at least a via is provided. For example, according to a embodiment the invention no adhesive layer between the at least one via and the electrode layer provided: normally, as already has been indicated, an insulating layer on the electrode layer intended. Then, the insulation layer is patterned to a Trench structure to create within the isolation structure. The Trench structure is filled with conductive material, thus forming the vias become. To ensure adequate adhesion between the vias and the Electrode layer and / or the insulating material that the vias surrounds, produces, an adhesive layer on the insulating layer formed after the trench structure has been formed, thereby the entire surface the trench structure or at least a part thereof is covered. According to this Embodiment can such an adhesive layer is omitted. Consequently, thereby simplifies the manufacturing process of the solid state electrolyte storage device. An intermediate layer can be omitted, as an intermediate layer such as an adhesive layer or seed layer, not necessarily needed The methods for generating vias according to embodiments of the invention perform.

According to one embodiment of the invention includes the at least one via tungsten thereof.

According to one embodiment According to the invention, the at least one via is insulating in a layer Embedded material, with the vertical level of the top the layer of insulating material is equal to or lower than the vertical level of the top of the at least one vias.

According to one embodiment According to the invention, the electrode layer has a lower part and an upper part made up of different materials consist.

According to one embodiment invention, the lower part comprises silver or consists of and the upper part comprises tantalum nitride or copper thereof.

According to one embodiment of the invention the thickness of the upper part between 50 nm to 150 nm.

According to one embodiment of the invention the thickness of the at least one vias between 250 nm and 400 nm.

According to one embodiment The invention provides a cell comprising: a composite structure with a solid electrolyte layer and an electrode layer on or above the solid electrolyte layer is provided; and at least one conductive via, above the electrode layer is provided, wherein the at least one conductive via the electrode layer directly contacted. The cell may for example be a memory cell. However, the invention is not limited to this. For example, the cell can also be used as an adjustable resistance unit in any electrical device such as an adjustable electrical resistance are used.

According to one embodiment The invention provides a memory module which, at least an integrated circuit, a memory device or a memory cell according to a embodiment of the invention. According to one embodiment According to the invention, the memory module is stackable.

The Invention will be described below with reference to the figures, for example embodiments explained in more detail.

It demonstrate

1A a schematic cross-sectional view of a solid state electrolyte storage cell in a first storage state;

1B a schematic cross-sectional view of a solid state electrolyte storage cell in a second memory state;

2A a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

2 B a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

2C a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

3A a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

3B a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

3C a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

3D a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

3E a manufacturing stage of a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention;

4 FIG. 12 shows a flowchart of a method for manufacturing a solid state electrolyte storage device according to an embodiment of the invention; FIG.

5 FIG. 12 shows a flowchart of a method for manufacturing a solid state electrolyte storage device according to an embodiment of the invention; FIG.

6 shows a schematic cross-sectional view of a portion of a solid state electrolyte storage device according to an embodiment of the invention;

7 shows a schematic representation of a computer system according to an embodiment of the invention;

8A shows a perspective view of a memory module according to an embodiment of the invention;

8B shows a perspective view of a memory module according to an embodiment of the invention;

9 shows a cross-sectional view of a phase change memory cell;

10 shows a schematic representation of a memory device with resistance change memory cells;

11A shows a cross-sectional view of a carbon storage cell in a first switching state;

11B shows a cross-sectional view of a carbon storage cell in a second switching state;

12A shows a schematic representation of a resistance change memory cell; and

12B shows a schematic representation of a resistance change memory cell.

In the characters can identical or corresponding areas, components and Component groups should be marked with separate reference numbers. It should also be noted that the figures are not to scale need to be.

Since the embodiments of the present invention are applicable to programmable metallization cells (PMCs) such as conductive bridging random access memory (CBRAM) devices, in the following description with reference to FIG 1a and 1b explaining an important principle underlying CBRAM devices.

A CBRAM cell has a first electrode 101 , a second electrode 102 and a solid electrolyte block (also known as an ion conductor block) 103 that is between the first electrode 101 and the second electrode 102 is arranged on. The solid electrolyte block may also be shared by multiple memory cells (not shown here). The first electrode 101 contacts a first surface 104 of the solid electrolyte block 103 , the second electrode 102 contacts a second surface 105 of the solid electrolyte block 103 , The solid-state electrolyte block 103 is opposite its environment by an isolation structure 106 isolated. The first surface 104 is usually the top, the second surface 105 the bottom of the solid electrolyte block 103 , The first electrode 101 is usually the upper electrode, the second electrode 102 the lower electrode of the CBRAM cell. One of the first and second electrodes 101 . 102 One is a reactive electrode, the other is an inert electrode. For example, the first electrode 101 the reactive electrode, and the second electrode 102 the inert electrode. In this case, the first electrode 101 for example, from silver (Ag), the solid electrolyte block 103 from chalcogenide material, and the isolation structure 106 consist of SiO ₂ or Si ₃ N ₄ . The second electrode 102 may alternatively or additionally nickel (Ni), platinum (Pt), iridium (Ir), rhenium (Re), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), vanadium (V), may include conductive oxides, silicides, and nitrides of the aforementioned materials, and may further include alloys of the aforementioned materials. The thickness of the ion conductor block 103 may for example be 5 nm to 500 nm. The thickness of the first electrode 101 may for example be 10 nm to 100 nm. The thickness of the second electrode 102 For example, it may be 5 nm to 500 nm, 15 nm to 150 nm, or 25 nm to 100 nm. The embodiments of the invention are not limited to the above-mentioned materials and thicknesses.

According to one embodiment of the invention, chalcogenide material (more generally: the material of the ion conductor block 103 ) to understand a compound having oxygen, sulfur, selenium, germanium and / or tellurium. According to one embodiment of the invention, chalcogenide material is a compound of a chalcogenide and at least one metal of group I or group II of the periodic table, for example arsenic trisulfide silver. Alternatively, the chalcogenide material contains germanium sulfide (GeS _x ), germanium selenide (GeSe _x ), tungsten oxide (WO _x ), copper sulfide (CuS _x ) or the like. Furthermore, the chalcogenide material may include metal ions, wherein the metal ions may be a metal selected from a group consisting of silver, copper, and zinc, or a combination or alloy of these metals. The ion conductor block 103 may consist of solid electrolyte material.

When a voltage across the solid electrolyte block 103 falls off, as in 1a is indicated, a redox reaction is set in motion, the Ag ⁺ ions from the first electrode 101 comes out and into the solid-state electrolyte block 103 into where they are reduced to silver. In this way, silver-containing clusters 108 in the solid electrolyte block 103 educated. When the voltage across the solid electrolyte block 103 decreases long enough, increases the size and number of silver-rich clusters within the solid electrolyte block 103 so strong that a conductive bridge (conductive path) 107 between the first electrode 101 and the second electrode 102 is trained. When the in 1b shown voltage across the solid electrolyte block 103 drops (inverse voltage compared to the in 1a shown voltage), a redox reaction is set in motion, the Ag ⁺ ions from the solid electrolyte block 103 out to the first electrode 101 drives, where they are reduced to silver. This will change the size and number of silver-rich clusters 108 within the solid electrolyte block 103 reduced. If this happens long enough, the conductive bridge becomes 107 deleted.

To determine the current memory state of the CBRAM cell, a measurement current is passed through the CBRAM cell. The measuring current experiences a high resistance when in the CBRAM cell no conductive bridge 107 is formed, and experiences a low resistance when in the CBRAM cell a conductive bridge 107 is trained. For example, a high resistance represents logic "0", whereas a low resistance logically represents "1" or vice versa. Instead of a measuring current, a measuring voltage can also be used.

In the following description reference should be made to 2A to 2C a method for manufacturing a solid state electrolyte storage device according to an embodiment of the invention will be explained.

At a first stage of the process ( 2A ) becomes a composite structure 201 provided a solid electrolyte layer 202 and a first conductive layer 203 having. The solid electrolyte layer 202 For example, it may comprise or consist of chalcogenide material, the first conductive layer 203 For example, it may comprise or consist of silver (Ag) or copper (Cu). In a second stage of the process ( 2 B ) becomes a second conductive layer 204 on the first conductor layer 203 arranged. The second conductive layer 204 For example, it can contain or consist of tungsten (W). In a third stage of the process ( 2C ) becomes the second conductive layer 204 structured. At least a part 205 the second conductive layer 204 , which is not removed by means of the structuring process, can be used as a via to the contact of the first conductor layer 203 serve. To the parts 205 For example, insulating material can be used as vias in the trenches / columns / regions 206 between the parts 205 the second conductive layer 204 , which are generated by the structure process, are filled.

In the following description is with reference to 3A to 3E a procedure 300 for manufacturing a solid state electrolyte storage device according to an embodiment of the invention.

3A shows a manufacturing stage in which a composite structure 201 with a solid electrolyte layer 202 and a first conductive layer 203 on a structure 301 having a plurality of electrodes, electric wires, selection means and the like. In detail:
3A shows a structure 301 with a bottom electrode layer 313 with several bottom electrodes 314 , Each bottom electrode 314 has a first plug 3141 and a second plug 314 ₂ which are stacked in this order. The second plugs 3142 contact the solid state electrolyte layer 202 directly. The bottom electrodes 314 are against each other by means of a first insulating layer 318 ₁ and a second insulation layer 318 ₂ isolated, which are stacked in this order. The first plugs 314 ₁ be from first adhesive layers 331 ₁ covered with the exception of their tops, which is the solid electrolyte layer 202 contact directly. The bottoms of the first plugs 314 ₁ are with the second plugs 314 ₂ that is below the first plugs 314 ₁ are arranged, electrically connected, wherein the second plugs 3142 through second adhesive layers 331 ₂ are covered. The bottoms of the second plugs 314 ₂ are (indirectly via second adhesive layers 331 ₂ ) with first conductive contacts 332 electrically connected (eg, polysilicon contacts) extending through an insulating layer 333 , which are below the first insulation layer 318 ₁ is arranged, through into a substrate 334 extends into it. At the junction between the conductive contacts 332 and the substrate 334 are areas 335 of the opposite conductivity type as that of the substrate 334 within the substrate 334 educated. bit 336 are within the first insulation layer 318 ₁ educated. Furthermore, wordlines 337 within the insulation layer 333 educated. The bitlines 336 are with the areas 335 via second conductive contacts 338 electrically connected (for example, polysilicon contacts). The wordlines 337 are with conductive elements 339 electrically connected (eg, polysilicon contacts) extending to the top of the substrate 334 extend, but through insulation layers 340 (Gate insulation layers) against the substrate 334 are isolated. Furthermore, isolation areas 341 , which consist of insulating material, within the substrate 334 , the isolation areas 341 , the appropriate senior contacts 338 disable, and the conductive elements 339 , above the isolation areas 341 are arranged, formed.

The guiding elements 339 act as gates, the areas 335 as source areas and drainage areas. Each bottom electrode 314 can be selected by a wordline 337 and a bit line 336 is selected. In this case, a current flows through the selected bottom electrode 314 , the corresponding first conductive contact 332 , the area of the substrate 334 that is below the selected word line 337 is located, and the corresponding second conductive contact 332 to the selected bit line 336 , For example, a rung 342 be formed under the assumption that the word line 337 ₁ and the bit line 336 ₁ to be selected. Any structure that has a first conductive contact 332 , an area on the substrate 334 that is below the selected word line 337 lies, a second conductive contact 332 and a bit line 336 can be interpreted as a selection device.

The first conductor layer 203 has a top electrode layer 302 on, for example, include or may consist of silver, and a conductor layer 303 above the top electrode layer 302 , which is, for example, tantalum nitride (TaN) comprises or consists thereof. A second conductor layer 204 is on top of the conduction layer 303 provided, ie on top of the composite structure 201 , The thickness of the second conductive layer 204 may for example be between 250 nm and 400 nm, ie, for example 300 nm. The second conductive layer 204 For example, tungsten may have or consist of. The second conductive layer 204 For example, on the composite structure 201 are deposited using a PVD (Physical Vapor Deposition) process. For example, the PVD process can be performed at temperatures below 300 ° C. An effect resulting from the use of temperatures below 300 ° C is that the risk of delamination of the solid electrolyte layer 202 (For example, a chalcogenide layer) can be greatly reduced. The thickness of the conductor layer 303 may for example be 50 nm to 150 nm, for example 100 nm.

3B shows a manufacturing stage that is obtained after the second conductive layer 204 up to a vertical level of the top of the conductive layer 303 has been structured down. Here was the entire second conductor layer 204 removed by the structuring process, with the exception of one part 205 that serves as the Via. The invention is not limited to the production of a single part 205 limited. Instead, the structuring process of the second conductive layer 204 also be carried out so that the second conductive layer 204 in several parts 205 is structured, whereby two or more conductive vias are generated. The process of structuring the second conductive layer 204 For example, it may be performed by placing a first mask layer (not shown) on the second conductive layer 204 depositing, thereby patterning the first mask layer using a lithography process, and the second wiring layer 204 is patterned using the patterned first mask layer as a mask for patterning the second conductive layer 204 ,

3C shows a manufacturing process stage in which an insulation layer 304 on the top of the in 3B has been deposited, ie on the top of the exposed Lei tung layer 303 and on the top and side surfaces of the parts 205 the second conductive layer 204 after the structuring process of the second conductive layer 204 remain. The insulation layer 304 For example, it may be an oxide layer.

3D shows a manufacturing stage in which the insulation layer 304 has been patterned (ie, removed) within the periphery of the solid state electrolyte storage device to be fabricated (as opposed to those in US Pat 3A to 3C and 3E shows 3D essentially a peripheral area of the storage device to be produced; only an end portion of the cell area (right part) of the memory device is shown). The structuring process of the insulation layer 304 For example, it may be carried out using a lithography process. Then the composite structure 201 be patterned (using, for example, an etching process) using the patterned insulating layer 304 as a mask (not shown). Within the outskirts become several conductive elements 343 intended.

3E shows a manufacturing stage in which after structuring the composite structure 201 another insulation layer on the structured insulation layer 304 was provided. Furthermore, a composite structure 305 coming from the insulation layer 304 and further insulation layers is reduced in thickness, ie the thickness of the composite structure 305 reduced until the vertical level of the top of the composite structure 305 is equal to or lower than the vertical level of the top of the vias (part 205 the second conductive layer 204 ). In this way, the via is "opened".

4 shows a method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention.

In a first process P1, a composite structure is provided, a solid electrolyte layer and a first conductive layer disposed on the solid electrolyte layer is arranged. In a second process P2 becomes a second Conductive layer formed on the first conductive layer. In one third process P3, the second conductive layer is structured so that at least a part of the structured second conductive layer is usable as a via for contacting the first conductive layer.

5 shows another method of manufacturing a solid state electrolyte storage device according to an embodiment of the invention. In a first process S1, a composite structure having a solid electrolyte layer and a first conductive layer provided on the solid electrolyte layer is provided. In a second process S2, a second conductive layer is deposited on the first conductive layer. In a third process S3, the first mask layer is deposited on the second conductor layer. In a fourth process S4, the first mask layer is patterned using a lithography process. In a fifth process S5, the second conduction layer is structured in such a way that at least part of the structured second conduction layer is usable as a via for contacting the first conduction layer, the structured first mask layer serving as a mask for structuring the second conduction layer. In a sixth process S6, the structured first mask layer is removed. In a seventh process S7, the second mask layer is deposited on the composite structure. In an eighth process S8, the second mask layer is patterned using a lithography process. In a ninth process S9, the composite structure is structured, the structured mask layer serving as a mask for structuring the composite structure. In a tenth process S10, an insulation layer is deposited on the structured composite structure. In an eleventh process S11, the thickness of the insulating layer is reduced until the vertical level of the upper surface of the second insulating layer is equal to or lower than the vertical level of the upper surface of the patterned second conductive layer.

6 shows a solid state electrolyte storage device according to an embodiment of the invention. The solid state electrolyte storage device 600 has a composite structure 201 with a solid electrolyte layer 202 and a first conductive layer 203 on the solid electrolyte layer 202 is provided on. A conductive via 601 is on the first conductor layer 203 provided, the Via 601 of isolated material 602 is surrounded. The guiding Via 601 contacts the first conductive layer 203 directly, ie no adhesive layer or other intermediate layer such as a seed layer is between the via 601 and the insulating material 602 and / or the top of the first conductive layer 203 intended.

In accordance with an embodiment of the invention, integrated circuits / memory devices described above may be used in a variety of applications or systems, such as those disclosed in U.S. Pat 7 shown computer system. The computer system 700 has an integrated circuit / memory device 702 on. The system further comprises a processing device 704 (For example, a microprocessor, other processing device or a controller), an input and output device tion, for example a keyboard 702 , an ad 708 and / or a wireless communication device 710 on. The storage device 702 , the processing device 704 , the keyboard 702 , the ad 708 and the wireless communication device 710 are by means of a bus 712 connected with each other.

The wireless communication device 710 may be configured to transmit or receive over a telephone landline, WiFi wireless network or other wireless networks. In the 7 shown input-output devices are only examples. The integrated circuits / memory devices described above can be used in alternative systems. Alternative systems may include a variety of different / alternative input and output devices, processors, or processing devices, as well as bus configurations. Such systems may be for general or special purpose use, such as for wireless communication / landline communication, photography, playing music or other digital information, or any other known or unknown applications associated with a computer system.

As in 8A and 8B 1, embodiments of the memory devices / integrated circuits according to the invention can be used in modules. In 8A is a memory module 800 shown that one or more storage devices / integrated circuits 804 which is on a substrate 802 are arranged. Each storage device / integrated circuit 804 can contain several memory cells. The memory module 800 can also use one or more electronic devices 806 comprising memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuitry or electronic devices that may be combined with memory device (s) of a module, such as memory devices / integrated circuits 804 , Furthermore, the memory module 800 a plurality of electrical connections 808 which can be used to the memory module 800 to connect with other electronic components, such as other modules.

As in 8B As shown, these modules may be stackable to form a stack 850 train. For example, a stackable memory module 852 one or more integrated circuits / memory devices 856 included on a stackable substrate 854 are arranged. Each integrated circuit / memory device 856 can contain several memory cells. The stackable memory module 852 can also use one or more electronic devices 858 comprising memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuitry, and which may be combined with memory devices of a module, such as integrated circuits / memory devices 856 , Electrical connections 860 are used to make the stackable memory module 852 with other modules within the stack 850 connect to. Other modules of the stack 850 may be additional stackable memory modules that are the stackable memory module described above 852 or other types of stackable modules, such as stackable processing modules, communication modules, or modules containing electronic components.

According to one embodiment of the invention the resistance change memory cells a resistance change memory device phase change memory cells be, the phase change material exhibit. The phase change material can be switched between at least two crystallization states (i.e., the phase change material may assume at least two degrees of crystallization), each one Crystallization state represents a memory state. If the number of possible crystallization states is two, becomes the crystallization state having a high degree of crystallization Also referred to as "crystalline state", where against the crystallization state, which has a low degree of crystallization also known as "amorphous State " becomes. Different crystallization states can be differentiated by corresponding different electrical properties are distinguished from each other, in particular by different resistances, which are implied by this. For example, a crystallization state, a high degree of crystallization (ordered atomic structure) generally has a lower resistance than a crystallization state, which has a low degree of crystallization (disordered atomic structure). For the sake of simplicity, it shall be assumed below that that the phase change material two crystallization states can accept (an "amorphous State "and a" crystalline State "). However be mentioned that also uses additional intermediate states can be.

Phase change memory cells may transition from the amorphous state to the crystalline state (and vice versa) when temperature variations within the phase change material occur. Such temperature changes can come in different ways be called. For example, a current may be passed through the phase change material (or a voltage may be applied to the phase change material). Alternatively, a current or voltage may be supplied to a resistance heating element provided adjacent to the phase change material. In order to set the memory state of a resistance change memory cell, a sense current may be passed through the phase change material (or a sense voltage may be applied to the phase change material), thereby measuring the resistance of the resistance change memory cell representing the memory state of the memory cell.

9 shows a cross-sectional view of an exemplary phase change memory cell 900 (Active-in-via type). The phase change memory cell 900 has a first electrode 902 , Phase change material 904 , a second electrode 906 as well as insulating material 908 on. The phase change material 904 becomes lateral through the insulating material 908 locked in. A selection device (not shown) such as a transistor, a diode or other active device may be connected to the first electrode 902 or the second electrode 906 be coupled to the application of the phase change material 904 with current or voltage using the first electrode 902 and / or the second electrode 906 to control. To the phase change material 904 into the crystalline state, the phase change material 904 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 904 above the phase change material crystallization temperature, but kept below the phase change material melting temperature. If the phase change material 904 is to be converted into the amorphous state, the phase change material 904 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 904 rises rapidly above the phase change material melting temperature, with the phase change material 904 then cooled quickly.

The phase change material 904 can contain a variety of materials. According to one embodiment, the phase change material 904 comprise (or consist of) a chalcogenide alloy containing one or more elements of group VI of the periodic table. According to a further embodiment, the phase change material 904 Comprise or consist of chalcogenide composite material such as GeSBTe, SbTe, GeTe or AbInSbTe. According to a further embodiment, the phase change material 904 comprise or consist of a chalcogen-free material, such as GeSb, GaSb, InSb, or GeGaInSb. According to a further embodiment, the phase change material 904 comprise or consist of any suitable material comprising one or more of Ge, Sb, Te, Ga, Bi, Pb, Sn, Si, P, O, As, In, Se, and S.

According to one embodiment of the invention, at least one of the first electrode 902 and the second electrode 906 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or mixtures or alloys thereof (or consist thereof). According to a further embodiment, at least one of the first electrode 902 and the second electrode 906 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and two or more elements of the group: B, C, N, O, Al, Si, P, S and / or mixtures and alloys thereof (or consist of this). Examples of such materials are TiCN, TiAlN, TiSiN, W-Al ₂ O ₃ , and Cr-Al ₂ O ₃ .

10 shows a block diagram of a memory device 1000 containing a write pulse generator 1002 , a distribution circuit 1004 , Phase change memory cells 1006a . 1006b . 1006c . 1006d (For example, phase change memory cells 900 as in 9 shown) and a sense amplifier 1008 having. According to one embodiment, the write pulse generator generates 1002 Current pulses or voltage pulses representing the phase change memory cells 1006a . 1006b . 1006c . 1006d by means of the distribution circuit 1004 whereby the storage states of the phase change memory cells 1006a . 1006b . 1006c . 1006d be programmed. According to one embodiment, the distribution circuit 1004 a plurality of transistors connecting the phase change memory cells 1006a . 1006b . 1006c . 1006d or heating elements adjacent to the phase change memory cells 1006a . 1006b . 1006c . 1006d are provided to supply DC pulses or DC pulses.

As already indicated, the phase change material of the phase change memory cells 1006a . 1006b . 1006c . 1006d from the amorphous state to the crystalline state (or vice versa) by changing the temperature. More generally, the phase change material can be converted from a first degree of crystallization to a second degree of crystallinity due to a temperature change. For example, the bit value "zero" may be assigned to the first (low) degree of crystallization, and the bit value "1" to the second (high) degree of crystallization. Since different degrees of crystallization imply different electrical resistances, is the sense amplifier 1008 capable of storing one of the phase change memory cells 1006a . 1006b . 1006c or 1006d depending on the resistance of the phase change material to determine.

In order to achieve high storage densities, the phase change memory cells 1006a . 1006b . 1006c and 1006d be designed to store several bits of data (ie the phase change material can be programmed to different resistance values). For example, if a phase change memory cell 1006a . 1006b . 1006c and 1006d is programmed to one of three possible resistance levels, 1.5 data bits per memory cell are stored. If the phase change memory cell is programmed to one of four possible resistance levels, two bits of data per memory cell can be stored, and so on.

In the 10 The illustrated embodiment may similarly be applied to other resistance change memory elements such as programmable metallization cells (PMCs), magnetoresistive memory cells (eg, MRAMs), organic memory cells (eg, ORAMs), or transition metal oxide memory cells (TMOs).

Another type of resistance change memory cell that can be used is to use carbon as a resistance change material. In general, amorphous carbon rich in sp ³ -hybridized carbon (ie, tetrahedral bonded carbon) has high resistance, whereas amorphous carbon rich in sp ² -hybridized carbon (i.e., trigonal-bonded carbon) has low resistance , This resistance difference can be utilized in resistance change memory cells.

According to one embodiment of the invention, a carbon memory cell is formed in a similar manner as described above in connection with the phase change memory cells. A temperature-induced change between an sp ³ -rich state and an sp ² -rich state can be used to change the resistance of amorphous carbon material. These varying resistances can be used to represent different memory conditions. For example, an sp ³ rich state (high resistance state) may represent "zero", and an sp ² rich state (low resistance state) may represent "one". Intermediate resistance states can be used to represent multiple bits as described above.

In this type of carbon storage cell, the use of a first temperature generally causes a transition that converts sp ³ -rich amorphous carbon into sp ² -rich amorphous carbon. This transition can be reversed by the application of a second temperature, which is typically higher than the first temperature. As mentioned above, these temperatures may be generated by, for example, charging the carbon material with a current pulse and / or a voltage pulse. Alternatively, the temperatures may be generated using a resistance heating element provided adjacent to the carbon material.

Another way to utilize resistance changes in amorphous carbon to store information is the field strength induced formation of a conductive path in an insulating amorphous carbon film. For example, applying a voltage pulse or current pulse may cause the formation of a conductive sp ² filament in insulating, sp ³ -rich amorphous carbon. The operation of this resistance carbon storage type is described in FIGS 11A and 11B shown.

11A shows a carbon storage cell 1100 who have a top contact 1102 a carbon storage layer 1104 with insulating amorphous carbon material rich in sp ³ -hybridized carbon atoms and a bottom contact 1106 having. As in 11B can be shown by means of a current (or voltage) passing through the carbon storage layer 1104 is passed, an SP ² filament 1150 in the sp ³ -rich carbon storage ^layer 1104 are formed, whereby the resistance of the memory cell is changed. Applying a high energy (or reverse polarity) current pulse (or voltage pulse) may be the sp ² filament 1150 destroy what the resistance of the carbon storage layer 1104 is increased. As discussed above, the changes in resistance may be to the carbon storage layer 1104 be used to store information, for example, representing a high resistance state "zero", and a low resistance state "one". In addition, in some embodiments, intermediate levels of filament formation or formation of multiple filaments in sp ³ -rich carbon films may be used to provide multiple varying levels of resistance, thereby storing multiple bits of information in a carbon memory cell. In some embodiments, alternating sp ³ -rich carbon layers and sp ² -rich carbon layers may be employed, with the sp ³ -rich layers exciting the formation of conductive filaments such that the currents and / or voltages, can be reduced to write a value in this carbon storage type used.

The resistance change memory cells such as the phase change memory cells and the carbon memory cells described above may be provided with a transistor, a diode or other active element for selecting the memory cell. 12A shows a schematic representation of such a memory cell using a resistance change memory element. The memory cell 1200 has a selection transistor 1202 and a resistance change memory element 1204 on. The selection transistor 1202 has a source section 1206 that with a bit line 1208 is connected, a drain section 1210 that with the memory element 1204 connected, and a gate section 1212 that with a wordline 1214 is connected. The resistance change memory element 1204 is still with a common line 1216 which may be grounded or connected to another circuit, such as a circuit (not shown) for determining the resistance of the memory cell 1200 what can be used in reading operations. Alternatively, in some configurations, a circuit (not shown) for determining the state of the memory cells 1200 during the read operation with the bit line 1208 be connected.

When in the memory cell 1200 will be described, the word line 1214 for selecting the memory cell 1200 used, and the resistance change memory element 1204 is done with a current pulse (or voltage pulse) using the bit line 1208 applied, whereby the resistance of the resistance change memory element 1204 will be changed. Similarly, when out of the memory cell 1200 is read, the word line 1214 used the cell 1200 and the bit line 1208 is used to change the resistance change memory element 1204 to apply a read voltage or a read current to the resistance of the resistance change memory element 1204 to eat.

The memory cell 1200 may be referred to as a 1T1J cell because it includes a transistor and a memory transition (the resistance change memory element 1204 ) uses. Typically, a storage device comprises an array having a plurality of such cells. Instead of a 1T1J memory cell, other configurations may be used. For example, in 12B an alternative construction of a 1T1J memory cell 1250 shown in which a selection transistor 1252 and a resistance change memory element 1254 are arranged in a different way compared to that in 12A shown construction. In this alternative construction, the resistance change storage element is 1254 with a bit line 1258 as well as with a source section 1256 of the selection transistor 1252 connected. A drain section 1260 of the selection transistor 1252 is with a common line 1266 which may be grounded or connected to another circuit (not shown) as discussed above. A gate section 1262 of the selection transistor 1252 is by means of a wordline 1264 controlled.

According to one embodiment The invention provides storage devices of increased quality and increased reproducibility.

In The following invention is intended to further exemplary embodiments of the invention explained become.

According to one embodiment The invention relates to a delamination of chalcogenide during the VC via education avoided.

In Standard manufacturing process, the top BEOL contact is made to the CBRAM chalcogenide plate, after the PL structuring process (structuring process the composite structure comprising a solid electrolyte layer and a Electrode layer disposed on the solid electrolyte layer is, has) executed has been. If after VC etching the Standard tungsten deposition is used, can cause delamination of the structured chalcogenide.

According to one embodiment The invention is the VC tungsten plug be generated before the chalcogenide is structured, and the Tungsten deposition can be performed are using a PVD process at low temperature (less than 300 ° C). Without structuring chalcogenide and using a Tungsten low temperature deposition can avoid delamination become.

According to one embodiment According to the invention, the VC contact can be performed before the PL structures is using a PVD tungsten deposition. The VC structuring can accomplished be by etching of tungsten and a subsequent oxide deposition. The secluded Oxide is used as a hard mask during of the PL etching process used. After the PL etching process a new oxide deposition is performed and a planarization process (for example, a CMP process), which "opens" the VC plug.

According to one embodiment of the invention, first PL etching, then VC etching and ei a filling process of tungsten at a deposition temperature of 350 ° C.

According to one embodiment of the invention, the integration scheme is as follows:
Chalcogenide deposition and silver deposition
TaN deposition (heating process can be performed if necessary)
PVD tungsten deposition
Lithography etching structuring (VC level)
Oxide deposition (hard mask)
Lithography Etching Structuring (PL Level)
Oxide deposition (VC-ILD)
Oxide CMP Planarization (Exit to W)

in the In the context of the invention, the terms "connecting" and "coupling" mean both direct and indirect Connect and couple.

100

CBRAM cell

101

first electrode

102

second electrode

103

Ion conductor block

104

first surface

105

second surface

106

isolation structure

107

senior path

 108

cluster

 200

method

201

composite structure

202

Solid electrolyte layer

203

first conductive layer

204

second conductive layer

 205

part

206

Trench / column / field

 300

method

301

structure

313

Bottom electrode layer

314

bottom electrode

318

insulation layer

331

adhesive layer

333

insulation layer

 334

substratum

 335

area

 336

bit

337

wordline

338

line contact

339

line element

340

insulation layer

341

isolation region

342

senior path

302

electrode layer

303

conductive layer

304

insulation layer

305

composite structure

600

Solid electrolyte memory device

 601

Via

602

insulating material

700

computer system

702

Resistance change memory device

704

processing device

706

keyboard

 708

display

710

communicator

 712

bus

800

memory module

802

substratum

804

Storage device / memory cell / integrated circuit

806

electronic contraption

808

electrical connection

 850

stack

852

memory module

854

substratum

856

storage device

858

electronic contraption

860

electrical connection

900

Phase change memory cell

902

first electrode

904

Phase change material

906

second electrode

908

insulating material

1000

storage device

1002

Write pulse generator

1004

distribution circuit

1006

Phase change memory cell

1100

Carbon memory cell

1102

top contact

1104

Carbon storage layer

 1106

bottom Contact

1150

filament

 1200

memory cell

 1202

selection transistor

1204

Resistance change memory element

 1206

source

 1208

bit

 1210

drain

 1212

gate

 1214

wordline

 1216

common management

 1250

memory cell

 1252

selection transistor

1254

Resistance change memory element

 1256

source

 1258

bit

 1260

drain

 1262

gate

 1264

wordline

 1266

common management

Claims (33)

A method of fabricating an integrated circuit having a resistance change memory device, the method comprising: providing a composite structure having a resistance change layer and a first line layer provided on or above the resistance change layer; Forming a second conductive layer on or above the first conductive layer; and patterning the second conductive layer such that at least a portion of the structured second conductive layer is usable as a via for contacting the first conductive layer. The method of claim 1, wherein an insulating layer is provided on the structured second conductive layer, and the thickness of the insulation layer is reduced until the vertical Level of the top of the second insulation layer equal or lower is structured as the vertical level of the tops second conductive layer. The method of claim 1 or 2, wherein the composite structure is structured after the second conductive layer is structured has been. Method according to one of claims 1 to 3, wherein the second Conductive layer tungsten (W) contains or it consists. Method according to one of claims 1 to 4, wherein the second Conductive layer is deposited using a PVD process. The method of claim 5, wherein the PVD process accomplished becomes at temperatures below 300 ° C. Method according to one of claims 1 to 6, wherein the resistance change layer Has or consists of chalcogenide. Method according to one of claims 2 to 7, wherein the thickness the insulation layer is reduced using a chemical-mechanical Polishing process (CMP). Method according to one of claims 1 to 8, wherein structuring the second conductive layer is performed by a first Mask layer is formed on the second conductive layer, wherein the first mask layer is patterned using a lithography process, and the second conductive layer structured with the structured first mask layer as mask for Structuring the second conductive layer is used. Method according to one of claims 3 to 9, wherein structuring the composite structure is deposited by depositing a second mask layer on the composite structure The second mask layer is patterned using a lithography process, and the composite structure structured with the structured second mask layer as mask for Structuring the composite structure is used. The method of claim 10, wherein the material of second mask layer comprises or consists of insulating material. A method according to claim 10 or 11, wherein the material the second mask layer, the same material as that of the insulating layer or consists of. Method according to one of claims 2 to 12, wherein the insulating layer is formed on the patterned second mask layer. Method for producing an integrated circuit with a resistance change memory cell, the method comprising: providing a composite structure with a resistance change layer and a first conductive layer provided on or above the resistance change layer is; Forming a second conductive layer on or above the first conductive layer; Depositing a first mask layer on or above the second conductive layer; Structure the first mask layer; Structuring the second conductive layer such that at least a part of the structured second conductive layer is usable as a via for contacting the first conductive layer, wherein the structured first mask layer serves as a mask for structuring the second conductive layer is used; Remove the textured first mask layer; Depositing a second mask layer or above the composite structure; Structuring the second Mask layer; Structuring the composite structure, where the structured second mask layer as a mask for structuring the Composite structure is used; Depositing an insulation layer on or above the structured composite structure; and To reduce the thickness of the insulation layer until the vertical level of the top the second insulating layer is equal to or lower than that vertical level of the top of the structured second conductive layer. The method of claim 14, wherein the reduction the thickness is executed is using a chemical-mechanical polishing process. The method of claim 14 or 15, wherein the second Conductive layer comprises or consists of tungsten. A method according to any one of claims 14 to 16, wherein the second Conductive layer is deposited using a PVD process. The method of claim 17, wherein the PVD process accomplished is at temperatures below 300 ° C. Integrated circuit with a memory device, comprising: a composite structure having a resistance change layer and an electrode layer overlying the resistance change layer is provided; wherein at least one via is above the electrode layer is provided, and wherein the at least one conductive via the electrode layer contacted directly. An integrated circuit according to claim 19, wherein between the at least one via and the electrode layer no adhesive layer is provided. Integrated circuit according to Claim 19 or 20, characterized wherein the at least one via comprises or consists of tungsten. Integrated circuit according to one of Claims 19 to 21, wherein the at least one via in a layer of insulating material is embedded, with the vertical level of the top of the layer of the insulating material is equal to or lower than the vertical one Level of the top of the at least one vias. Integrated circuit according to one of Claims 19 to 22, wherein the electrode layer has a lower part and an upper part Part has, each consisting of different materials. The integrated circuit of claim 23, wherein the lower part comprises or consists of silver, and the upper part Part of tantalum nitride or copper or consists thereof. Integrated circuit according to Claim 23 or 24, characterized wherein the thickness of the upper part is 100 nm. Integrated circuit according to one of Claims 19 to 25, wherein the thickness of the at least one vias is 300 nm. Integrated circuit according to one of Claims 19 to 26, wherein the memory device comprises a programmable metallization device is. Integrated circuit according to one of Claims 19 to 27, wherein the programmable metallization device is a solid state electrolyte storage device is. Cell, with: a composite structure with a Resistance change layer and an electrode layer overlying the resistance change layer is provided; at least one conductive Via, above the electrode layer is provided, wherein the at least one conductive via the electrode layer directly contacted. Memory module with at least one resistance change layer, which has: a composite structure with a resistance change layer and an electrode layer overlying the resistance change layer is provided; at least one conductive via, above the electrode layer is provided, wherein the at least one conductive via the electrode layer directly contacted. The memory module of claim 30, wherein the memory module is stackable. Computer system, with: an input device; einre Output device; a processing device; and one Memory, wherein the memory is a composite structure with a resistance change layer and an electrode layer disposed on the resistance change layer is provided, wherein at least one conductive via above the electrode layer is provided, and the at least one conductive Directly contacted via the electrode layer. The computer system of claim 32, wherein the at least an input device and the output device a wireless Have communication device.