DE102007029829A1 - Semiconductor component, has electrical contact structure with two metallic layers, where one of metallic layers is provided on other metallic layer such that latter metallic layer is surrounded by former metallic layer - Google Patents
Semiconductor component, has electrical contact structure with two metallic layers, where one of metallic layers is provided on other metallic layer such that latter metallic layer is surrounded by former metallic layer Download PDFInfo
- Publication number
- DE102007029829A1 DE102007029829A1 DE200710029829 DE102007029829A DE102007029829A1 DE 102007029829 A1 DE102007029829 A1 DE 102007029829A1 DE 200710029829 DE200710029829 DE 200710029829 DE 102007029829 A DE102007029829 A DE 102007029829A DE 102007029829 A1 DE102007029829 A1 DE 102007029829A1
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- metal layer
- metal
- layer
- semiconductor body
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 229910052751 metal Inorganic materials 0.000 claims abstract description 148
- 239000002184 metal Substances 0.000 claims abstract description 148
- 238000000034 method Methods 0.000 claims abstract description 30
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims abstract description 6
- 238000005275 alloying Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- 230000000877 morphologic effect Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000005566 electron beam evaporation Methods 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
Abstract
Description
Ausführungsbeispiele der Erfindung beziehen sich auf ein Halbleiterbauelement mit einem ohmschen Kontakt und ein Verfahren zum Herstellen eines ohmschen Kontaktes an einem Halbleiterkörper.embodiments The invention relates to a semiconductor device with an ohmic Contact and a method for making an ohmic contact on a semiconductor body.
Elektronische Bauelemente benötigen elektrische Zuleitungen mit geringen Verlusten. Die Widerstände der elektrischen Zuleitungen setzen sich im Einzelnen zusammen aus den Widerständen des:
- 1. Bonddraht,
- 2. Übergang Bonddraht-Metallisierung auf dem Chip,
- 3. Metallisierung auf dem Chip und
- 4. Metall-Halbleiterkontakt, auch ohmscher Kontakt genannt.
- 1. bonding wire,
- 2. Transition bonding wire metallization on the chip,
- 3. Metallization on the chip and
- 4. Metal-semiconductor contact, also called ohmic contact.
Der Kontaktwiderstand des ohmschen Kontaktes wird hauptsächlich beeinflusst durch die Dotierung des Halbleiters, die Sauberkeit der Halbleiteroberfläche, der Kontaktmetallisierung und der Legiertemperatur zur Ausbildung einer intermetallischen Phase zwischen Metallisierung und Halbleitermaterial.Of the Contact resistance of the ohmic contact is mainly influenced by the doping of the semiconductor, the cleanliness of the semiconductor surface, the Contact metallization and the alloying temperature to form a intermetallic phase between metallization and semiconductor material.
Neben einem geringen Kontaktwiderstand sollte der ohmsche Kontakt auch eine geringe Morphologie aufweisen. Dies ist vor allem dann wichtig, wenn die Strukturen und Abstände des elektronischen Bauelements sehr klein sind (μm-Bereich). Deshalb sollte eine Oberflächenwelligkeit bzw. Kantenrauhigkeit der Metallisierung gering sein. Eine größere Welligkeit ist z. B. von Nachteil, wenn bei der Fotolithographie kleiner Strukturen nur sehr dünne Lacke verwendet werden. Eine hohe Kantenrauhigkeit führt zwangsweise zu größeren Abständen der Strukturen.Next a low contact resistance ohmic contact should also have a low morphology. This is especially important when the structures and distances of the electronic component are very small (μm range). That's why one should surface waviness or edge roughness of the metallization be low. A bigger ripple is z. B. disadvantageous if in the photolithography of small structures only very thin paints be used. A high edge roughness inevitably leads to larger distances of the structures.
Vor allem bei „Wide-Band-Gap" Halbleitermaterialien wie z. B. Silizium-Carbid, bei denen hohe Legiertemperaturen für die Ausbildung des ohmschen Kontaktes notwendig sind, ist es schwierig, einen geringen Kontaktwiderstand und eine glatte Morphologie gleichzeitig zu erzielen.In front especially in "wide band gap" semiconductor materials such as As silicon carbide, where high alloying temperatures for training ohmic contact are necessary, it is difficult to a small Achieve contact resistance and a smooth morphology at the same time.
Aufgabe der vorliegenden Erfindung ist es, einen ohmschen Kontakt auf einem Halbleiterbauelement mit niedrigem Kontaktwiderstand und glatter Morphologie und ein Verfahren zum Herstellen eines solchen ohmschen Kontaktes bereitzustellen.task The present invention is an ohmic contact on a Semiconductor device with low contact resistance and smooth morphology and a method of making such an ohmic contact provide.
Gelöst wird diese Aufgabe durch die Merkmale der unabhängigen Ansprüche 1 und 12.Is solved This object is achieved by the features of the independent claims 1 and 12th
In einer Ausführungsform weist ein Halbleiterbauelement einen Halbleiterkörper und eine elektrische Kontaktstruktur auf einer Oberfläche des Halbleiterkörpers auf, wobei die elektrische Kontaktstruktur eine erste Metallschicht aus einem ersten Metall und eine zweite Metallschicht aus einem zweiten Metall auf der ersten Metallschicht umfasst, und wobei die erste Metallschicht an der Grenzfläche zum Halbleiterkörper einen ohmschen Kontakt ausbildet und die zweite Metallschicht derart ist, dass die erste Metallschicht umschlossen ist.In an embodiment For example, a semiconductor device has a semiconductor body and an electrical contact structure on a surface of the semiconductor body on, wherein the electrical contact structure, a first metal layer of a first metal and a second metal layer of one second metal on the first metal layer, and wherein the first metal layer at the interface with the semiconductor body a ohmic contact is formed and the second metal layer is such that the first metal layer is enclosed.
In einer Ausführungsform des Verfahrens zum Herstellen eines ohmschen Kontaktes an einem Halbleiterkörper wird ein Halbleiterkörper bereitgestellt, auf dem Halbleiterkörper eine erste Metallschicht aus einem ersten Metall aufgebracht, auf der ersten Metallschicht eine zweite Metallschicht aus einem zweiten Metall derart aufgebracht, dass die erste Metallschicht umschlossen wird und ein ohmscher Kontakt zwischen der ersten Metallschicht und dem Halbleiterkörper ausgebildet.In an embodiment of the method for producing an ohmic contact on a semiconductor body a semiconductor body provided on the semiconductor body, a first metal layer applied from a first metal, on the first metal layer a second metal layer of a second metal is applied in such a way that the first metal layer is enclosed and an ohmic contact formed between the first metal layer and the semiconductor body.
Vorteilhafte Weiterbildungen der Erfindung sind in den abhängigen Ansprüchen angegeben.advantageous Further developments of the invention are specified in the dependent claims.
Ausführungsbeispiele der Erfindung werden nachfolgend, Bezug nehmend auf die beiliegenden Figuren, näher erläutert. Die Erfindung ist jedoch nicht auf die konkret beschriebenen Ausführungsformen beschränkt, sondern kann auch in geeigneter Weise modifiziert und abgewandelt werden. Es liegt im Rahmen der Erfindung, einzelne Merkmale und Merkmalskombinationen einer Ausführungsform mit Merkmalen und Merkmalskombinationen einer anderen Ausführungsform geeignet zu kombinieren, um zu weiteren erfindungsgemäßen Ausführungsformen zu gelangen.embodiments of the invention are described below with reference to the attached figures, explained in more detail. The However, the invention is not limited to the specific embodiments described limited, but may also be suitably modified and modified become. It is within the scope of the invention, individual features and feature combinations an embodiment with features and feature combinations of another embodiment suitable to combine to further embodiments of the invention reach.
Es zeigen:It demonstrate:
Bevor im Folgenden die Ausführungsbeispiele der vorliegenden Erfindung anhand der Figuren näher erläutert werden, wird darauf hingewiesen, dass gleiche Elemente in den Figuren mit den gleichen oder ähnlichen Bezugszeichen versehen sind und dass eine wiederholte Beschreibung dieser Elemente weggelassen wird.Before in the following the embodiments of the present invention will be explained with reference to the figures, it is noted that same elements in the figures with the same or similar Reference signs are provided and that a repeated description of these elements is omitted.
In
In
dem Halbleiterkörper
Auf
einer Oberfläche
Die
erste Metallschicht
Die
intermetallische Phase ist wichtig für die Ausbildung eines guten
ohmschen Kontaktes. Die erste Metallschicht
Typische Werte für die Legiertemperatur T1 zur Ausbildung des ohmschen Kontakt am Beispiel von Titan und Aluminium auf einem Silizium-Carbid-Halbleiterkörper sind T1 ≈ 900°C bis 1000°C. Zur Ausbildung eines guten ohmschen Kontaktes wird diese Temperatur T1 für ca. 30 sec bis 2 min gehalten.typical Values for the alloying temperature T1 for forming the ohmic contact using the example of Titanium and aluminum are on a silicon carbide semiconductor body T1 ≈ 900 ° C to 1000 ° C. For training a good ohmic contact, this temperature T1 for about 30 Sec held until 2 min.
Um
den Einfluss dieser Legiertemperatur T1 auf die Morphologie der
Kontaktstruktur
Als zweites Metall kann beispielweise ein Wolframsilicidnitrit zum Einsatz kommen. Dieses Metall weist eine hohe thermische Stabilität auf und übersteht somit nachfolgende Temperschritte ohne signifikante Veränderung.When second metal can be used, for example, a tungsten silicide nitrite come. This metal has a high thermal stability and survives thus subsequent tempering steps without significant change.
Dadurch,
dass die zweite Metallschicht
In
einer Alternativen Ausführungsform,
wie in
In
den
Die
zweite Schicht kann aus einem Fotolack hergestellt werden. Die Hinterschneidung
der Maske
Alternativ
kann in einer nicht dargestellten Ausführungsform die erste Metallschicht
Für die erste
Metallschicht
In
Insbesondere
wenn die zweite Metallschicht
Die
zweite Metallschicht
In
einem (nicht dargestellten) weiteren Schritt kann, wie im Beispiel
zur
In
Die
Maske
In nicht dargestellter Weise können noch nachfolgende Prozessschritte bis zur endgültigen Fertigstellung des gewünschten Halbleiterbauelements folgen.In not shown way still subsequent process steps until the final completion of the desired Follow semiconductor device.
Die
in den Ausführungsbeispielen
beschriebene Kontaktstruktur
- 1010
- HalbleiterbauelementSemiconductor device
- 1111
- HalbleiterkörperSemiconductor body
- 1212
- HalbleiterbauelementstrukturenSemiconductor device structures
- 1313
- Elktr. KontaktstrukturElktr. Contact structure
- 1414
- Oberflächesurface
- 1515
- erste Metallschichtfirst metal layer
- 1616
- zweite Metallschichtsecond metal layer
- 1717
- weitere MetallschichtFurther metal layer
- 1818
- Maskemask
- 1919
- Öffnungopening
- 2020
- erste Schichtfirst layer
- 2121
- zweite Schichtsecond layer
Claims (35)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200710029829 DE102007029829A1 (en) | 2007-06-28 | 2007-06-28 | Semiconductor component, has electrical contact structure with two metallic layers, where one of metallic layers is provided on other metallic layer such that latter metallic layer is surrounded by former metallic layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200710029829 DE102007029829A1 (en) | 2007-06-28 | 2007-06-28 | Semiconductor component, has electrical contact structure with two metallic layers, where one of metallic layers is provided on other metallic layer such that latter metallic layer is surrounded by former metallic layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102007029829A1 true DE102007029829A1 (en) | 2009-01-02 |
Family
ID=40075927
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DE200710029829 Ceased DE102007029829A1 (en) | 2007-06-28 | 2007-06-28 | Semiconductor component, has electrical contact structure with two metallic layers, where one of metallic layers is provided on other metallic layer such that latter metallic layer is surrounded by former metallic layer |
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DE (1) | DE102007029829A1 (en) |
Cited By (3)
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---|---|---|---|---|
ITTO20120646A1 (en) * | 2012-07-23 | 2014-01-24 | St Microelectronics Srl | METHOD OF FORMING ELECTRIC CONTACT INTERFACE REGIONS OF AN ELECTRONIC DEVICE |
JP2014086438A (en) * | 2012-10-19 | 2014-05-12 | Toyota Motor Corp | Semiconductor device and semiconductor device manufacturing method |
WO2015078919A1 (en) * | 2013-11-28 | 2015-06-04 | Osram Opto Semiconductors Gmbh | Method for producing optoelectronic components for encapsulating layers |
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---|---|---|---|---|
DE10005368A1 (en) * | 2000-02-07 | 2001-08-16 | Daimler Chrysler Ag | Electrical contact on semiconductor materials comprises binary or ternary metal alloy having melting point which matches process temperature |
US20040016929A1 (en) * | 2001-09-06 | 2004-01-29 | Osamu Nakatsuka | Electrode for p-type sic |
EP1450394A1 (en) * | 2002-07-11 | 2004-08-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
DE10261364B4 (en) * | 2002-12-30 | 2004-12-16 | Osram Opto Semiconductors Gmbh | Process for producing a temperable multi-layer contact coating, in particular a temperable multi-layer contact metallization |
US20050258459A1 (en) * | 2004-05-18 | 2005-11-24 | Kiuchul Hwang | Method for fabricating semiconductor devices having a substrate which includes group III-nitride material |
-
2007
- 2007-06-28 DE DE200710029829 patent/DE102007029829A1/en not_active Ceased
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10005368A1 (en) * | 2000-02-07 | 2001-08-16 | Daimler Chrysler Ag | Electrical contact on semiconductor materials comprises binary or ternary metal alloy having melting point which matches process temperature |
US20040016929A1 (en) * | 2001-09-06 | 2004-01-29 | Osamu Nakatsuka | Electrode for p-type sic |
EP1450394A1 (en) * | 2002-07-11 | 2004-08-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
DE10261364B4 (en) * | 2002-12-30 | 2004-12-16 | Osram Opto Semiconductors Gmbh | Process for producing a temperable multi-layer contact coating, in particular a temperable multi-layer contact metallization |
US20050258459A1 (en) * | 2004-05-18 | 2005-11-24 | Kiuchul Hwang | Method for fabricating semiconductor devices having a substrate which includes group III-nitride material |
Non-Patent Citations (2)
Title |
---|
Merkel, U. [u.a.]: Ohmic behaviour of Au/WSiN/ (Au , Ge, Ni)-n-GaAs systems. In: Thin Solid Films, IS SN 0040-6090, 1992, Vol. 217, S. 108-112 |
Merkel, U. [u.a.]: Ohmic behaviour of Au/WSiN/ (Au, Ge, Ni)-n-GaAs systems. In: Thin Solid Films, ISSN 0040-6090, 1992, Vol.217, S. 108-112; * |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITTO20120646A1 (en) * | 2012-07-23 | 2014-01-24 | St Microelectronics Srl | METHOD OF FORMING ELECTRIC CONTACT INTERFACE REGIONS OF AN ELECTRONIC DEVICE |
US9159611B2 (en) | 2012-07-23 | 2015-10-13 | Stmicroelectronics S.R.L. | Method of forming electric contact interface regions of an electronic device |
JP2014086438A (en) * | 2012-10-19 | 2014-05-12 | Toyota Motor Corp | Semiconductor device and semiconductor device manufacturing method |
WO2014060804A3 (en) * | 2012-10-19 | 2014-06-12 | Toyota Motor Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
CN104885194A (en) * | 2012-10-19 | 2015-09-02 | 丰田自动车株式会社 | Semiconductor device and manufacturing method of semiconductor device |
TWI562369B (en) * | 2012-10-19 | 2016-12-11 | Toyota Motor Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
US9607836B2 (en) | 2012-10-19 | 2017-03-28 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method of semiconductor device |
CN104885194B (en) * | 2012-10-19 | 2017-06-27 | 丰田自动车株式会社 | The manufacture method of semiconductor device and semiconductor device |
WO2015078919A1 (en) * | 2013-11-28 | 2015-06-04 | Osram Opto Semiconductors Gmbh | Method for producing optoelectronic components for encapsulating layers |
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