DE102007002156A1 - Semiconductor arrangement, comprises heat sink body, which is provided for dissipating heat from semiconductor component, where heat sink has electric conductive body with recess for receiving semiconductor component - Google Patents
Semiconductor arrangement, comprises heat sink body, which is provided for dissipating heat from semiconductor component, where heat sink has electric conductive body with recess for receiving semiconductor component Download PDFInfo
- Publication number
- DE102007002156A1 DE102007002156A1 DE102007002156A DE102007002156A DE102007002156A1 DE 102007002156 A1 DE102007002156 A1 DE 102007002156A1 DE 102007002156 A DE102007002156 A DE 102007002156A DE 102007002156 A DE102007002156 A DE 102007002156A DE 102007002156 A1 DE102007002156 A1 DE 102007002156A1
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- heat sink
- semiconductor device
- recess
- semiconductor
- sink body
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Abstract
Description
Die vorliegende Erfindung bezieht sich auf eine Halbleiteranordnung mit Wärmesenke und insbesondere auf eine Leistungs-Halbleiteranordnung mit verbesserter Wärmeabfuhr.The The present invention relates to a semiconductor device with heat sink and in particular to a power semiconductor device with improved heat dissipation.
In der Halbleitertechnik und insbesondere in der Leistungs-Halbleitertechnik werden zunehmend immer dünnerwerdende Halbleiterbausteine bzw. -Chips mit Schichtdicken kleiner 200 μm hergestellt. Ferner besteht zunehmend die Notwendigkeit beidseitig prozessierte Halbleiterbausteine zur Realisierung von Halbleiterbauelementen zu realisieren, die sich durch das gesamte Bausteinsubstrat erstrecken.In Semiconductor technology and in particular in the power semiconductor technology are becoming increasingly thinner semiconductor devices or chips produced with layer thicknesses less than 200 microns. Further There is an increasing need for both sides processed semiconductor devices to realize the realization of semiconductor devices that are extend through the entire device substrate.
Die Wärmeabfuhr von derartigen immer dünner werdenden Halbleiterbausteinen rückt hierbei zusehends in den Vordergrund der Entwicklungsaktivitäten. Einerseits muss hierbei eine Wärmeleitfähigkeit vom Halbleiterbaustein zu einer Wärmesenke bzw. zu einem Kühlkörper verbessert werden. Andererseits müssen die auf Grund einer thermischen Beanspruchung entstehenden mechanischen Spannungen zwischen Halbleiterbaustein und Wärmesenke minimiert werden, um beispielsweise eine unerwünschte Delamination zu vermeiden. Ferner gilt es die letzten Bearbeitungsschritte zu vereinfachen, insbesondere bei sehr dünnen Halbleiterbausteinen oder Halbleiterwafern vor dem Vereinzeln und Löten der Bausteine auf die Wärmesenke bzw. den Kühlkörper beinhaltende Substrate wie beispielsweise Anschlussdrahtrahmen (lead frames). Ferner sollen die elektrischen Anschlussmöglichkeiten einer derartigen Halbleiteranordnung zur Montage auf einer Leiterplatte verbessert werden.The Heat dissipation of such ever thinner Semiconductor devices are increasingly coming to the fore here of development activities. On the one hand, this one must Thermal conductivity of the semiconductor device to a Heat sink or improved to a heat sink become. On the other hand, due to a thermal Stress arising mechanical stresses between semiconductor device and heat sink are minimized, for example, a to avoid unwanted delamination. Furthermore, it applies the simplify last processing steps, especially at very thin semiconductor devices or semiconductor wafers in front of Separating and soldering the blocks to the heat sink or the heat sink-containing substrates such as for example, lead frames. Furthermore, the electrical connection options of such a semiconductor device be improved for mounting on a circuit board.
Insbesondere für beidseitig prozessierte Halbleiterbausteine ist eine derartige Halbleiteranordnung unzureichend. Ferner ist bei starker thermischer Beanspruchung eine erhöhte Delamination zu beobachten und zum Teil kann eine nur unzureichende Wärmeabfuhr realisiert werden.Especially for both sides processed semiconductor devices is a such semiconductor device insufficient. It is also strong thermal stress to observe increased delamination and sometimes only insufficient heat dissipation can be realized become.
Ferner ist eine Verarbeitung von sehr dünnen Wafern wegen deren Verbiegung auf Grund von thermisch verspannender Schichten stark erschwert. Aus diesem Grund sind der Dicke von Vorderseiten-Metallisierungen und -Passivierungen Grenzen gesetzt, da ansonsten die Waferverbiegung bis zu einem zylindrischen Einrollen eskalieren kann. Ferner werden bei immer stärker werdenden Stromdichten insbesondere für Leistungs-Halbleiteranordnungen immer mehr Bonddrähte notwendig, wobei eine Anwendung auf die sogenannte Flip-Chip-Technologie insbesondere auf Grund der beidseitigen Anschlüsse am Halbleiterbaustein nicht möglich sind.Further is a processing of very thin wafers because of them Bending due to thermally stressing layers strong difficult. For this reason, the thickness of front side metallizations and passivations limits, otherwise the wafer bending can escalate to a cylindrical curl. Further, at ever-increasing current densities especially for Power semiconductor devices more and more bonding wires necessary being an application to the so-called flip-chip technology in particular due to the two-sided connections on the semiconductor device are not possible.
Es besteht daher ein Bedürfnis eine Halbleiteranordnung mit Wärmesenke zu schaffen, welche verbesserte Eigenschaften hinsichtlich einer Wärmeabfuhr, einer Delamination und einer Verarbeitbarkeit von sehr dünnen Halbleiterbaustein-Substraten ermöglicht.It There is therefore a need for a semiconductor device Heat sink to create what improved properties with regard to heat dissipation, delamination and a processability of very thin semiconductor device substrates allows.
Erfindungsgemäß wird eine Halbleiteranordnung mit Wärmesenke zum Abführen von Wärme aus einem Halbleiterbaustein geschaffen, wobei die Wärmesenke einen elektrisch leitfähigen Körper mit einer Aussparung zum Aufnehmen des Halbleiterbausteins aufweist.According to the invention a semiconductor device with heat sink for discharging created by heat from a semiconductor device, wherein the heat sink an electrically conductive body having a recess for receiving the semiconductor device.
Nachfolgend werden Ausführungsbeispiele der Erfindung unter Bezugnahme auf die Zeichnung näher beschrieben.following Be embodiments of the invention with reference described in detail on the drawing.
Es zeigen:It demonstrate:
Gemäß der vorliegenden Erfindung kann die Wärmesenke aus einem elektrisch leitfähigen Körper bestehen, der eine Aussparung zum Aufnehmen des Halbleiterbausteins aufweist. Insbesondere bei Verarbeitung von sehr dünnen Halbleiterbausteinen ist somit eine Passivierung erst nach dem Einbringen in den Wärmesenken-Körper möglich, wodurch sich verbesserte Wärmeleitfähigkeiten ergeben. Ferner wird dadurch die Realisierung von Flip-Chip-Bauelementen ermöglicht.According to the present invention, the heat sink may consist of an electrically conductive body having a recess for receiving the Semiconductor devices has. In particular, when processing very thin semiconductor devices, a passivation is possible only after the introduction into the heat sink body, resulting in improved Wärmeleitfähigkeiten. Furthermore, this enables the realization of flip-chip components.
Die Form der Aussparung ist beispielsweise an die Form des Halbleiterbausteins angepasst, wodurch sich eine weiter verbesserte Wärmeabfuhr und eine weiter verringerte Delaminierung ergibt.The Shape of the recess is, for example, to the shape of the semiconductor device adjusted, resulting in a further improved heat dissipation and gives a further reduced delamination.
Beispielsweise kann zumindest zwischen den Seitenwänden der Aussparung und den Seitenwänden des Halbleiterbausteins eine erste Isolierschicht ausgebildet sein, wodurch sich eine weitergehende mechanische Stabilisierung und eine oftmals notwendige Seitenwand-Passivierung von Halbleiterbausteinen effektiv realisieren lässt. Weiterhin ist dadurch eine Delaminierung auch bei sehr hohen thermischen Beanspruchungen stark verringert.For example can be at least between the side walls of the recess and the sidewalls of the semiconductor device a first Insulating be formed, resulting in a more extensive mechanical stabilization and often necessary sidewall passivation of semiconductor devices can be effectively realized. Farther This is a delamination even at very high thermal stresses greatly reduced.
Beispielsweise kann eine Vorderseite des Halbleiterbausteins um eine Höhe von 20 bis 100 μm über eine Vorderseite des Wärmesenken-Körpers hinausragen, wodurch sich insbesondere bei einer galvanischen Ausbildung von Anschluss-Lötballen oder Anschluss-Feldern ein geeigneter Höhenausgleich zwischen den Lötballen bzw. -Feldern auf dem Halbleiterbaustein und den entsprechenden Lötballen und -Feldern auf dem Wärmesenken-Körper erreichen lässt.For example may be a front of the semiconductor device around a height from 20 to 100 microns across a front of the heat sink body protrude, resulting in particular in a galvanic training of terminal solder bales or terminal boxes a suitable Height compensation between the solder balls or fields on the semiconductor device and the corresponding solder balls and fields on the heat sink body.
Beispielsweise besteht der Wärmesenken-Körper aus Cu oder aus einem Verbundwerkstoff mit Kohlenstoffteilchen und Cu, wodurch man eine gute Anpassung an den thermischen Ausdehnungskoeffizienten des Halbleitersubstrats insbesondere bei Silizium-Substraten erhält.For example The heat sink body consists of Cu or out a composite with carbon particles and Cu, whereby one a good adaptation to the thermal expansion coefficient of the semiconductor substrate, in particular in the case of silicon substrates.
Beispielsweise kann ein Anschluss-Lötballen auf einer Vorderseite des Halbleiterbausteins und zumindest ein weiterer Anschluss-Lötballen auf einer Vorderseite des Wärmesenken-Körpers ausgebildet sein. Hierbei besteht weder die Notwendigkeit der Verwendung eines Draht-Bondens noch einer Pressmasse zur Realisierung eines Gehäuses, wodurch sich die Kosten wesentlich reduzieren lassen. Ferner können auch für Halbleiterbausteine mit sehr kleinen Abmessungen Flip-Chiptaugliche Bauelemente realisiert werden.For example can be a connecting solder ball on a front of the Semiconductor devices and at least one additional connection pads on a front side of the heat sink body be educated. There is neither the need for use a wire bonding still a molding compound to realize a Housing, which significantly reduces costs to let. Furthermore, it is also possible for semiconductor components realized with very small dimensions flip chip-compatible components become.
Beispielsweise kann die erste Isolierschicht ferner zumindest auf einem Teilabschnitt der Vorderseite des Wärmesenken-Körpers, darauf eine Baustein-Anschlussschicht zum Anschließen des Halbleiterbausteins und darauf ein weiterer Anschluss-Lötballen oder ein weiteres Anschluss-Feld an der Vorderseite des Wärmesenken-Körpers neben der Aussparung ausgebildet sein, wodurch nicht nur eine einfache Vorderseiten- und Rückseitenkontaktierung, sondern darüber hinaus komplexere Kontaktierungsmöglichkeiten des Halbleiterbausteins effektiv gelöst werden können.For example the first insulating layer may further at least on a portion the front of the heat sink body, on top a device connection layer for connecting the semiconductor device and then another connecting soldering ball or another Connection field on the front of the heat sink body be formed next to the recess, which is not only a simple Front and back contact, but above it In addition, more complex contacting possibilities of the semiconductor device can be effectively solved.
Im Folgenden werden Ausführungsbeispiele der Erfindung anhand von Figuren dargestellt, die lediglich der Illustration dienen und den Umfang der Erfindung nicht beschränken.in the Below, embodiments of the invention are based on represented by figures, which serve only for illustration and not limit the scope of the invention.
Beispielsweise
kann der Wärmesenken-Körper
Gemäß
Ferner
kann nicht nur eine hervorragende elektrische Leitfähigkeit
sowie Wärmeleitfähigkeit realisiert werden, sondern
wegen der Aussparung darüber hinaus eine sehr stabile mechanische
Verbindung zu einer (nicht dargestellten) Passivierung aus Photoimid
geschaffen werden, die somit gegenüber einer Delamination
auf Grund thermischer Beanspruchung unempfindlich ist. Bei Verwendung
von Silizium für das Substrat der Halbleiterbausteine
Gemäß
Damit sind bereits die Voraussetzungen gegeben, selbstjustierende galvanische Anschluss-Lötballen oder Anschluss-Felder zu erzeugen, ohne auf Keimschichten und Fotolithographie zurückgreifen zu müssen.In order to are already given the prerequisites, self-aligning galvanic Create connecting solder bales or connection fields without resorting to seed layers and photolithography to have to.
Alternativ
zum vorstehend beschriebenen gesinterten Wärmesenken-Körper
bzw. -Wafer kann dieser auch galvanisch hergestellt werden. Hierbei werden
die beispielsweise bereits vereinzelten oder noch unvereinzelten
Halbleiterbausteine
Letztendlich
entsteht auch hierbei der gleiche Wärmesenken-Körper
Während
beim gesinterten Wärmesenken-Körper
Gemäß
Ferner
kann zur Realisierung eines Source-Kontaktes eine dünne
Metallisierungsschicht
Wie
bereits vorstehend beschrieben wurde, kann ein derartiger sehr dünner
Halbleiterbaustein
In
gleicher Weise können jedoch auch sehr dünne Lötplättchen
zur Realisierung der dargestellten Lötschicht
Beispielsweise
kann eine Vorderseite des Halbleiterbausteins
Anschließend
kann mit herkömmlichem Wafer-Equipment eine erste Isolierschicht
bzw. Passivierung
Auf
diese Weise erhält man nicht nur eine hervorragende Seitenwand-Passivierung
für den Halbleiterbaustein
Hinsichtlich
eines nicht dargestellten Gate-Anschluss-Lötballens oberhalb
der Steuerschicht
Eine üblicherweise
(auf Grund der pn-Diode D) zu beobachtende ungleichmäßige
Aufwachsrate für den Source-Anschluss-Lötballen
Obwohl
in
Bevor
die Halbleiterbausteine
Bei der nicht dargestellten alternativen Ausgestaltung, bei der der Halbleiterwafer für die Herstellung der Leistungs-Halbleiterbauelemente bereits vor oder nach dem Dünnen mit Trenngräben ausgestattet wird und auf den Wafer mit den Trenngräben dann eine Verbundwerkstoff-Füllgalvanik mit beispielsweise Kupfer und Kohlenstoffteilchen direkt aufgebracht wird, können die Zwischenräume zwischen den Halbleiterbausteinen und dem Wärmesenke-Verbundwerkstoff galvanisch, mit geeigneten Metallen wie beispielsweise Nickel und Kupfer anschließend verfüllt werden. Bei dieser alternativen Variante ergibt sich der Vorteil, dass während des gesamten Produktionsablaufes zu keinem Zeitpunkt ein gedünnter und somit bruchgefährdeter Wafer vorliegt.at the alternative embodiment, not shown, in which the Semiconductor wafer for the production of power semiconductor devices already before or after thinning with separating trenches is equipped and on the wafer with the dividers then a composite filling electroplating with, for example Copper and carbon particles can be applied directly the spaces between the semiconductor devices and the heat sink composite galvanically, with suitable Metals such as nickel and copper subsequently be filled. This alternative variant results the advantage that throughout the production process at no time a thinned and thus vulnerable to breakage Wafer is present.
Auf diese Weise erhält man eine Halbleiteranordnung, die eine stark verbesserte Wärmeabfuhr zu einem Wärmesenken-Körper aufweist. Ferner besteht die Möglichkeit auch beidseitig prozessierte Halbleiterbausteine mittels Flip-Chip-Technologie zu verarbeiten, wobei ferner die Gefahr einer Delamination stark verringert und die mechanischen Eigenschaften stark verbessert sind. Die Verarbeitung von ultradünnen Halbleiterbausteinen wird auf diese Weise wirtschaftlich möglich.On in this way, one obtains a semiconductor device having a greatly improved heat dissipation to a heat sink body having. Furthermore, there is also the possibility of both sides process processed semiconductor devices using flip-chip technology, Furthermore, the risk of delamination greatly reduced and the mechanical properties are greatly improved. The processing of ultra-thin semiconductor devices is going this way economically possible.
Gemäß
Der
Wärmesenken-Körper
Gemäß
Gemäß
Durch
das Herausführen von Halbleiterbausteinkontakten, wie beispielsweise
dem Source-Kontakt auf eine größere und somit
bondbare Fläche neben dem Halbleiterbaustein
Nach
dem Sägen bzw. Vereinzeln der Wärmesenken-Körper
Gemäß
Im
Gegensatz zur
Genauer
gesagt kann in ähnlicher Weise wie bei den vorstehend genannten
Ausführungsbeispielen nach dem Verlöten des Halbleiterbausteins
Gemäß
Ferner
dient eine erste Metallisierungsschicht, die an der Oberfläche
der ersten Isolierschicht
Auf
Grund einer geeigneten Strukturierung der ersten Isolierschicht
Auf
diese Weise erhält man wiederum eine Halbleiteranordnung
mit Wärmesenke, die ohne zusätzliches Drahtbonden
oder einer zusätzlichen Pressmasse für ein Gehäuse
ein unmittelbar für eine Flip-Chip-Technologie verwendbares
Modul bereitstellt. Dieses Modul mit den Lötballen
Gemäß
Beispielsweise
besitzen gemäß
Die
Erfindung wurde vorstehend anhand eines Leistungs-Halbleiterbauelements
mit galvanisch ausgebildeten Lötballen bzw. -Pads beschrieben.
Sie ist jedoch nicht darauf beschränkt und umfasst in gleicher
Weise auch alternative Halbleiterbauelemente mit alternativ realisierten
Lötballen bzw. -Pads. Ferner wurde die Erfindung dahingehend
beschrieben, dass das Löten der Halbleiterbausteine sowie
das galvanische Ausbilden der Lötballen bzw. Kontakt-Pads
und die Erzeugung einer abschließenden Passivierung auf
Waferebene durchgeführt wird. Die Erfindung ist jedoch
nicht darauf beschränkt und kann in gleicher Weise auch
für bereits vereinzelte Halbleiterbau steine an bereits
vereinzelten Wärmesenken-Körpern
- 11
- HalbleiterbausteinSemiconductor device
- 22
- Wärmesenken-KörperHeat sink body
- 33
- Aussparungrecess
- 44
- n-Substratn-substrate
- 55
- p-Bodyp-body
- 66
- FeldisolationsschichtField insulating layer
- 77
- Gatedielektrikumgate dielectric
- 8A8A
- Source-AnschlussschichtSource terminal layer
- 8B8B
- Gate-AnschlussschichtGate layer
- 99
- Lötschichtsolder layer
- 1010
- erste Isolierschichtfirst insulating
- 1111
- Source-Anschluss-LötballenSource Connection Lötballen
- 1212
- Drain-Anschluss-LötballenDrain-Lötballen
- 1313
- Gate-Anschluss-LötballenGate-Lötballen
- 1414
- weitere LötschichtFurther solder layer
- 15, 17A, 17B, 17C15 17A, 17B, 17C
- Baustein-AnschlussschichtenBlock connection layers
- 16, 1816 18
- zweite Isolierschichtsecond insulating
- 17D17D
- Kontaktschichtcontact layer
- 1919
- Leiterplattecircuit board
- 2020
- Leitbahnenmeridians
- 3030
- Trägerplattesupport plate
- 4040
- BonddrähteBond wires
- 5050
- Anschlussdrähteleads
- 6060
- isolierende Verbindungsschichtinsulating link layer
- 7070
- Gehäusecasing
- WSWS
- Wärmesenkeheat sink
- SPSP
- Source-PadSource pad
- DPDP
- Drain-PadDrain pad
- SBSB
- Sägebereichcutting area
- RBRB
- Randbereichborder area
- DD
- Diodediode
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - EP 0488783 A2 [0004] EP 0488783 A2 [0004]
Claims (22)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007002156A DE102007002156A1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor arrangement, comprises heat sink body, which is provided for dissipating heat from semiconductor component, where heat sink has electric conductive body with recess for receiving semiconductor component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007002156A DE102007002156A1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor arrangement, comprises heat sink body, which is provided for dissipating heat from semiconductor component, where heat sink has electric conductive body with recess for receiving semiconductor component |
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Publication Number | Publication Date |
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DE102007002156A1 true DE102007002156A1 (en) | 2008-07-17 |
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DE102007002156A Ceased DE102007002156A1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor arrangement, comprises heat sink body, which is provided for dissipating heat from semiconductor component, where heat sink has electric conductive body with recess for receiving semiconductor component |
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WO2009060219A3 (en) * | 2007-11-08 | 2009-08-06 | Photonstar Led Ltd | Ultra high thermal performance packaging for optoelectronics devices |
WO2010138983A1 (en) * | 2009-06-02 | 2010-12-09 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for contacting an electronic component and a heat-conducting element and for producing a printed circuit board |
US8736062B2 (en) | 2012-08-16 | 2014-05-27 | Infineon Technologies Ag | Pad sidewall spacers and method of making pad sidewall spacers |
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EP0488783A2 (en) | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
EP0684645A2 (en) * | 1994-05-26 | 1995-11-29 | Analog Devices, Incorporated | EMF shielding of an integrated circuit package |
US5583377A (en) * | 1992-07-15 | 1996-12-10 | Motorola, Inc. | Pad array semiconductor device having a heat sink with die receiving cavity |
US20020187590A1 (en) * | 2000-08-31 | 2002-12-12 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
US6709898B1 (en) * | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
US20050250250A1 (en) * | 2002-10-11 | 2005-11-10 | Chien-Min Sung | Diamond composite heat spreader having thermal conductivity gradients and associated methods |
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2007
- 2007-01-15 DE DE102007002156A patent/DE102007002156A1/en not_active Ceased
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EP0488783A2 (en) | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
US5583377A (en) * | 1992-07-15 | 1996-12-10 | Motorola, Inc. | Pad array semiconductor device having a heat sink with die receiving cavity |
EP0684645A2 (en) * | 1994-05-26 | 1995-11-29 | Analog Devices, Incorporated | EMF shielding of an integrated circuit package |
US20020187590A1 (en) * | 2000-08-31 | 2002-12-12 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
US6709898B1 (en) * | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
US20050250250A1 (en) * | 2002-10-11 | 2005-11-10 | Chien-Min Sung | Diamond composite heat spreader having thermal conductivity gradients and associated methods |
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WO2009060219A3 (en) * | 2007-11-08 | 2009-08-06 | Photonstar Led Ltd | Ultra high thermal performance packaging for optoelectronics devices |
US8324633B2 (en) | 2007-11-08 | 2012-12-04 | Photonstar Led Limited | Ultra high thermal performance packaging for optoelectronics devices |
WO2010138983A1 (en) * | 2009-06-02 | 2010-12-09 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for contacting an electronic component and a heat-conducting element and for producing a printed circuit board |
US8736062B2 (en) | 2012-08-16 | 2014-05-27 | Infineon Technologies Ag | Pad sidewall spacers and method of making pad sidewall spacers |
DE102013108268B4 (en) | 2012-08-16 | 2022-12-29 | Infineon Technologies Ag | Pad-sidewall spacers and method of making pad-sidewall spacers |
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