DE102007001859B3 - Integrated circuit e.g. dynamic RAM, for use in electronic device, has resistive memory cell, and p-channel transistor that produces predetermined reading voltage for smaller resistance range which has reference conditions of reference cell - Google Patents

Abstract

The circuit (200) has a resistive memory cell (210), which is switched between high and low impedance memory states, and a reference cell (220) with a resistance value, which reproduces a reference condition. A p-channel transistor (50) and a remote voltage regulator unit (60) apply predetermined reading voltages to the cells (220, 210), respectively. The unit (60) produces the voltage for a resistance range, which has the memory states of the cell (210). The transistor produces the voltage for a smaller resistance range, which has the reference conditions of the reference cell. An independent claim is also included for a method for determining a memory state of a resistive memory cell.

Description

The The present invention relates to an integrated circuit having a Resistive memory cell, which is switchable between a high-impedance memory state and at least one low-resistance memory state, and a method for determining a storage state of a resistive memory cell. The invention further relates to a memory module having a plurality of resistive memory cells, as well as an electronic device having such a memory chip.

In different data processing systems and electronic Devices are used so-called non-volatile memory devices. These memories have programmable memory cells in which a stored information reliably obtained even without external power supply remains. This occurs in contrast to so-called volatile Save as DRAM (Dynamic Random Access Memory) no loss of memory content immediately after shutdown the supply voltage of the memory.

One Type of non-volatile Memory is the so-called flash memory. In this storage type For example, a single memory cell consists of a FET transistor (Field Effect Transistor), which is an isolated called "floating gate" Auxiliary electrode between the gate and the source-drain path (channel) of the transistor. To program the flash memory cell a high positive potential is applied to the gate, whereby an electric charge (electrons) is applied to the auxiliary electrode becomes. The uncharged state of the flash memory cell is restored achieved by applying the charge on the auxiliary electrode a high nega tive potential to the gate of the auxiliary electrode is expelled. The charge on the auxiliary electrode is there the conductivity or the resistance of the source-drain path at the transistor turned on at the gate before, which determines a storage state of the flash memory cell is being used.

Furthermore are non-volatile Resistive memory known, which is based on the exploitation of additional electrical Properties and phenomena based. This falls in particular the CBRAM memory (Conductive Bridging RAM), in which a memory cell a resistance memory element with an intermediate two electrodes arranged electrolyte material with a high has specific resistance. By applying a programming voltage to the electrodes may be a conductive path in the electrolyte material be built, making the resistive memory cell of a high resistance state passes into a low resistance state. The change from the high-impedance memory state to the low-impedance one Memory state can by applying a corresponding erase voltage Undone become. The different resistances define detectable ones storage conditions the memory cell.

One Another resistive memory is the so-called phase change memory, also referred to as PCRAM (Phase Change RAM). This has a memory cell a resistive storage element with one between two electrodes arranged phase change material, usually a metal alloy, on. By means of electrical pulses, the phase change material can be heated and thus between one (originally) amorphous and a crystalline phase state switched back and forth become. Dependent on of the phase state, the resistive memory cell becomes one high-impedance memory state (amorphous phase) and in a low-impedance Memory state (crystalline phase) offset, resulting in information storage is being used.

To the Reading out information from a memory cell of a CBRAM and a PCRAM memory device may have a predetermined read voltage be applied to the memory cell by means of a readout circuit, to cause an electric current flow through the memory cell. The strenght of the electric current is dependent on the resistance state the resistive memory cell. By detecting one of the current dependent electrical measurement, usually a voltage drop across one in series with the memory cell Load element, therefore, the memory state of the memory cell can be determined. For this purpose, the electrical measured variable is compared with a reference variable. The reference size usually becomes dependent on an electric current obtained by applying the predetermined Read voltage to two parallel and serving as a reference Resistive memory cells is caused. One of these reference cells is in a high-resistance state, whereas the other reference cell is in a low resistance state is located so that the parallel-connected reference cells a Reference state on two load elements connected in parallel with a resistance value between the high-resistance and the low-resistance Play memory state.

Since the resistance states of a resistive memory cell of a CBRAM and a PCRAM memory differ by several orders of magnitude, depending on the voltage source used, considerable deviations between the actual voltage applied to the memory cell and the desired reading can occur result in voltage. However, a reliable evaluation of the memory state of the resistive memory cell requires the application of a constant and reproducible read voltage to the memory cell. Thus, in particular, a small resistance of the memory cell can result in a voltage applied to the memory cell breaking in, as a result of which no current flow required for the evaluation is no longer possible. In order to prevent such impairments, the voltage applied to the resistive memory cell and the reference cells in the case of CBRAM or PCRAM memory modules is regulated to the predefined read voltage by means of voltage regulating units. In this case, a voltage regulating unit usually has a feedback operational amplifier and a regulating transistor connected to an output of the operational amplifier, which involves a certain amount of circuitry.

The US 6,597,598 B1 discloses a memory device with resistive memory cells. A read voltage, which is applied to a memory cell and a reference cell for reading out a memory state, is hereby generated by means of voltage regulation units.

Instead of a memory cell of a memory module as a binary coded Insert memory cell for storing a bit and the memory cell only between two different resistance states (logic "0", logical "1") back and forth switch, it is possible to a memory cell as a so-called multilevel cell (MLC, Multi Level Cell) for storing multiple bits by using a larger number at memory states to operate. For example, are for storing 2-bit information four distinguishable resistance states of a memory cell required.

A Multilevel operation of memory cells is in flash memory known. For determining a storage state of a flash memory cell In this case, a given read voltage is applied to the flash memory cell or at their source-drain path created as well as an electrical parameter depending on a thereby caused recorded electric current. The electrical parameter is with reference variables of a electric current compared, which by applying the predetermined Reading voltage is caused to reference cells. The reference cells have reference states with resistance values between the individual memory states of the to be read flash memory cell. For example, at a 2-bit mode, three reference cells each with different reference conditions used to determine in which of four possible memory states the flash memory cell is located. Setting the default Read voltage at the flash memory cell to be evaluated and at the reference cells This is done using transistors, which as source follower operate.

Also with a CBRAM and a PCRAM memory module is the possibility given a multilevel operation, as a resistive memory cell between a high-impedance memory state and multiple low-impedance memory states can be switched back and forth. To evaluate the memory state a resistive memory cell may be known from flash memories However, readout concept should not be applied because the resistance states of resistive memory cells unlike flash memory cells lie in a resistance region which as described above several orders of magnitude includes. Specifying the read voltage using as the source follower switched transistors Therefore, a drop in the reading voltage in low-resistance memory conditions for Consequence, whereby a rating is impaired or not is possible. Although could such an impairment using the voltage stabilization or regulation described above be compensated. The provision of voltage regulation units both for memory cells as well as for Would have reference cells However, a relatively high circuit complexity and thus a relative high space requirement of a memory module with a multilevel mode of operation for Episode.

From the US 5,828,616 For example, a flash memory is known in which the flash memory cells are operated as multilevel cells for storing, for example, 2-bit information. A read voltage applied to a memory cell to be read and associated reference cells is thereby generated by means of voltage regulation units.

The Object of the present invention is an improved solution for applying a read voltage for an integrated circuit, a memory chip and a elec tronic Specify device with resistive memory cells. It is further Object of the invention, an improved method for determining to provide a memory state of a resistive memory cell.

These Task is achieved by an integrated circuit according to claim 1, a memory module according to claim 9, an electronic device according to claim 23 and a method according to claim 24 solved. Further advantageous embodiments The invention are set forth in the dependent claims.

According to a first aspect of the present invention, an integrated circuit is proposed which comprises a resistive memory cell and has at least one reference cell. The resistive memory cell is switchable between a high-impedance memory state and at least one low-resistance memory state. The reference cell has a resistance value representing a reference state. The integrated circuit further comprises a first means for applying a predetermined read voltage to the resistive memory cell. The first device is designed to generate the read voltage for a first resistance region, which comprises the memory states of the resistive memory cell. The integrated circuit further comprises a second means for applying the predetermined read voltage to the reference cell. The second device is designed to generate the read voltage for a second resistance region, which is smaller than the first resistance region, and which comprises the reference state of the reference cell.

According to one second aspect of the present invention is a memory device proposed, which a plurality of word lines and bit lines and a plurality of resistive memory cells and reference cells having. A resistive memory cell is at a cross point a word line and a bit line arranged and is switchable between a high-resistance memory state and at least one low-resistance memory state. A reference cell is at a crossing point a word line and a bit line arranged and has a Resistance value, which represents a reference state. The memory chip has a first means for applying a predetermined reading voltage to a resistive memory cell for elicatory electrical Current in a bit line associated with the resistive memory cell on. The first device is designed to read the voltage for a generate first resistance region, which the memory states of the resistive memory cell. The memory module has the further a second means for applying the predetermined reading voltage to a reference cell for generating an electric current in a bit line associated with the reference cell. The second Device is designed to read the voltage for a relative to the first resistance range smaller second resistance range too generate, which includes the reference state of the reference cell. The memory module also has an evaluation device, to determine the memory state of a resistive memory cell.

According to one third aspect of the present invention is an electronic Device with such a memory module described above proposed.

by virtue of the fact that the second institution unlike the first device is formed, the read voltage to a reference cell for one To generate resistance range, which only the resistance value the reference cell and not the entire resistance range of a resistive memory cell, the second device may be compared to the realized first device with a lower circuit complexity become. As a result, the integrated circuit has the memory chip and the electronic device on a small footprint.

According to one Fourth aspect of the present invention is a method for Determining a memory state of a resistive memory cell proposed, wherein the resistive memory cell is switchable between a high-impedance memory state and at least one low-resistance memory state. A given read voltage is applied to the resistive memory cell created. The read voltage is here for ei nen first resistance range which generates the memory states of the resistive memory cell includes. An electrical parameter is dependent on one caused by the read voltage across the resistive memory cell recorded electric current. The given reading voltage will be the further applied to a reference cell, wherein the reference cell has a resistance value representing a reference state. The reading voltage is here for one opposite the first resistance region smaller second resistance region generated, which includes the reference state of the reference cell. An electrical reference will be dependent on one caused by the read voltage at the reference cell recorded electric current. The memory state of the resistive Memory cell is based on a comparison of the measured variable with the Reference size determined.

The inventive method allows a reliable one Determining the memory state of the resistive memory cell, since the read voltage at the memory cell for all memory states of Memory cell comprehensive resistance range is generated. Thereby, that the reading voltage at the reference cell, however, for a Resistance region is generated, which only the reference state includes the reference cell, the method requires a small Circuitry.

According to a preferred embodiment of the invention, the first device has a voltage regulation unit, by means of which a voltage applied to the resistive memory cell voltage is regulated to the predetermined read voltage. In the event that the resistive memory cell is in a low-resistance memory state, the memory cell may cause a voltage drop, the voltage regulation unit compensated by raising the voltage to the predetermined reading voltage.

Preferably the voltage regulation unit has a feedback operational amplifier and a with the operational amplifier connected control transistor on.

According to one another preferred embodiment The invention is a small footprint or circuit complexity in a memory module thereby favors that the voltage regulation unit switchable to the bit lines is connected. In such an embodiment a memory module can only one voltage regulation unit for all have resistive memory cells.

According to one another preferred embodiment The invention features the second device as a source follower operated transistor for adjusting the read voltage to the reference cell. That way the second device with a low circuit complexity realize.

The advantageous effects of the invention are particularly in such embodiments achieved in which memory cells as multilevel cells for storage be operated by more than 1 bit. This can be considered, for example a multilevel operation for storing 2-bit information. The Resistive memory cell is therefore preferably switchable between a high-impedance memory state and three low-impedance memory states.

Around the memory state of such a resistive memory cell reliably determine, the memory cell are preferably three reference cells assigned. The three reference cells have three different ones Resistance values for reproducing reference states between the individual memory states of the resistive memory cell. The second resistance area The second device here comprises the three different reference states.

According to one another preferred embodiment According to the invention, three electrical reference quantities are each dependent one caused by the read voltage at the three reference cells recorded electric current. The memory state of the resistive Memory cell is based on a comparison of the resistive memory cell associated electrical measurement with the three reference sizes determined.

According to one another preferred embodiment According to the invention, a resistive memory cell has a resistance memory element and a selection transistor. In the resistance memory element it may be a CBRAM or PCRAM resistor storage element act.

The The invention will be explained in more detail below with reference to the attached figures. It It should be understood, however, that the appended drawings illustrate only typical embodiments of the present invention and therefore the scope of the invention do not restrict. The invention may include other equally effective embodiments. Show it:

1 a schematic representation of a conventional integrated circuit for reading a operated as a multilevel cell flash memory cell;

2 a schematic representation of an integrated circuit for reading a multilevel cell operated resistive memory cell according to an embodiment of the present invention;

3 a schematic representation of an integrated circuit for reading a multilevel cell operated resistive memory cell according to another embodiment of the present invention;

4 a schematic representation of an electronic device with a memory module according to an embodiment of the present invention; and

5 a schematic representation of an electronic device with a memory module according to another embodiment of the present invention.

1 shows a schematic representation of a conventional integrated circuit 100 for reading a flash memory cell 110 , which is operated as a multilevel cell for storing 2-bit information. The memory cell designed as a memory transistor 110 In this case, it can be put into one of four memory states with different resistance values of the source-drain path, which is determined by means of the circuit 100 can be evaluated. For this purpose, the memory cell 110 three reference cells 120 assigned, which reference states with resistance values between the individual memory states of the memory cell 110 exhibit. Also with the reference cells 120 is it like in 1 represented by flash memory cells, which are offset in the corresponding different reference states.

The circuit 100 has a wordline 20 on, which with the control terminals or gates of the memory cell 110 and the reference cells 120 connected is. By applying an activation potential to the word line 20 can the memory cell 110 and the reference cells 120 be activated for a rating.

A first terminal (source / drain) of the memory cell 110 and the reference cells 120 is each with a high potential 12 , For example, connected to a supply voltage. A second connection (source / drain) of the memory cell 110 and the reference cells 120 is each to a bit line 21 connected. A bit line 21 is each connected to a first terminal (source / drain) of a p-channel transistor 50 connected.

The transistors 50 , which are operated as a source follower, are with their gates to a control line 25 connected, and in each case via a second connection (source / drain) to a first terminal of a load element 30 connected. The load elements 30 are presently connected as a diode connected n-channel transistors, which in each case via a second terminal with a ground potential 10 are connected.

In addition, the circuit points 100 three readout amplifiers 40 on. About the readout amplifiers 40 each becomes a potential at a node 31 or at the first terminal of the diode 30 the conduction path of the memory cell 110 and at a node 31 or at the first terminal of a diode 30 the conduction path of a reference cell 120 sampled. The readout amplifiers 40 are for this purpose via appropriate lines with the nodes 31 or the first terminals of the diodes 30 connected.

In operation of the circuit 100 becomes the wordline 20 activated by applying an activation potential to the memory cell 110 and the reference cells 120 to unlock for a rating. Also, the transistors are 50 by applying a control potential to the control line 25 connected through.

In this way, in each case to the first terminal (source / drain) of the transistors 50 or to a node 51 a predetermined potential to a bit line 21 created, causing the memory cell 110 and the reference cells 120 in each case a predetermined reading voltage is set. This has the consequence that in the conduction paths of the memory cell 110 and the reference cells 120 one electric current each from the high potential 12 to the ground potential 10 flows.

The strength of the current is in each case dependent on the resistance state of the memory cell 110 and the reference cells 120 , and therefore each gives a voltage drop across the diodes 30 ago, which by means of a readout amplifier 40 by picking up a potential at a node 31 can be sampled.

The potential at the node 31 the conduction path of the memory cell 110 can therefore use the readout amplifiers 40 with the potentials at the nodes 31 the conduction paths of the reference cells 120 are compared to the memory state of the memory cell 110 to determine. This amplify the readout amplifiers 40 each one difference between that at the node 31 the conduction path of the memory cell 110 and at a node 31 a conduction path of a reference cell 120 applied potential. On the basis of the increased potential differences, the memory state of the memory cell 110 be determined.

Even with a resistive memory cell such as a CBRAM and a PCRAM memory cell, it is possible to operate the memory cell as a multilevel cell. In this case, use is made of the fact that the resistive memory cell can be switched back and forth between a high-impedance memory state and a plurality of low-resistance memory states. In such a resistive memory cell, the in 1 illustrated integrated circuit 100 however, are not used for evaluating a memory state, since the resistance states of the memory cell, unlike a flash memory cell, are in a resistance range that includes several orders of magnitude. The use of a transistor operated as a source follower for setting a read voltage to the resistive memory cell would result in a low-resistance memory state that the memory cell causes a voltage drop and consequently no current flow is possible. In the embodiments of the present invention illustrated in the following figures, such an impairment is avoided with relatively little circuit complexity by providing different means for applying the read voltage to resistive memory cells to be evaluated and to reference cells.

2 shows a schematic representation of an integrated circuit 200 for reading out a resistive memory cell operated as a multilevel cell 210 according to an embodiment of the invention. The memory cell 210 has a resistance memory element 211 and a selection transistor 212 on. The resistance of the resistive memory element 211 gives the memory state of the memory cell 210 in front.

For example, the memory cell 210 a CBRAM memory cell in which the Widerstandsspei storage element 211 two electrodes and a high resistivity electrolyte material disposed between the electrodes (not shown). The memory cell 210 is therefore in a high-impedance memory state, provided that the resistance memory element 211 is not programmed. By applying voltages to the electrodes using in 2 not shown circuit elements, a conductive path can be formed or re-formed in the electrolyte material. Depending on the degree of formation of the conductive path in the electrolyte material of the resistive memory element 211 indicates the memory cell 210 one of several low-impedance memory states.

In the 2 illustrated memory cell 210 For example, one of four possible memory states is used to store 2-bit information, ie the memory cell 210 It is possible to switch between the high-impedance memory state and three low-resistance memory states. For example, the high-resistance memory state corresponds to the memory cell 210 an effective electrical resistance of 1 GΩ, while the low-resistance memory states of the memory cell 210 Resistance values in the kΩ range, ie, for example, 10 kΩ, 30 kΩ and 50 kΩ, respectively.

An evaluation of the memory state of the memory cell 210 is using three of the memory cell 210 associated reference cells 220 which has different resistance values for reproducing reference states between the individual memory states of the memory cell 210 exhibit. All reference states can be compared to the high-resistance memory state of the memory cell 210 low-resistance, relatively small resistance range, ie two-digit kΩ range, and correspond to effective electrical resistances of, for example, 20 kΩ, 40 kΩ and 80 kΩ.

The reference cells 220 are like in 2 illustrated resistive memory cells each having a resistive memory element 211 and a selection transistor 212 , which are connected in the corresponding different reference states. In this way, a high reliability of the evaluation of the memory state of the memory cell becomes 210 achieved because in a manufacturing process of the memory cell 210 occurring and the electrical properties of the memory cell 210 influencing process deviations in a corresponding manner in the preparation of the reference cells 220 available.

Both at the memory cell 210 as well as the reference cells 220 is a first terminal of the resistive memory element 211 with a high potential 12 and a second terminal of the resistive memory element 211 with a first source / drain terminal of the selection transistor 212 connected. The potential 12 is also called plate potential. A second source / drain terminal of the selection transistor 212 is each to a bit line 21 , and a control terminal or gate of the selection transistor 212 each to a word line 20 connected.

The further construction of the conduction paths of the reference cells 220 corresponds to the structure of the line paths of in 1 illustrated conventional circuit 100 , A bit line 21 is in each case connected to a first source / drain terminal of a p-channel transistor connected as a source follower 50 connected. A gate of a transistor 50 is in each case to a control line 25 , and a second source / drain terminal of a transistor 50 each to a first terminal of a diode 30 connected n-channel transistor (load element) connected. To a second terminal of a diode 30 is each a ground potential 10 created. A voltage drop across a diode 30 is in each case by one of three readout amplifiers 40 sampled. The readout amplifiers 40 are therefore via respective lines each with a terminal of a diode 30 or a node 31 between a diode 30 and a transistor 50 connected to one at a node 31 available potential.

In contrast, in the conduction path of the memory cell to be read 210 instead of a transistor operated as a source follower 50 a voltage regulation unit 60 intended. The voltage regulation unit 60 has a feedback operational amplifier 61 and a control transistor 62 on. The control transistor 62 is formed as a p-channel transistor. Here, the source / drain terminals of the control transistor 62 with the bit line 21 and with an n-channel diode 30 , and the gate of the control transistor 62 with an output of the operational amplifier 61 connected. To a first input of the operational amplifier 61 becomes a constant reference potential 11 created. Via a feedback line 63 becomes a at a source / drain terminal of the control transistor 62 or at a node 64 the bit line 21 applied potential to a second input of the operational amplifier 61 created.

For sampling a voltage drop across the diode 30 the conduction path of the memory cell 210 are the three readout amplifiers 40 via corresponding lines with the associated connection of the diode 30 or node 31 between the diode 30 and the control transistor 62 connected. To a second terminal of the diode 30 is the ground potential 10 created.

To evaluate the memory state of the memory cell 210 becomes the wordline 20 activated by applying a corresponding activation potential, whereby the selection transistors 212 the memory cell 210 and the reference cells 220 by turn. In this way, the resistance memory elements 211 the memory cell 210 and the reference cells 220 via the through-connected selection transistors 212 conducting with the bitlines 21 connected.

In addition, both to the memory cell 210 as well as to the reference cells 220 a predetermined reading voltage 15 applied to the flow of an electric current in the individual conduction paths of the high potential 12 to the ground potential 10 whose strength depends on the resistance states of the memory cell 210 and the reference cells 220 depends. The reading voltage 15 falls as in 2 indicated by arrows, substantially over the resistive memory elements 211 from.

Due to the fact that all reference states of the reference cells 220 lie in a low-resistance and in particular relatively small resistance range, can be the predetermined reading voltage 15 Reliable and with a low circuit complexity or space requirement using the transistors connected as a source follower 50 at the reference cells 220 to adjust. A reading voltage 15 at a reference cell 220 This corresponds essentially to the difference between the high potential 12 and one opposite the potential 12 lower potential on the corresponding bit line 21 ie a potential at a node 51 or source / drain terminal of a transistor 50 , To the with the gate of a transistor 50 connected control line 25 Therefore, a control potential is applied, which is the sum of the read voltage 15 determining potential at a node 51 and one on a transistor 50 decreasing gate-source or threshold voltage corresponds. In this way, the potential becomes a node 51 and thus the specified reading voltage 15 at a reference cell 220 reliably determined for all reference states.

The at the memory cell 210 applied voltage essentially corresponds to the difference between the high potential 12 and a potential on the bit line 21 ie a potential at the node 64 or source / drain terminal of the control transistor 62 , The potential at the node 64 is via the feedback line 63 to the second input of the operational amplifier 61 created. As is usual for such a circuit, the operational amplifier attempts 61 that at the node 64 potential applied to the via the first input of the operational amplifier 61 applied reference potential 11 to regulate. The reference potential 11 is at the given reading voltage 15 Voted. In this way, the potential becomes the node 64 to the reference potential 11 , and so on the memory cell 210 applied voltage reliably to the specified reading voltage 15 regulated. This applies to a relatively large resistance range, which includes both the high-resistance memory state and the low-resistance memory states of the memory cell 210 includes. Particularly in the case of a low-resistance memory state of the memory cell 210 is a collapse of the voltage using the voltage regulation unit 60 by raising the voltage to the specified reading voltage 15 compensated.

The electric current in the individual line paths gives a voltage drop to that of the memory cell 210 and the reference cells 220 associated diodes 30 and thus the height of the potentials at the terminals of the diodes 30 or to the node 31 before, which in turn through the readout amplifier 40 is scanned. Thereby the potentials at the nodes become 31 the conduction paths of the reference cells 220 each one of the three readout amplifiers 40 , and the potential at the node 31 the conduction path of the memory cell 210 from all three readout amplifiers 40 tapped to compare the potentials. The respective differences at the nodes 31 detected potentials are through the readout amplifier 40 strengthened. On the basis of the increased potential differences, the memory state of the memory cell 210 be determined.

3 shows a schematic representation of an integrated circuit 300 for reading out a resistive memory cell operated as a multilevel cell 310 according to another embodiment of the present invention. The structure of the circuit 300 and their operation is essentially the same as in 2 illustrated circuit 200 ,

The memory cell 310 which is a resistance memory element 311 and a selection transistor 312 is, for example, a PCRAM memory cell. In this case, the resistance memory element 311 two electrodes and a phase change material disposed between the electrodes (not shown). By applying electrical pulses to the electrodes using in 3 not shown circuit elements, the phase change material can be heated and thus switched between an amorphous and a crystalline phase state back and forth. Depending on the degree of formation of the crystalline phase state, the memory cell 310 in addition to a high-impedance memory state one of several low-impedance memory states.

Also at the in 3 illustrated scarf tung 300 becomes the memory cell 310 For example, in one of four possible memory states for storing 2-bit information offset, ie that the memory cell 310 It is possible to switch between the high-impedance memory state and three low-resistance memory states. For example, the high-resistance memory state corresponds to the memory cell 310 an effective electrical resistance of 1 MΩ, whereas the low-ohmic storage conditions of the memory cell 310 Resistance values in the kΩ range, ie, for example, 1 kΩ, 3 kΩ and 5 kΩ.

An evaluation of the memory state of the memory cell 310 in turn, using three of the memory cell 310 associated reference cells 320 performed, which reference states with resistance values between the individual memory states of the memory cell 310 exhibit. The reference states of the reference cells 320 can in one compared to the high-resistance memory state of the memory cell 310 low resistance and relatively small resistance range, ie kΩ range, and effective electrical resistances of, for example, 2 kΩ, 4 kΩ and 8 kΩ correspond. Also with the reference cells 320 is it like in 3 represented by resistive memory cells each having a resistive memory element 311 and a selection transistor 312 which are offset in the corresponding different reference states.

Differences to the circuit 200 from 2 consist essentially in the exchange of potentials 10 and 12 in the individual conduction paths, and in the different arrangement of the resistive memory element 311 and the selection transistor 312 in a memory cell 310 or a reference cell 320 , So are acting as load elements diodes 30 , which in the present case are formed by p-channel transistors, in the circuit 300 with a high potential 12 , and the memory cell 310 or the reference cells 320 with a ground potential 10 connected. Also is a resistance memory element 311 the memory cell 310 or the reference cells 320 directly to a bit line 21 connected, whereas one via a word line 20 activatable selection transistor 312 with the ground potential 10 connected is.

In the conduction paths of the reference cells 320 are in turn connected as source follower transistors 50 for setting one to a predetermined reading voltage 15 matched potential on the bit lines 21 or at nodes 51 and thus for setting the read voltage 15 at the reference cells 320 used. The transistors 50 are of the n-channel type. The gates of the transistors 50 are in turn connected to a control line 25 connected.

Since all reference states of the reference cells 320 lie in a low-resistance and in particular relatively small resistance range, can be the predetermined reading voltage 15 using the transistors 50 reliable on the reference cells 320 to adjust. A reading voltage 15 at a reference cell 320 This corresponds essentially to the difference between one compared to the ground potential 10 higher potential on the corresponding bit line 21 ie a potential at a node 51 or source / drain terminal of a transistor 50 , and the ground potential 10 , Due to the opposite circuit 200 from 2 exchanged potentials 10 . 12 run the one reading voltage 15 characterizing arrows in 3 in one opposite 2 reverse direction.

In the conduction path of the memory cell 310 is in turn a voltage regulation unit 60 with a feedback operational amplifier 61 and one to an output of the operational amplifier 61 connected control transistor 62 intended. The control transistor 62 is in this case of the n-channel type. To a first input of the operational amplifier 61 is one to the specified reading voltage 15 coordinated reference potential 11 , and to a second input of the operational amplifier 61 via a feedback line 63 one at a node 64 the bit line 21 applied potential applied. This becomes the potential at the node 64 to the reference potential 11 , and so on the memory cell 310 applied voltage reliably to the specified reading voltage 15 regulated. The reading voltage 15 at the memory cell 310 This corresponds essentially to the difference between the potential at the node 64 and the ground potential 10 , The regulation of the voltage at the memory cell 310 to the specified reading voltage 15 using the voltage regulation unit 60 is possible for a relatively large resistance range, which includes both the high-resistance memory state and the low-resistance memory states of the memory cell 310 includes. In this way, in particular a collapse of the reading voltage 15 in a low-resistance memory state of the memory cell 310 compensated.

An evaluation of the memory state of the memory cell 310 is done using three readout amplifiers 40 performed, each of which is predetermined by a current flow voltage drop across diodes 30 in the individual conduction paths. For this purpose, potentials at nodes 31 the conduction paths of the reference cells 320 in each case to one of the three readout amplifiers 40 , and the potential at a node 31 the conduction path of the memory cell 310 to all three readout amplifiers 40 created. The respective differences of the potentials at the nodes 31 be through the readout amplifiers 40 strengthened. On the basis of increased potential the memory state of the memory cell can differ 310 be determined.

4 shows a schematic representation of an electronic device 400 with a memory module 410 according to an embodiment of the present invention. In the electronic device 400 For example, it may be a memory device 410 or several memory modules 410 act exhibiting memory module. Alternatively, the electronic device may 400 also act on a board or motherboard of a computer. Here, the electronic device 400 next to the memory chip 410 or several memory modules 410 other components such as an in 4 indicated control device 70 exhibit.

The memory chip 410 the device 400 has a circuit structure according to the circuit 200 respectively. 300 of the 2 and 3 with a variety of resistive memory cells 411 and reference cells 412 on. The memory cells 411 and reference cells 412 are matrix-shaped in the form of rows and columns at crossing points of a plurality of word lines 20 and bitlines 21 and each have a resistive memory element and a selection transistor. In the memory cells 411 and reference cells 412 these can be both CBRAM and PCRAM memory cells. For clarity, in 4 only three lines or word lines 20 and seven columns or bit lines 21 shown. Also was on the representation of applied to the individual line paths potentials 10 and 12 waived.

A memory cell 411 is switchable between a high-impedance memory state and three low-resistance memory states. Den at a wordline 20 arranged memory cells 411 are therefore each three on the relevant word line 20 arranged reference cells 412 assigned. The three reference cells 412 each have different resistance values or reference states between the individual memory states of a memory cell 411 on. The reference states can be in a low-resistance range.

For controlling a read voltage of the bit lines 21 arranged resistive memory cells 411 are voltage regulation units 60 intended. The voltage regulation units 60 may each comprise an operational amplifier and a control transistor, and are connected to the respective bit lines 21 the conduction paths of the memory cells 411 connected. For setting the read voltage of the bit lines 21 arranged reference cells 412 are three transistors operated as source followers 50 provided, which with the jewei time bit lines 21 the conduction paths of the reference cells 412 and a control line 25 are connected.

Both the voltage regulation units 60 as well as the transistors 50 are further according to the circuits 200 respectively. 300 of the 2 and 3 to serve as load elements diodes 30 connected. Voltage drops at the diodes 30 become of three readout amplifiers 40 scanned via corresponding lines. This will cause the voltage drops across the diodes 30 the conduction paths of the reference cells 412 each one of the readout amplifier 40 detected. The voltage drops at the diodes 30 the conduction paths of the memory cells 411 can be using in the wires between the diodes 30 and the readout amplifiers 40 arranged switching elements 80 selectively from the three readout amplifiers 40 be scanned. A switching element 80 may be formed as a switching transistor, and is via a corresponding selection line 81 activated.

For determining the memory state of a memory cell arranged in a specific row and column 411 becomes the wordline in question 20 activated. In this way, the resistive memory elements of all the memory cells become 411 and reference cells 412 the selected row via the associated switched selection transistors with the bit lines 21 or ground potentials 10 conductively connected, whereby each one of the respective resistance state of the memory cells 411 and reference cells 412 dependent current flows in the individual line paths.

Furthermore, a switching element 80 the memory cell to be read 411 associated column using the appropriate select line 81 activated. In this way, the predetermined by the electric current voltage drop across the diode 30 the relevant column of the three readout amplifiers 40 detected. Also, the voltage drops on the diodes 30 the conduction paths of the reference cells 412 from the sense amplifiers 40 sampled. In this case, as with the above 2 and 3 explains potential differences between the diodes 30 the individual conduction paths through the readout amplifiers 40 strengthened.

Based on the through the readout amplifiers 40 amplified potential differences, the controller 70 an evaluation of the memory state of the selected memory cell 411 make. Also the described activation of a word line 20 and a switching element 80 using the appropriate selection line 81 can by the control device 70 be carried out or initiated.

5 shows a schematic representation of an electronic device 420 with a memory module 430 according to another embodiment of the present invention. Also with the device 420 For example, it may be both a memory module with one or more memory modules 430 , as well as a motherboard with one or more memory modules 430 and optionally further components such as a control device 70 act.

The memory chip 430 has essentially the same structure and the same operation as in 4 illustrated memory module 410 on. In contrast to the memory module 410 is at the memory chip 430 from 5 but only a voltage regulation unit 60 and a diode 30 for all resistive memory cells 411 intended. As a result, the memory chip is characterized 430 by a particularly small footprint or circuit complexity. The voltage regulation unit 60 Here is about switching elements 80 switchable with the bit lines 21 the conduction paths of the memory cells 411 connected. According to the in 4 illustrated memory module 410 becomes a switching element 80 via an appropriate selection line 81 activated.

The basis of the 2 to 5 Illustrated embodiments are preferred embodiments of the invention. In addition, further embodiments can be realized, which comprise further modifications of the invention.

For example can Reference cells be designed as fixed electrical resistors, instead of resistive To use memory cells as reference cells. Also, load elements, at which a voltage drop is sensed using others Circuit elements as transistors or diodes such as Resistive elements be realized.

In addition, a memory device may have a structure in which the circuit structure of FIG 4 and 5 illustrated memory blocks 410 . 430 with at a wordline 20 arranged memory cells 411 , the memory cells 411 associated three reference cells 412 , the voltage regulation unit (s) 60 , the three transistors 50 , the diodes 30 and the three readout amplifiers 40 is repeated several times in the row direction.

Also, a voltage regulation unit with other than that in the 2 and 3 be formed structure shown. For example, it is possible to provide, instead of an operational amplifier, circuit elements which compare a potential applied to a bit line according to an operational amplifier with a reference potential for voltage regulation.

Furthermore, it is possible to operate resistive memory cells as multilevel cells for storing more than 2 bits. In general, the storage of n-bit information can be realized by means of 2 ⁿ distinguishable memory states of a memory cell and a high-resistance and (2 ⁿ -1) low-resistance memory states of a memory cell. An evaluation of the memory state of a memory cell is in this case carried out by means of (2 ⁿ -1) Referenzzel len, which each have different resistance values or reference states between the individual memory states of the memory cell. Correspondingly, (2 ⁿ -1) readout amplifiers can be used here.

Further are the described embodiments not limited to memory cells of the CBRAM or PCRAM type. Embodiments of Invention can be correspondingly further resistive Apply storage concepts where the generation is more distinguishable resistance states a memory cell based on other electrical phenomena and properties. For example, memory on the basis may be considered here of transition metal oxides.

Claims (29)

Integrated circuit, comprising: - a resistive memory cell ( 210 . 310 . 411 ), which is switchable between a high-impedance memory state and at least one low-resistance memory state; At least one reference cell ( 220 . 320 . 412 ), the reference cell ( 220 . 320 . 412 ) has a resistance value representing a reference state; - a first facility ( 60 ) for applying a predetermined reading voltage ( 15 ) to the resistive memory cell ( 210 . 310 . 411 ), the first facility ( 60 ), the read voltage ( 15 ) for a first resistance region which determines the memory states of the resistive memory cell ( 210 . 310 . 411 ); and - a second device ( 50 ) for applying the predetermined reading voltage ( 15 ) to the reference cell ( 220 . 320 . 412 ), the second device ( 50 ), the read voltage ( 15 ) for a smaller compared to the first resistance region second resistance region, which the reference state of the reference cell ( 220 . 320 . 412 ). An integrated circuit according to claim 1, wherein said first means is a voltage regulation unit ( 60 ) for controlling one at the resistive memory cell le ( 210 . 310 . 411 ) applied voltage to the predetermined reading voltage ( 15 ) having. An integrated circuit according to claim 2, wherein the voltage regulation unit ( 60 ) a feedback operational amplifier ( 61 ) and one with the operational amplifier ( 61 ) connected control transistor ( 62 ) having. Integrated circuit according to one of the preceding claims, wherein the second device comprises a transistor (2) operated as a source follower. 50 ) for setting the reading voltage ( 15 ) at the reference cell ( 220 . 320 . 412 ) having. Integrated circuit according to one of the preceding claims, wherein the resistive memory cell ( 210 . 310 . 411 ) can be switched between the high-impedance memory state and three low-resistance memory states. Integrated circuit according to Claim 5, with three of the resistive memory cells ( 210 . 310 . 411 ) associated reference cells ( 220 . 320 . 412 ), the three reference cells ( 220 . 320 . 412 ) three different resistance values for reproducing reference states between the individual memory states of the resistive memory cell ( 210 . 310 . 411 ), and wherein the second resistance region of the second device ( 50 ) comprises the three different reference states. Integrated circuit according to one of the preceding claims, wherein the resistive memory cell ( 210 . 310 . 411 ) a resistance memory element ( 211 . 311 ) and a selection transistor ( 212 . 312 ) having. Integrated circuit according to one of the preceding claims, wherein a reference cell ( 220 . 320 . 412 ) is a resistive memory cell which is switched to a reference state. Memory module, comprising: - a plurality of word lines ( 20 ) and bitlines ( 21 ) - a plurality of resistive memory cells ( 210 . 310 . 411 ), wherein a resistive memory cell ( 210 . 310 . 411 ) at a crossing point of a word line ( 20 ) and a bit line ( 21 ) is arranged and is switchable between a high-impedance memory state and at least one low-resistance memory state; A plurality of reference cells ( 220 . 320 . 412 ), wherein a reference cell ( 220 . 320 . 412 ) at a crossing point of a word line ( 20 ) and a bit line ( 21 ) and has a resistance value representing a reference state; - a first facility ( 60 ) for applying a predetermined reading voltage ( 15 ) to a resistive memory cell ( 210 . 310 . 411 ) for causing an electric current in one of the resistive memory cells ( 210 . 310 . 411 ) associated bit line ( 21 ), the first facility ( 60 ), the read voltage ( 15 ) for a first resistance region which determines the memory states of the resistive memory cell ( 210 . 310 . 411 ); - a second facility ( 50 ) for applying the predetermined reading voltage ( 15 ) to a reference cell ( 220 . 320 . 412 ) for causing an electric current in one of the reference cells ( 220 . 320 . 412 ) associated bit line ( 21 ), the second device ( 50 ), the read voltage ( 15 ) for a smaller compared to the first resistance region second resistance region, which the reference state of the reference cell ( 220 . 320 . 412 ); and - an evaluation device ( 30 . 40 ) to determine the memory state of a resistive memory cell ( 210 . 310 . 411 ). A memory device according to claim 9, wherein the first device is a voltage regulation unit ( 60 ) for controlling a resistive memory cell ( 210 . 310 . 411 ) applied voltage to the predetermined reading voltage ( 15 ) having. Memory chip according to claim 10, wherein the voltage regulation unit ( 60 ) a feedback operational amplifier ( 61 ) and one with the operational amplifier ( 61 ) connected control transistor ( 62 ) having. Memory module according to one of claims 10 or 11, wherein the voltage regulation unit ( 60 ) with a bit line ( 21 ) for voltage regulation at the bit line ( 21 ) arranged resistive memory cells ( 210 . 310 . 411 ) connected is. Memory module according to one of claims 10 or 11, wherein the voltage regulation unit ( 60 ) switchable with the bitlines ( 21 ) connected is. Memory device according to one of Claims 9 to 13, the second device having a transistor (FIG. 50 ) for setting the reading voltage ( 15 ) on a reference cell ( 220 . 320 . 412 ) having. Memory chip according to claim 14, wherein the transistor operated as a source follower ( 50 ) with a bit line ( 21 ) for setting the reading voltage ( 15 ) at the bit line ( 21 ) arranged reference cells ( 220 . 320 . 412 ) connected is. Memory chip according to one of claims 9 to 15, wherein a resistive memory cell ( 210 . 310 . 411 ) can be switched between the high-impedance memory state and three low-impedance Spei cherzuständen. A memory device according to claim 16, wherein a resistive memory cell ( 210 . 310 . 411 ) three reference cells ( 220 . 320 . 412 ), the three reference cells ( 220 . 320 . 412 ) three different resistance values for reproducing reference states between the individual memory states of the resistive memory cell ( 210 . 310 . 411 ), and wherein the second resistance region of the second device ( 50 ) comprises the three different reference states. A memory device according to claim 17, wherein on a word line ( 20 ) arranged resistive memory cells ( 210 . 310 . 411 ) three reference cells ( 220 . 320 . 412 ) assigned. Memory module according to one of claims 9 to 18, wherein the evaluation device the resistive memory cells ( 210 . 310 . 411 ) and the reference cells ( 220 . 320 . 412 ) associated load elements ( 30 ) and a readout amplifier ( 40 ), wherein the electric current in a resistive memory cell ( 210 . 310 . 411 ) and in a reference cell ( 220 . 320 . 412 ) associated bit line ( 21 ) a voltage drop across one of the resistive memory cells ( 210 . 310 . 411 ) and at one of the reference cell ( 220 . 320 . 412 ) associated load element ( 30 ), which in each case by the readout amplifier ( 40 ) is scanned. A memory device according to claim 19, wherein a load element is a diode ( 30 ). Memory chip according to one of Claims 9 to 20, wherein a resistive memory cell ( 210 . 310 . 411 ) a resistance memory element ( 211 . 311 ) and a selection transistor ( 212 . 312 ) having. Memory chip according to one of claims 9 to 21, wherein a reference cell ( 220 . 320 . 412 ) is a resistive memory cell which is switched to a reference state. Electronic device with a memory module according to one of the claims 9 to 22. Method for determining a memory state of a resistive memory cell ( 210 . 310 . 411 ), wherein the resistive memory cell ( 210 . 310 . 411 ) is switchable between a high-impedance memory state and at least one low-impedance memory state, comprising the method steps: - applying a predetermined read voltage ( 15 ) to the resistive memory cell ( 210 . 310 . 411 ), the reading voltage ( 15 ) is generated for a first resistance region, which determines the memory states of the resistive memory cell (FIG. 210 . 310 . 411 ); Detection of an electrical measured variable as a function of a voltage 15 ) at the resistive memory cell ( 210 . 310 . 411 ) caused electric current; - applying the predetermined reading voltage ( 15 ) to a reference cell ( 220 . 320 . 412 ), the reference cell ( 220 . 320 . 412 ) has a resistance value representing a reference state, and wherein the read voltage ( 15 ) is generated for a smaller compared to the first resistance region second resistance region, which the reference state of the reference cell ( 220 . 320 . 412 ); Detecting an electrical reference variable as a function of a through the read voltage ( 15 ) at the reference cell ( 220 . 320 . 412 ) caused electric current; and determining the memory state of the resistive memory cell ( 210 . 310 . 411 ) Based on a comparison of the measured variable with the reference size. A method according to claim 24, wherein as a measured variable and as a reference variable in each case a voltage drop across one of the resistive memory cells ( 210 . 310 . 411 ) and at one of the reference cell ( 220 . 320 . 412 ) associated load element ( 30 ) is used. Method according to one of claims 24 or 25, wherein one at the resistive memory cell ( 210 . 310 . 411 ) applied voltage to the predetermined reading voltage ( 15 ) is regulated. Method according to one of claims 24 to 26, wherein the resistive memory cell ( 210 . 310 . 411 ) can be switched between the high-impedance memory state and three low-resistance memory states. The method of claim 27, wherein the resistive memory cell ( 210 . 310 . 411 ) three reference cells ( 220 . 320 . 412 ) to which the predetermined reading voltage ( 15 ), the three reference cells ( 220 . 320 . 412 ) three different resistance values for reproducing reference states between the individual memory states of the resistive memory cell ( 210 . 310 . 411 ), and wherein the second resistance region comprises the three different reference states. A method according to claim 28, wherein three electrical reference quantities each depend on one by the read voltage ( 15 ) at the three reference cells ( 220 . 320 . 412 ) are detected, and wherein the memory state of the resistive memory cell ( 210 . 310 . 411 ) based on a comparison of the measured variable with the three Reference sizes is determined.