DE102007001783B4 - A semiconductor memory device, method for writing or recovering a threshold voltage, and for operating a semiconductor memory device - Google Patents

Abstract

A semiconductor memory device comprising: complementary first and second bit lines (BL, BLB); a unit memory cell having complementary first and second floating capacitor free floating body transistor memory cells (MC) coupled to the complementary first and second bit lines (BL, BLB), respectively; and a voltage sense amplifier (S / A) connected between the complementary first and second bit lines (BL, BLB) and amplifying a voltage difference (ΔVBL) between the complementary first and second bit lines (BL, BLB), the memory element has a capacitive coupling between the first and second bit lines which effects a negative bias for writing or restoring a threshold voltage of the first or second floating body transistor memory cell, the capacitive coupling comprising a parasitic capacitance between the first and second bit lines , or the capacitive coupling comprises a capacitive element, which is looped in between the first and second bit lines.

Description

The present invention relates to a semiconductor memory device, a method for writing or recovering a threshold voltage of a capacitor-free floating body-transistor memory cell element, and operating a semiconductor memory device.

Typically, the memory cells of dynamic random access memory (DRAM) are formed of a capacitor for storing charges and a transistor for accessing the capacitor. A logic value of each memory cell is determined by a voltage of the capacitor. However, in an effort to improve element integration, DRAM memory cells formed of a single transistor have been proposed. Such single transistor type memory cells are referred to herein as "capacitorless floating body transistor memory cells", and in certain cases, the acronym "transistor cell" is used.

In a write mode, the threshold voltage of a floating body-transistor capacitorless memory cell is varied by changing the channel body potential of the cell, and in a read mode, a distinction is made between logic states based on an amount of current flowing through the row. This will be further explained below with reference to 1 described in more detail.

1 FIG. 12 is a schematic cross-sectional view of an exemplary capacitor-free floating body transistor memory cell. FIG.

As shown, the capacitor-free floating body transistor memory cell according to the present example comprises a silicon (Si) substrate 100 and a buried oxide layer 101 , Above the buried oxide layer 101 is a floating channel body area or area 102 that is between source and drain regions 103 and 104 is arranged. A gate-thieves-cricket 105 and a gate electrode 106 are over a floating channel body area 102 aligned, and insulating layers 107 (eg SiO ₂ layers) are formed around the capacitor-free floating body transistor memory cell of other elements on the substrate 100 to isolate.

Logical "1" and "0" states are dependent on the threshold voltage Vth of the capacitor-free floating body transistor memory cell, and examples of write and read voltages applied to the capacitor-free floating body transistor memory cell are further shown below in Table 1: Table 1 Threshold (Vth) Source (Vs) Gate (Vg) Drain (Vd) Write "1" low 0V 1.5 V 1.5 V Write "0" high 0V 1.5 V -1.5 V Read - 0V 1.5 V 0.2V

During a data "1" write operation, a bias condition is set where Vgs> Vth and Vgd <Vth. This causes the transistor cell to operate in a saturation region. In this state, impact ionization occurs in the boundary or transition region between the drain region 104 and the floating channel body area 102 , The result will be holes in the floating channel body area 102 injected. This increases the potential of the floating channel body region 102 and reduces the threshold voltage Vth of the capacitor-free floating body transistor memory cell.

During a data "0" write operation, the drain voltage Vd is lowered to a negative voltage to provide a forward bias condition at the transition between the floating channel body region 102 and the drain region 104 to accomplish. The forward voltage or forward voltage causes in the floating channel body region 102 included holes in the drain area 104 hike. This reduces the potential of the floating channel body region 102 and increases the threshold voltage Vth.

During a read operation, a bias condition is set such that Vgs> Vth and Vgd> Vth, so that the transistor cell is operated in its linear region. A drain current is measured and compared with a reference cell current to thereby discriminate whether the capacitor-free floating body transistor memory cell is in a high (logic "0") or low (logic "0") "1") threshold Vth state. In particular, if the measured drain current is less than the reference current, a logic "0" state is read. If the measured drain current is greater than the reference current, a logic "1" state is read.

Conventionally, the reference cell current is generated using reference (or dummy) transistor cells programmed in "0" and "1" states, respectively. Further, a reference voltage generating circuit and other circuits are employed to generate a reference current that lies between the drain currents of the "0" and "1" reference transistor cells. Exemplary is on the US 6,567,330 directed.

The reading of capacitor-free floating body transistor memory cells is prone to a variety of errors. Examples of such errors are described below with reference to FIGS 2A to 2C described.

2A and 2 B show "0" state and "1" state drain current distributions 201 and 202 a number of capacitor-free floating body transistor memory cells and reference cell current distributions 203 that are associated with multiple read operations. 2A illustrates the case that the reference cell current distribution 203 and the "0" state drain current distribution 201 at 210 overlap and 2 B illustrates the case that the reference cell current distribution 203 and the "1" state drain current distribution 202 at 211 overlap. In both cases, read errors will occur. The overlap conditions 210 and 211 of the 2A and 2 B can come from a number of factors, including process changes, temperature changes, and so on.

2C shows the case that the transistor cell "0" state and the "1" state drain current distributions 201 and 202 together 212 overlap. This may be due to the volatile nature of capacitor-free floating body transistor memory cells. This means that leakage currents from the floating channel body region can lead to a drifting of the threshold voltages Vth of the cell transistors. It is therefore necessary to periodically refresh capacitor-free floating body transistor memory cells in the same manner in which conventional capacitor type DRAM cells are refreshed.

In addition to the above-described susceptibility to read errors, the DRAM type non-floating body transistor memory cell type of cell is disadvantageous in requiring the provision of a reference current generator, reference memory cells, and other circuits by the reference current to create. This might turn out to be a burden when trying to increase the integration density of the memory element. In addition, in a refresh operation, additional time is consumed to refresh the reference memory cells.

The WO 2004/102625 A2 shows a semiconductor memory device having complementary first and second bit lines, a unit memory cell having complementary first and second floating capacitor free floating body transistor memory cells coupled to the complementary first and second bit lines, respectively, and a voltage sense amplifier interposed between the complementary first and second bit lines are looped in and amplify a voltage difference between the complementary first and second bit lines.

The US 2005/0063224 A1 shows a programming method for floating body transistor memory cells.

The US 2005/0232043 A1 shows a semiconductor memory device with floating body transistor memory cells.

The invention is based on the technical problem of specifying a semiconductor memory element and a method for operating a semiconductor memory element which permit reliable operation and an increase in the density of the memory element.

The invention solves the problem by means of a semiconductor memory element having the features of patent claim 1 or patent claim 8 and a method of operating a semiconductor memory element having the features of patent claim 14.

Advantageous embodiments of the invention are specified in the subclaims, the wording of which is hereby incorporated by reference into the description in order to avoid unnecessary text repetitions.

Advantageous embodiments of the invention, which are described in detail below, as well as to simplify the understanding of the invention explained embodiments of the prior art are shown in the drawing. It shows / shows:

1 a cross-sectional view of a conventional capacitor-free floating body transistor memory cell;

2A to 2C Charts of cell current distributions of conventional capacitor-free floating body transistor memory cells;

3 a block diagram of a capacitor-free floating body transistor memory cell element according to an embodiment of the present invention;

4 a circuit diagram showing a unit memory cell and a sense amplifier according to an embodiment of the present invention;

5A to 5C Timing diagrams for explaining the operation of a capacitor-free floating body transistor memory cell element according to an embodiment of the present invention; and

6A to 6C Timing diagrams for explaining the operation of a capacitor-free floating body transistor memory cell element according to another embodiment of the present invention.

In the drawings, the absolute and relative sizes of layers and regions may be exaggerated and / or simplified for the sake of clarity. In addition, it should be understood that when one element or layer is described as being "on," "connected to," or "coupled to" with respect to another element or layer, it directly adjoins the other element or layer may be arranged, connected to this or this or coupled to this or this or that intermediate elements or layers may be present.

3 FIG. 12 is a block diagram of a capacitor-free floating body transistor memory cell device according to an embodiment of the present invention. FIG.

The memory cell element according to the example of 3 includes a memory cell array 100 , a row decoder 200 , a column decoder 300 and a control block 400 ,

The memory cell array 100 comprises a plurality of memory blocks BLK <1: k>, as in 3 shown. Each memory block BLK <1: k> comprises a plurality of word lines WL <1: m>, a plurality of true bit lines BL <1: n> and a plurality of complementary bit lines BLB <1: n>. In the present example, the bit lines BL <1: n> and the complementary bit lines BLB <1: n> are alternately arranged within each memory block BLK <1: k>, as in FIG 3 shown.

Each bit line BL and its complementary bit line BLB are collectively referred to herein as "bit line pair" BL / BLB. Accordingly, within the present exemplary embodiment, there are "n" bit line pairs BL / BLB <1: n> per memory block BLK.

As later (with reference to 4 ) is described in more detail, at each intersection of the word lines WL <1: k><1:m> and the bit lines BL <1: n> and BLB <1: n> within each memory block BLK <1: k> is a capacitor-free floating -Body-transistor memory cell MC arranged. A "unit memory cell" in this embodiment is defined by a first capacitor-free floating body transistor memory cell MC connected to a true bit line BL, and a second capacitor-free floating body transistor memory cell MC connected to a complementary bit line BLB connected is. The unit memory cell stores a logic value as indicated by complementary threshold voltage states of the first and second floating body-transistorless capacitor memory cells. That is, each of the unit memory cells includes complementary first and second floating capacitor body-transistor memory cells having opposite threshold voltage states. According to the present exemplary embodiment, the capacitor-free floating body transistor memory cells are transistors of the NMOS type.

Since there are "m" word lines WL per memory block and "n" bit line pairs BL / BLB per memory block BLK, each of the "k" memory blocks BLK contains the memory cell array 100 "M × n" unit memory cells.

Further referring to 3 For example, a pair of isolation gates ISOG and a sense amplifier S / A are connected between corresponding bit line pairs BL / BLB of adjacent memory blocks BLK. In the present exemplary embodiment, all pairs of isolation gates ISOG and sense amplifiers S / A, which are connected between odd-numbered bit line pairs BL / BLB, are shifted to the right (referring to the illustration of FIG 3 ) are aligned with respect to the odd-numbered memory blocks BLK, and the groups of isolation gates ISOG and sense amplifiers S / A which are looped between even-numbered bit line pairs BL / BLB are to the right (referring to the illustration in FIG 3 ) with respect to the even-numbered memory blocks BKL.

The word lines WL <1: k><1:m> are connected to the row decoder 200 connected, as in 3 shown. Furthermore, the column decoder generates 300 Column select signals CSL <1: n> which are applied to the respective sense amplifiers S / A of the complementary bit line pairs BL / BLB <1: n>. In addition, the control block generates 400 a number of control signals for the isolation gates ISOG and sense amplifiers S / A associated with each memory block BLK. These control signals include first and second isolation signals ISO1 and ISO2, first and second sense amplifier control signals LA and LAB, and a ground select line signal GSL. Furthermore, although not shown in the figure to avoid complexity, complementary data lines are applied to column select gate terminals (not shown) of sense amplifiers S / A associated with each memory block BLK.

Reference will now be made to 4 , which illustrates an example of the isolation gates IOSG and the sense amplifier S / A, which are connected between bit line pairs BL / BLB of adjacent memory blocks BLK1 and BLK2.

In the first memory block BLK1, a unit memory cell TMC (also referred to herein as a twin memory cell) is formed by complementary first and second floating body floating memory cells FN1 and FN1B, each connected to a word line WL with its gate terminal. The first capacitor-free floating body memory cell FN1 is connected between the true bit line BL and a first select line SL1, and the second capacitor-free floating body memory cell FN1B is connected between the complementary bit line BLB and a second select line SL2.

A first transmission gate TG1 is connected between the first selection line SL1 and a ground selection line GSL, and a second transmission gate TG2 is connected between the second selection line SL2 and the ground selection line GSL. The first transmission gate TG1 comprises NMOS transistors N1 and N2, each of which has its gate connected to the true bit line and the ground select line GSL. Likewise, the second transfer gate TG2 comprises NMOS transistors N3 and N4, each of which has its gate connected to the complementary bit line BLB and the ground select line GSL.

In 4 By means of a broken line, a parasitic capacitance Cb1 is shown between the true bit line BL and the complementary bit line BLB. As will be described in more detail later, one or more embodiments of the invention operate to use this parasitic capacitance Cb1 to recover one or more threshold voltages of the twin memory cell TMC.

The second memory block BLK2 is formed in a similar manner as the first memory block BLK1 described above.

A first isolation gate ISOG1 comprises an NMOS transistor N5 connected between a true sub-bit line SBL and the true bit line BL of the first memory block BLK, and an NMOS transistor N6 connected between a complementary sub-bit line SBLB and the complementary bit line BLB of the first memory block BLK1 is looped. Similarly, a second isolation gate ISOG2 includes an NMOS transistor N7 connected between the true sub-bit line SBL and the true bit line BL of the second memory block BLK2, and an NMOS transistor N8 connected between the complementary sub-bit line SBLB and the complementary bit line BLB of the second memory block BLK2 is looped. The NMOS transistors N5 and N6 of the first isolation gate ISOG1 receive at their gate terminals a first isolation signal ISO1, and the transistors N7 and N8 of the second isolation gate ISOG2 receive at their gate terminals a second isolation signal ISO2.

The sense amplifier S / A comprises a column selection gate CSLG formed by NMOS transistors N9 and N10. The NMOS transistor N9 is connected between a true data line D and the true sub-bit line SBL. The NMOS transistor N10 is connected between a complementary data line DB and the complementary sub-bit line SBLB. Each of the NMOS transistors N9 and N10 receives at its gate terminal a column select signal CSL.

The sense amplifier S / A further comprises sense amplifier NMOS transistors N11 and N12 and PMOS transistors P1 and P2. The NMOS transistors N11 and N12 are connected in series between the true sub-bit line SBL and the complementary sub-bit line SBLB. Similarly, the PMOS transistors P1 and P2 are also connected in series between the true sub-bit line SBL and the complementary sub-bit line SBLB. The NMOS transistor N12 and the PMOS transistor P2 are connected with their gate terminal to the true sub-bit line SBL, while the NMOS transistor N11 and the PMOS transistor P1 are connected with their gate terminal to the complementary sub-bit line SBLB. Further, a first sense amplifier control signal LA is applied to the connection node between the PMOS transistors P1 and P2, and a second sense amplifier control signal LAB is applied to the connection node between the NMOS transistors N11 and N12.

An operation of the capacitor-free floating body memory cell element of 3 and 4 According to one embodiment of the present invention will now be with reference to the 5A to 5C described.

With common reference to the 3 . 4 and 5A First, an activation operation according to an embodiment of the present invention will be described. The activation operation includes a recovery function, and time intervals T1 and T2 of the activation operation are executed before each read and write operation.

At the beginning of a bit line charging time interval T1, the control block 400 in that the ground selection line signal GSL and the first isolation signal ISO1 assume the value HIGH (eg 2 V). Thereby, the transmission gates TG1 (transistor N2) and TG2 (transistor N4) are turned ON, the true bit line BL is connected to the true sub-bit line SBL, and the complementary bit line BLB is connected to the complementary sub-bit line SBLB. In addition, the row decoder activates the word line WL in the HIGH state (for example, 2 V or more), and thus the capacitor-free floating body transistor memory cells FN1 and FN1B are turned on to an extent that depends on their respective threshold voltages.

As a result of the diverging threshold voltages of the floating-body-transistor memory cells FN1 and FN1B, the voltage of the true bit line BL deviates from that of the complementary bit line BLB. For example, assume that data "1" has been written in the memory cell FN1 and data "0" in the memory cell FN1B. In this case, the threshold voltage Vth1 of the memory cell FN1 is lower than the threshold voltage Vth0 of the memory cell FN1B. Assuming a 2V supply voltage (VCC = 2V), this means that the true bit line voltage VBL and the complement bit line voltage VBLB approximate the following relationships: VBL = 2V - VthN2 - Vth1 VBLB = 2V - VthN4 - Vth0

Thus, the following voltage difference ΔVBL results between VBL and VBLB, as in FIG 5A shown: ΔVBL = Vth0 - Vth1

For example, ΔVBL may be on the order of about 0.3V when the supply voltage is 2V.

The time interval T2 serves to restore a data "1" in one of the capacitor-free floating body transistor memory cells FN1 and FN1B. In the present example, the data "1" in memory cell FN1 is refreshed.

The control block 400 causes the ground select line signal GSL to become LOW (eg, 0V), turning off the transfer gates TG1 (transistor N2) and TG2 (transistor N4), and putting the bit lines BL / BLB in a floating state. In addition, the first sense amplifier control signal LA is activated with a level HIGH (eg, 2V), and the second sense amplifier control signal LAB is activated at the value LOW (eg, 0V). The sense amplifier S / A thus detects the bit line voltage difference ΔVBL and, in the present example, boosts the voltage of the true bit line BL to the value VCC (e.g., 2V) and the voltage of the complementary bit line BLB to VSS (e.g. B. mass). During this time, the voltage of the true bit line BL (VCC) is applied to the memory cell FN1 to restore the data "1" of the memory cell FN1.

The time interval T3 serves to restore a data "0" in one of the capacitor-free floating body transistor memory cells FN1 and FN1B. In the present example, the data "0" in memory cell FN1B is refreshed.

The control block 400 causes the isolation signal ISO1 to become LOW (eg, 0V) to thereby electrically isolate the bit lines BL and BLB from the sub-bit lines SBL and SBLB, respectively. As a result, the voltage of the true bit line BL drops to the threshold voltage VthN1 of the transistor N1.

Furthermore, the voltage of the complementary bit line BLB is initially driven to a negative voltage due to the parasitic capacitance Cb1 between the true bit line BL and the complementary bit line BLB. This means that the parasitic capacitive coupling causes a blocking voltage between the capacitor-free floating body transistor memory cell FN1B and the complementary bit line BLB. Thus, during this time, the data "0" is restored in the floating body-transistor capacitor memory cell FN1B. Finally, the voltage of the complementary bit line BL assumes the threshold voltage VthN4 of the transistor N4.

With common reference to the 3 . 4 and 5B Now, a write operation according to an embodiment of the present invention will be described. By way of example, a case is illustrated in which a data "1" is written in the capacitor-free floating body transistor memory cell FN1 and a data "0" in the capacitor-free floating body transistor memory cell FN1B.

Time intervals T1 and T2 of the write operation according to 5B correspond to the time intervals T1 and T2 of the activation operation described above in connection with FIG 5A has been described. Accordingly, a detailed description thereof will be omitted to avoid repetition.

During the time interval T3, the column decoder speaks 300 to a write command and a column address to enable the column select line signal CSL to be HIGH (eg, 2V). This causes the column select gate CSLG to electrically connect the true data line D to the true sub-bit line SBL and the complementary data line DB to the complementary sub-bit line SBLB. Further, since the isolation signal ISO1 is activated to the value HIGH, a data "1" of the true data line D and a data "0" of the complementary data line DB are transmitted to the true bit line BL and the complementary bit line BLB, respectively. As a result, according to the present example, the voltage of the true bitline BL assumes approximately the value VCC (eg, 2V) which causes the data "1" to be written to the capacitor-less floating body transistor memory cell FN1.

During the time interval T4, the column decoder deactivates 300 the column selection line signal CSL to the value LOW, and the control block 400 deactivates the isolation signal ISO to the value LOW and the sense amplifier control signals LA and LAB to the value LOW or HIGH. As with restoring "0" (T3) according to the one described above 5A causes the parasitic capacitance Cb1 between the true bit line BL and the complementary bit line BLB that the complementary bit line BLB is initially driven to a negative voltage. The parasitic capacitive coupling causes a blocking voltage between the capacitor-free floating body transistor memory cell FN1B and the complementary bit line BLB. Thus, the data "0" is written into the capacitor-free floating body transistor memory cell FN1B during the time interval T4.

With common reference to the 3 . 4 and 5C Now, a reading operation according to an embodiment of the present invention will be described. As before, an example is presented in which a data "1" is read from the floating-body-transistor floating-capacitor memory cell FN1 and a data "0" is read from the floating-body-transistor floating-capacitor memory cell FN1B.

Time intervals T1 and T2 of the read operation according to 5C correspond to the time intervals T1 and T2 of the activation operation described above in connection with FIG 5A has been described. Accordingly, detailed description is omitted to avoid repetition.

During the time interval T3, the column decoder speaks 300 to a read command and an address to enable the column select line signal CSL to be HIGH. Thereby, a data "1" on the true sub-bit line SBL is transmitted to the true data line D, and a data "0" is transmitted on the complementary sub-bit line SBLB to the complementary data line DB.

Thereafter, the time interval T4 is executed in the same manner as previously in connection with the time interval T3 in FIG 5A described so that the data "0" of the capacitor-free floating body transistor memory cell FN1B is restored.

The memory element and methods of operation described above offer a number of advantages over conventional floating body transistor capacitor memory elements. For example, by applying a sufficiently high voltage as the ground selection line signal GSL, the bit line voltage difference ΔVBL can be generated to enable the use of a voltage sense amplifier in contrast to the conventional consuming current sense amplifiers. In addition, it is not necessary to equalize the bit lines BL and BLB after the activation operation since ΔVBL is generated during the bit line load operation. In addition, the design of the circuit is simplified by using parasitic capacitive coupling between the bit lines BL and BLB to achieve a reverse bias state which recovers data "0" in the floating body-transistor memory cell (s) and / / or write.

Furthermore, the embodiment uses complementary capacitor-free floating body transistor memory cells to define each unit memory cell of the memory element, such as a DRAM element. Thus, the design offers the advantage of a high-density dense capacitor-free memory cell structure while avoiding the need for reference cells (or dummy cells), reference current generators, and other circuitry conventionally required to read the logic values of the transistor cells. Furthermore, by avoiding reference cells, the processing time is not prolonged by the refreshing of the reference cells.

In the above-described embodiment, the capacitance Cb1 is a parasitic capacitance between the conductive true bit line BL and the conductive complementary bit line BLB. As those skilled in the art will appreciate, these conductive connections or lines are separated by one or more isolators, thus forming parasitic capacitances. It should be noted, however, that a true capacitive element may be electrically inserted between the bit lines BL and BLB to replace or supplement the parasitic capacitance Cb1.

An operation of the capacitor-free floating body transistor memory cell element of FIG 3 and 4 According to a further embodiment of the present invention will now be with reference to the 6A to 6C described.

The design of the 6A to 6C corresponds to the embodiment according to the 5A to 5C with the exception that gate-induced drain leakage (GIDL) is used instead of impact ionization to write a data "1" into the capacitor-free floating body transistor memory cell FN1 and / or or restore. That is, by driving the word line (WL) voltage to a negative voltage (eg, -0.6 V), the gate terminal of the memory cell FN1 becomes negative while the drain voltage of the memory cell FN1 is positive. As one skilled in the art understands, this circumstance may result in generation of GIDL current in memory cell FN1, which writes or restores a data "1" into memory cell FN1.

Referring to 6A At time t2, the WL voltage is driven to a negative voltage during the time interval T2 to produce a GIDL current which restores the data "1" in the memory cell FN1. Subsequently, during the time interval T3, the WL voltage becomes HIGH to restore a data "0" in the memory cell FN1B, as previously described in connection with FIG 5A described.

Similarly, in the write operation according to 6B and the reading operation according to 6C the WL voltage is driven to a negative voltage during time intervals T2 and T3 to produce a GIDL current which regenerates and / or writes a data "1" in memory cell FN1. Thereafter, the WL voltage during the time interval T4 assumes a value HIGH to restore a data "0" in the memory cell FN1B, as previously described in connection with FIG 5B and 5C has been described.

With the exception of the abovementioned deviations, the design of the 6A to 6C the embodiment of the previously described 5A to 5C , Accordingly, a detailed explanation of the 6A to 6C renounced to avoid repetition.

Claims (18)

Semiconductor memory element, comprising: complementary first and second bit lines (BL, BLB); a unit memory cell having complementary first and second floating capacitor free floating body transistor memory cells (MC) coupled to the complementary first and second bit lines (BL, BLB), respectively; and a voltage sense amplifier (S / A) connected between the complementary first and second bit lines (BL, BLB) and amplifying a voltage difference (ΔVBL) between the complementary first and second bit lines (BL, BLB), wherein the memory element has a capacitive coupling between the first and second bit lines that provides a negative bias for writing or restoring a threshold voltage of the first or second floating body transistor memory cell, the capacitive coupling having a parasitic capacitance between the first and second bit lines comprises second bit lines, or the capacitive coupling comprises a capacitive element, which is looped in between the first and second bit lines. A semiconductor memory device according to claim 1, characterized in that the voltage sense amplifier comprises: first and second NMOS transistors connected in series between the complementary first and second bit lines; and first and second PMOS transistors connected in series between the complementary first and second bit lines; wherein respective gate terminals of the first NMOS and PMOS transistors are connected to the first bit line, and respective gate terminals of the second NMOS and PMOS transistors are connected to the second bit line. The semiconductor memory device according to claim 1 or 2, further comprising an isolation gate connected between the voltage sense amplifier and the first and second bit lines. A semiconductor memory device according to any one of claims 1 to 3, characterized in that the sense amplifier comprises complementary first and second sub-bit lines and a column selection gate which selectively connects the first and second sub-bit lines to complementary first and second data lines, respectively. Semiconductor memory element according to one of claims 1 to 4, characterized in that the first and second capacitor-free floating body transistor memory cells are connected via gate terminals to a word line. The semiconductor memory device of claim 1, further comprising a ground select line and first and second transfer gates, wherein the first transfer gate and the first capacitor-free floating body transistor memory cell are connected in series between the ground select line and the first bit line and wherein the second transfer gate and the second capacitor-free floating body transistor memory cell are connected in series between the ground select line and the second bit line. A semiconductor memory device according to claim 6, characterized in that the first transmission gate comprises a first transistor whose gate terminal is connected to the first bit line, and a second transistor whose gate terminal is connected to the ground selection line, and that second transmission gate has a third transistor whose gate terminal is connected to the second bit line, and a fourth transistor whose gate terminal is connected to the ground selection line. Semiconductor memory element with a memory cell array ( 100 ) having a plurality of memory cell blocks (BL1~BLk) and a plurality of voltage sense amplifiers (S / A) connected to the plurality of memory cell blocks (BL1~BLk), each of the memory cell blocks (BL1~BLk) being complementary first and second bit lines (BL, BLB) and a unit memory cell having complementary first and second floating capacitor free floating body transistor memory cells (MC) connected to the complementary first and second bit lines (BL, BLB), respectively has a capacitive coupling between the first and second bit lines that provides a negative bias for writing or restoring a threshold voltage of the first or second floating body transistor memory cells, the capacitive coupling comprising a parasitic capacitance between the first and second bit lines , or the capacitive coupling comprises a capacitive element that zw The first and second bit lines are looped in. A semiconductor memory device according to claim 8, characterized in that the complementary first and second floating capacitorless body-transistor memory cells are connected via gate terminals to the word lines within each memory cell block. The semiconductor memory device of claim 9, further comprising a row decoder connected to the word lines within each memory cell block. The semiconductor memory device according to any one of claims 8 to 10, further comprising a column decoder which selectively connects first and second data lines to the first and second bit lines, respectively. The semiconductor memory device according to any one of claims 8 to 11, further comprising a control block that controls an operation of the plurality of sense amplifiers. A semiconductor memory device according to any one of claims 8 to 12, characterized in that the sense amplifier comprises complementary first and second sub-bit lines and a column selection gate which selectively connects the first and second sub-bit lines to complementary first and second data lines, respectively. Method for operating a semiconductor memory element, comprising the steps: Restoring a low threshold state of a complementary first capacitor-free floating body transistor memory cell (MC) connected to a first bit line (BL); and Restoring a high threshold state of a complementary second capacitor-free floating body transistor memory cell (MC) connected to a second bit line (BLB); wherein the high threshold state of the complementary second capacitor-free floating body transistor memory cell (MC) is restored by capacitively coupling the first and second bit lines (BL, BLB) causing a voltage of the second bit line (BLB) to become negative. A method according to claim 14, characterized in that impact ionization is used to restore the low threshold state of the second capacitor-free floating body transistor memory cell. A method according to claim 14 or 15, characterized in that a positive voltage is applied to the gate terminal of the second capacitor-free floating body transistor memory cell when the low threshold state of the second capacitor-free floating body transistor memory cell is restored. The method of claim 14, characterized in that gate-induced drain leakage current (GIDL) is used to restore the low threshold state of the second capacitor-free floating body transistor memory cell. A method according to claim 15, characterized in that a negative voltage is applied to the gate terminal of the second capacitor-free floating body transistor memory cell when the low threshold state of the second capacitor-free floating body transistor memory cell is restored.

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