DE102006061648B4 - Transform coefficient block coding - Google Patents

Abstract

Apparatus for coding a block (34) of transform coefficients, wherein the transform coefficients are each represented by a plurality of magnitude bits (252), so that they define a sequence of magnitude bit-planes (38 ₁ ... 38 _n )
encoding means for sweeping the magnitude bits of a predetermined one of the magnitude bit planes (38 ₁ .... 38 _n ) and encoding predetermined ones of the magnitude bits into a coded data stream, the encoder comprising:
a buffer (106; 710);
a bit extractor (104; 712) for, upon passing through the magnitude bits, obtaining first status bits indicative of the transform coefficients represented by magnitude bits of the predetermined magnitude bit plane next in order at the earliest according to an order of traversal indicate the predetermined magnitude bit-plane from magnitude bits representing the same transform coefficients as the earliest next-rank magnitude bits but at more significant bit-planes than the same and filling the buffer with the determined first status bits; and
an encoder (112, 108 ₁ , 108 ₂ , 108 ₃ , 714) for encoding ...

Description

The The present invention relates to the coding of transform coefficient blocks, such as z. As an image, such as in the course of the digital Image compression method according to the JPEG2000 standard occurs.

The Steps of the JPEG2000 encoding process include optional splitting of the picture in so-called tiles or tiles, d. H. rectangular image areas, a DC signal level shift, an optional transformation the color components, the implementation a discrete wavelet transformation, a scalar quantization of wavelet coefficients, an array of quantized ones Wavelet coefficients in two-dimensional fields, so-called "code blocks", comprising a block coding a so-called "coefficient bit-modeling process" and a Arithmetic coding operation and arranging the coded code block data to a standard coding current. Described are the steps for example in Christopoulos et al .: The JPEG2000 Still Image Coding System: An Overview, IEEE Transactions to Consumer Electronics, Vol. 46, No. 4, pp. 1103-1127, November 2000.

Of the The most computationally intensive part among these steps is coefficient bit modeling. In this step, a code block in so-called magnitude or Amount bite levels decomposed in the order of the MSBs or the most significant bits to the least significant LSBs Bits are arranged, as well as associated sign bits, which are separate be handled or considered. Each amount bit level is in a sequence of three coding passes or coding runs modulated, except for the first bit plane, with only one coding pass is modulated. These coding passes pass through the bits of a Amount bit level in a specific order. It starts at the bit of the position top left, then three bits underneath, before jumping one column to the right. This is how you get started Stripe of the width of the code block and the Height of four coefficients. After a code block so in the horizontal direction was processed, becomes the next Stripe four coefficient positions processed deeper, etc.

ISO / IEC15444-1 describes closer, whether and which coding scheme during a coding pass is used. In particular, this will Decision taken by coefficient. In other words only certain coefficients are modulated during the first coding pass. Among the remaining coefficients encodes the second coding pass also a part. The rest is from the third coding pass modeled. Which coefficient belongs to which coding pass depends u. a. depending on whether the respective coefficient is significant or of the significance of its direct neighbors. ISO / IEC15444-1, below called the standard for short, defines a binary status variable for each Coefficients in a block of code, the so-called "significance status". Initially initialized to "insignificant", she changes to "significant" at the Amount bit level, at the first time a set bit of the coefficient modeling is and remains so until the end of the modeling of this code block set.

For a bit a coefficient that occurs during a Encoding run in a certain bit plane by a coding scheme is modeled, a data bit is generated together with a context index. This context index results primarily from the significance status variables of the coefficient and his neighbors. For certain coding runs, the first and the third, it follows that also the sign bit of the current coefficient modeling together with a context index, which in turn depends on the significance status variables and the sign of its neighbors. One so-called "amount refinement" - or MR coding scheme or the second coding pass additionally evaluates whether this scheme already at previous bit levels on the modeled Coefficient was applied, or for the first time. The downstream arithmetic coder expects the bit-context pairs in the the order described above.

follows one of the order in which the bit-context pairs of the arithmetic Encoder according to the standard are to be encoded, this results in a sequential sequence in Regards the coding passes, as described above and in particular is also complied with by software implementations. Through implementations in hardware a higher one Achieve coding speed. For example, several code blocks independently be encoded from one another simultaneously by using multiple block encoders be instantiated in parallel. However, this is an enormous Resource consumption, such. B. with regard to the required transistors on an integrated circuit or in terms of gate equivalents with a FPGA (Field Programmable Gate Array).

For example, in Lian et al .: Analysis and Architecture Design of Block Coding Engine for EBCOT in JPEG 2000, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 3, March 2003, pp. 219-230 a hardware design of the block coder described in JPEG2000, which saves on required checks per Coefficient in each pass, whether the respective coefficient belongs to the respective pass can be achieved by the membership checks are parallelized and, depending on the affiliation of no or one or more bits to the respective pass 4-er columns or groups of 4-er columns be skipped per pass. A hardware solution for the JPEG2000 block coder proposed in Gangadhar and Bhatia: FPGA based EBCOT Architecture for JPEG 2000, Field Programmable Technology (FPT), 2003, Proceedings 2003, IEE International Conference, pp. 228-233, goes one step further, according to which Runs are parallelized, so that fewer clock cycles for coding the code blocks are necessary. In this case, in addition to a memory for storing the magnitude bits and sign bits, a buffer is provided for buffering updated significance status variables between a first processing unit, which handles the first coding pass, and a second processing unit, which is responsible for the coding cycles 2 and 3.

It but remains desirable, a hardware-effectively implementable solution for encoding transform coefficient blocks find, as it happens, for example, in the JPEG2000 encoding.

In the US 2004/0228539 A1 there is described a bit-plane encoding sweep generator which performs a picture coding method comprising the steps of: dividing an input picture into sub-bands by means of a wavelet transform; Dividing each of the subbands generated at the wavelet transform step into code blocks each having a predetermined size; Generating a bit-plane comprising from a most significant bit to a least significant bit in units of the code block; Processing each of sample points in the bit plane based on any one of a plurality of encoding passes; and performing arithmetic coding according to results of the encoding sweep processing; in the coding pass processing, significance / non-significance information is read from a storage means indicating whether sample points are in a range which includes the position of a currently-processed sampling point and which is occupied by a predetermined number of samples, and those which exist around the area are significant or non-significant, and a parallel comparison is made between the significance / non-significance information and a plurality of preset matching patterns, thereby detecting a next sample point to be processed.

In the US 2002/0027516 A1 For example, a method of entropy coding symbols representative of a code block having transform coefficients of a digital image is described. The method includes a significance propagation sweep, an amount refinement sweep, and a sweep sweep for entropy coding the symbols. The method generates a first list of positions of those coefficients in the code block that have symbols that are to be entropy encoded during the significant bitplane significance traversal sweep, prior to the significant bitplane significance traversal sweep. The method also generates a second list of positions of those coefficients in the code block that have symbols that are to be entropy coded during the amount refinement sweep of the current bit plane before the current bit plane amount refinement pass. The method also generates a third list of positions of those coefficients in the code block that have symbols that are to be entropy coded during the cleaning pass of the current bit plane before the current bit plane is scanned.

In the US 2003/035476 A1 For example, a bit-plane processor reads out a code block serving as an arithmetic-coding unit from an SRAM. After converting the code block to the form of a bit-plane, the bit-plane processor supplies bit data to a sweep processor. The thread processor includes an s-pass processor, an r-pass processor, and a c-pass processor. Each of s-pass, r-pass and c-pass processes is performed in parallel in such a state that a start time thereof is shifted by an operation of two delay units by a predetermined unit time. For example, in JPEG200, special purpose subdividing units which divide / divide data into three respective passes of s-pass (significance pass), r-pass (refine pass), and c-pass (purge pass) and parallelize processing operations of these special-purpose subpart units. In this case, results of pass-through processing in a bit plane of a high order bit at the time of pass processing in a bit plane of a low-order bit are referred to. The preprocessing by the plurality of special purpose subdividing units may be performed in parallel while maintaining a time delay to an extent that a cross-reference necessary among the results of the preprocessing is performed. For example, this cross-reference may be a one-way reference, so that reference is made to a processing result of the s-pass in the r-pass processing and to a processing result of the r-pass in the c-pass processing becomes.

The US 2005/0094881 A1 describes an encoding device and a coding method in which input image information is encoded by: storing, in a storage device, state quantity information representing a predetermined state quantity to be used while being sequentially updated according to a processing state of the encoding process, if a predetermined one Coding process is performed on the image information; Performing the encoding process on the image information for each of the processing units by using the state quantity information corresponding thereto with a predetermined plurality of pixels as the processing unit, wherein the state quantity information having the plurality of pixels corresponding to the processing unit of the image information is stored as a word in the storage means; and wherein the state quantity information necessary for performing the encoding process on the image information of the processing unit is read out in units of the words from the storage means.

The The object of the present invention is a method and an apparatus for coding a block of transform coefficients, such as B. those of a picture, to create a more effective Enable implementation in hardware.

These The object is achieved by a device according to claim 1 and a method according to claim 29 solved.

An apparatus for coding a block of transform coefficients, wherein the transform coefficients are each represented by a plurality of magnitude bits defining a sequence of magnitude bit-planes, comprises coding means for sweeping the magnitude bits of a predetermined one of the magnitude bit-planes and encoding predetermined ones of the magnitude bits of the tuples into a coded one Data stream, wherein the coding means a buffer 106 ; a Bitextraktor 104 for, upon passing through the magnitude bits, determining first status bits indicative of significance for the predetermined magnitude bit-plane from the magnitude bits for the transform coefficients represented by magnitude bits of the predetermined magnitude bit-plane next in order according to an order of traversal at the earliest which represent the same transform coefficients as the earliest next-ranked magnitude bits, but at more significant bit-planes are the same and fill the cache with the first status bits detected; and an encoder for encoding the predetermined magnitude bits into the encoded data stream using the first status bits in the buffer.

A A realization of the present invention is that a more effective or more efficient implementation of the transform coefficient block coder allows when an encoder encodes the predetermined magnitude bits into the encoded data stream using status bits in one Caching, by a Bitextraktor on the Base of information filled which include magnitude bits having the same transform coefficients represent as at the earliest next numbered bits of magnitude, but in more significant bit-planes are the same.

On this way it is possible the significance information provided by the encoder, if appropriate needed to decide whether and, if so, which or which the magnitude bits of the predetermined magnitude bit plane to the predetermined ones Include amount bits, while of passing the magnitude bits only temporarily or locally in the Near the currently in line with the amount bits to store, thereby a bigger store to store the significance information is omitted. Thereby In turn, the memory requirement can be kept small, so that conversely, a more complex but conversely faster storage technology can be used to store these status bits. Despite one only temporary Storing the status information in the cache can an update of the content with which the Cache filled is to use this updated content during encoding. The additional Effort for the logic to the permanent Extraction of status information instead of storage and Restore over all bit levels are relatively low across from the saving of storage costs. In addition, the extraction means no temporal loss, because the extraction is temporally parallel to the actual encoding be performed can.

Further embodiments The present invention will be described below with reference to FIG the figures closer explained. Show it:

1 a block diagram of an image compressor, in which the transformation coefficient block coding according to the invention can be applied;

2 a schematic representation of a division of the transformation coefficients in magnitude bits and sign bits;

3 a block diagram of a block encoder according to an embodiment of the present invention;

4 a block diagram of the bit modeling unit of the coding pass 1 (Pass 1) 3 according to an embodiment of the present invention;

5 a block diagram of the bit modeling unit for the coding pass 2 (Pass 2) 3 according to an embodiment of the present invention;

6 a block diagram of the bit modeling unit for the coding pass 3 (Pass 3) 3 according to an embodiment of the present invention;

7 a block diagram of the pass or decoder of 3 according to an embodiment of the present invention;

8th a schematic representation for illustrating the size of the shift register unit of 3 and the content stored therein at a particular time; and

9 a block diagram of a block encoder according to another embodiment of the present invention.

1 shows an image compressor 10 as an example of an application in which the embodiments described below can be used advantageously. The image compressor 10 from 1 is designed to be a source image 12 consisting of, for example, arranged in columns and rows samples or pixel values in a coded data stream or code stream 14 to compress. This includes the compressor 10 from 1 For example, a series connection of optionally a tile divider 16 , a DC level shifter 18 , optionally a color transformer 20 , a transformer 22 for spatial spectral decomposition, an optional quantizer 24 , a block coder or block coder 26 and a data folder 28 , The tile divider splits the picture 12 in, for example, rectangular image areas, so-called tiles or tiles. The further processing is carried out per tile or tile, so that the further compression in the individual tiles takes place independently of each other. The DC level shifter 18 performs within each tile a uniform across all pixels of the corresponding tile DC offset, so that, for example, after the mean of the pixel values, such. B. the luminance values, zero. The color transformer 20 optionally performs a color transformation on the pixel values, the color transformation being optional and of course only in the case of color images 12 takes place. Thereupon the transformer leads 22 a spatial spectral decomposition per tile through. In the case of a JPEG2000 code stream to be generated 14 For example, the transformation is, for example, a wavelet transform, more specifically, a discrete wavelet transform that is applied to each tile one at a time. In this way, each tile is decomposed into different resolution levels consisting of subbands of transform coefficients describing frequency characteristics of local areas of each tile. The transform coefficients can already be integers. The quantizer 24 optionally translates the transform coefficients to scalar quantization and merges them into code blocks, ie, for example, rectangular arrays of transform coefficients. The block encoder 26 The transform coefficients in the code blocks are entropy-coded bit by bit into data streams, whereupon the data arbiter 28 the arithmetic coded codeblock data streams still suitably order the code stream 14 to form, such. B. a JPEG2000-compliant code stream.

The block encoder 26 In particular, as in 1 is shown a coefficient bit modeler 30 with a downstream arithmetic coder 31 on. The coefficient bit modeler 30 assigns to the magnitude bits of the coefficients contexts assigned by the arithmetic coder 32 be used for arithmetic coding. In particular, the arithmetic coder 32 a contextual binary arithmetic coder adapted to divide a current interval representing the current state of the arithmetic coder into two halves depending on estimated probabilities for occurrence of each bit value for the next bit to be encoded, and among these halves one to limit the current interval to this interval depending on how the actual bit value of the current bit to be coded is, the estimated probabilities being different for each context, and the context by the coefficient bit modeler 30 is determined depending on adjacent significances and / or magnitude bit values and a plurality of possible contexts. The encoder may also adaptively adapt the pre-initialized estimates during encoding to the actual probabilities per context.

The following explanation of exemplary embodiments of the present invention initially concentrates on a JPEG2000-compliant compression, for which reason the object of the block coder in the following is this background 26 will be illustrated in more detail. In particular are from the block encoder 26 the individual magnitude bits of the transform coefficients in a block in a predetermined order into the arithmetic-coded data stream of the arithmetic coder 32 in particular first bitwise from the most significant bitplane to the least significant bitplane and within those bitplanes by scanning the coefficient magnitude bits in three passes in a fixed scan order, encoding in each pass only magnitude bits that meet certain criteria such that three passes from the arithmetic coded data stream all magnitude bits are reconstructed. To illustrate the split in bit planes and the scan order within those planes, shows 2 exemplarily a code block of size 3 × 8.

In particular shows 2 at 34 exemplarily a 3 × 8 code block with 3 × 8 transformation coefficients a to x. As by the arrow 36 is indicated, each coefficient a to x by n amount bits a ₁ ... n, ..., x ₁ ... x _n and a respective sign bit a _vz , ..., x _vz represented, wherein the splitting 36 in magnitude bits and sign bits, for example inherently from the type of discrete wavelet transform 22 or from quantization 24 ( 1 ). The MSBs or significant magnitude bits are, for example, the bits a ₁ ... X ₁ and form a first magnitude bit level 38 ₁ , Likewise, the other magnitude bits can be assigned to corresponding bit planes 38 ₂ ... 38 _n sum up. Every bit level 38 ₁ ... 38 _n as well as the sign bits 40 So each form a 3 × 8 bit array.

The aforementioned scan order now provides that the bits of a bit plane 38 ₁ ... 38 _n in four columns or tuples of four column bits adjacent magnitude bits from one line end to the other, ie, stripwise, whereupon the next strip is scanned in the next lines, and within each four column vector or each tuple the magnitude bits from the top be scanned down. For the bit levels 38 ₁ ... 38 _n Thus, the scan pattern can be displayed as
a _i, b _i, c _i, d _i, i _i, j _i, k _i, l _i, q _i, r _i, s _i, t _i, e _i, f _i, g _i, h _i, m _i , n _i , o _i , p _i , u _i , v _i , w _i , x _i , where i = 1 ... n,
this scan pattern here exemplarily comprises six quadruplets or tuples and two stripes.

A triple scan of the magnitude bits of the individual bit planes will now be according to the embodiment described below for a block coder 26 This is avoided by the fact that the amount bits associated with the respective passes are detected by means of a scan and encoded into data words, from which the bit values and the associated contexts result, whereupon the same are cached in a buffer in an appropriate sequence in an arithmetically coded data stream. In this case, a constant lookup in a memory is avoided by the magnitude bits and sign bits are cached.

3 shows a block encoder 100 according to an embodiment of the present invention. It comprises a storage unit 102 , a bitextractor 104 , a shift register unit 106 , a coefficient bit modeler stage 108 , a cache 110 and an arithmetic coding device 112 , The storage unit 102 For example, is a random access memory such. As a RAM, and acts as an interface for obtaining the quantized signed transformation coefficients of the code blocks to be coded, such. B. the code block 34 from 2 , The Bitextraktor 104 is with the store 102 coupled to the memory contents of the memory unit 102 Views 114 to be able to perform from the storage unit 102 To read magnitude bits and sign bits. When and on what magnitude bits and / or sign bits of the bitextractor 104 will be described in more detail below. Anyway, the Bitextraktor 104 responsible for this, the shift register unit 106 based on the information read from the storage unit 102 to fill with bits from the coefficient bit modeling stage 108 needed to make the necessary contexts or the necessary precoding. More specifically, the Bitextraktor scans 104 In a manner which will be described in more detail below, the amount bit-plane for the amount-bit-plane is the amount bits of the current amount bit-plane along the prescribed strips and fills the shift register unit 106 during the scanning process with information continuously, so that the shift register unit 106 due to its shift register length, comprises information bits relating to a current portion of the current magnitude bit plane along the stripes comprising the coefficient bit modeling stage 108 currently needed for their context creation or precoding. In anticipation of the later more detailed description forms the Bitextraktor 104 for example, from the coefficient amount bits and the sign bits by mere assumption the amount of bits to be newly recorded 108 the current bit-plane, by mere assumption the new sign bits to be recorded 118 and by appropriate combining associated status bits 120 and feeds it to the shift register unit 106 too, which is sized to fit the individual bits 108 . 110 . 112 at a depth of a respective suitable number of shift stages, as will be described in more detail below. Neighbor bits located at the edge of the code block are padded with zeros, as shown in FIG 3 is shown as an example for the upper neighbor bits.

Simplifying is in 3 shown, the shift register 106 see four registers each (shaded) together with each 14 neighbor registers, each for the coefficient bits 108 , Sign bits 118 and status bits 120 , The shift register unit 106 can thus be used as multiple shift registers 106 _1,2,3,4 each one for the magnitude bits, sign bits and two different status bits which will be described in more detail below, these individual shift registers 106 _{1 ... 4} synchronized with each other, so that each shift pulse at the same time by one horizontal position or by a shift register rank, ie by a 6-he vector in 3 to be pushed further.

Internally, the coefficient bit modeling stage decomposes 108 into several bit-modeling units 108 ₁ , 108 ₂ and ₃ of which the first is responsible for pass 1 or pass 1, the second pass 2 or pass 2 and the third pass 3 or pass 3, and which will be described in more detail below. The individual units 108 ₁ - ₃ are each shift registers with respective bit registers 106 ₁ - 106 ₄ coupled to analyze the corresponding register contents and for each bit to be modeled from a current tuple of magnitude bits stored in

3 the hatched registers correspond to determine whether or not to model according to the respective pass or pass, and if so, with what result. The bit modeling units 108 ₁ - ₃ are in particular designed to generate, per tuple or per amount bit belonging to the respective pass, a correspondingly precoded data word including control bits explained in more detail below and in respective latches 110 ₁ . 110 ₂ and 110 ₃ the cache stage 110 store. Data words belonging to tuples in which there is no magnitude bit associated with the respective pass can be discarded, as will be described below, as well as data words for magnitude bits not associated with the respective pass.

The bit modeling units 108 ₁ - ₃ In particular, they can be designed to set control bits in the data words that are generated by the subsequent arithmetic coding device 112 can be used to put in the cache 110 ₁ - 110 ₃ stored data words or the magnitude bits encoded in the same in the appropriate order and using the correct context or subjecting the arithmetic coding in another mode, such. As a plain text mode to insert into the data stream, as will be discussed in more detail below. For this purpose, the arithmetic coding device 112 in particular a continuous decision maker 122 on which an arithmetic coder 124 is downstream. The pass decision maker 122 acts as encoder of the precoded data words in the latches 110 ₁ - 110 ₃ and is coupled with the latter. The pass decision maker reconstructs from these data words 122 contextualized bits with context associated with each of runs 1, 2 and 3 and pass 1, pass 2 and pass 3, respectively, and passes these pairs to the arithmetic coder in the appropriate order, ie pass 1 followed by pass 2 followed by pass 3 124 in addition to the bit values and the associated context indices, the forwarded information also contains information about the arithmetic coder 124 may include coding modes to be used or the like, wherein the control signals from the decision maker 122 to the arithmetic coder 124 in 3 generally with 126 are displayed. In other words, the passport decoder encodes 122 the read data words in the buffers 110 back to bit-context pairs 126 and leads this to the downstream arithmetic coder 124 in a prescribed manner and appropriate representation.

The above has been roughly the structure of the block coder 100 from 3 described and the tasks and functionalities of the individual units roughly sketched. Before proceeding with the detailed description of the bit modeling units 108 ₁ - ₃ and the passport-decision maker 122 and based thereon a detailed description of the operation of the block encoder 100 In the following, the general aim of the interaction of the units of 3 to give an overview which may be helpful in understanding the following detailed description. As already mentioned, the bitextractor ensures 104 for filling the shift register unit 106 , The Bitextraktor 104 scans the current amount bitmap in strips. As a first approximation one can therefore use the shift register unit 106 as a window moving across the current amount bit plane along the scan order, with synchronous movement of a corresponding window in the sign bit plane 40 ( 2 ) and caching associated status bits for these window contents. The bit modeling units 108 ₁ - ₃ require no further information than those in the shift register unit for their work 106 That's why lengthy memory accesses 114 on the storage unit 102 are not necessary. In addition, only one pass through the current amount bit plane is necessary, although the standard, as discussed above, defines three passes for determining the order in which the magnitude bits are to be encoded into the data stream. To achieve the latter, each of the bit-modeling units takes care of it 108 ₁ - ₃ only to those Amount bits in the quad tuples belonging to the respective own pass. Generally speaking, passport 1 takes care of magnitude bits of transform coefficients that are not yet significant, ie whose magnitude bits in the more significant magnitude bit-planes are zero or non-significant, but adjacent to transform coefficients that are significant. To eliminate confusion, it is noted that a transform coefficient in a particular magnitude bit-plane is said to be significant if at least one of the magnitude bits in the more significant magnitude bit-planes is 1 and becomes "significant" in a particular magnitude bit-plane if none of the magnitude bits are in the more significant However, during the coding of the current bit level, it is still significant in this level by means of an amount bit of 1. An amount bit is said to be significant if it is 1. Pass 2 takes care of transformation coefficients, which are already significant in the current amount bitmap. The pass 3 finally addresses the remaining magnitude bits, ie the magnitude bits of transform coefficients which are non-significant and did not fall into pass 1.

The significances of the transform coefficients in the magnitude bit-plane currently to be coded play in the modeling of the bit-modeling units 108 ₁ - ₃ is carried out, a major role, since the contexts are determined from this and this information is already present at the decoder during decoding and thus he can emulate the context modeling. It should already be noted that the decision as to whether a particular amount bit belongs to the pass 3 sometimes depends on whether one of the neighbor amount bits, although in logical sequence before pass 1, belongs to a non-significant transform coefficient but belongs to the pass 1 and Thus, if necessary, virtually or according to the order defined in the standard, after which the runs are performed sequentially, even before the end of the pass 1 is significant, in which case the appropriate amount bit may not belong to the passport 3, but the passport 1. Das However, of course, the problem of signing neighbor amount bits concerns only those neighborhood amount bits that are ahead of the currently considered magnitude bit according to the magnitude bit scan order.

The bit modeling units 108 ₁ - ₃ fill their respective cache 110 ₁ - 110 ₃ with consecutive data words, in turn, from the passport decision maker 122 be read out, namely amount bitwise way, so with the cache 110 ₁ beginning until the last data word of the current amount bit plane has been read, then proceeding with the buffer 110 ₂ until the last data word has been read from the current amount bit level, again followed by the buffer 110 ₃ until the last data word has been read there, exceptionally in the first or most significant amount bit level equal to the buffer 110 ₃ is started because there is no transformation coefficient is significant, and thus no amount bit of this level can belong to another passport than pass 3. The data words are in the pass decision maker 122 also decoded and into corresponding control signals for the arithmetic coder 124 converted, which forms a coded data stream for the code block.

In the following, the internal structure of the bit-modeling units and the pass-decision maker of 3 described in more detail. 4 shows the structure of the bit modeling unit 108 ₁ , It is responsible for pass 1, ie for the first coding pass, also referred to as "significance propagation pass", because it relates to magnitude bits of transform coefficients which are in the vicinity of already significant transform coefficients and thus are likely to become significantly more significant than those transformation coefficients farther from already significant ones. As mentioned above, the decision as to whether to model a corresponding magnitude bit in the pass 1 pass is based on whether the corresponding coefficient for the current bit-plane is still insignificant and at least one of its direct neighbor coefficients is significant or significant in the course of the first pass becomes.

The bit modeling unit 108 ₁ has an analysis prediction unit 200 a magnitude bit pre-encoding unit 202 , the latter input side upstream multiplexer 204 . 206 , a sign bit precoding unit 208 , the latter input side upstream multiplexer 210 . 212 , an update demultiplexer 214 , a valid bit multiplexer 216 , a four-bit register 218 , a clock counter 220 , a coefficient selector 222 and a control bit control 224 on, in 4 for easier understanding even the cache 110 ₁ and the shift register unit 106 are shown.

The analysis predictor 200 is intended to advance, ie in anticipation of pushing the next tuple to be processed into the part of the shift register 106 at which the bit modeling unit 108 ₁ the tuple to be processed expects which spot in 4 are shown with hatching to determine which of these magnitude bits belong to pass 1. The analysis / prediction unit 200 For example, this decision is made whenever the shift register unit 106 through the bit extractor 104 ( 3 ) is refilled, ie at each shift pulse. In 4 meets the analysis prediction unit 200 For example, the decision on membership or non-membership of the magnitude bits of the 4-er vector q _m , r _m , s _m , t _m , the next shift in the register unit 106 to the current tuple or to the hatched register area, where currently the magnitude bits i _m , j _m , k _m and l _{m are} located. To make the prediction, the analysis / prediction unit is 200 with register cells of the register unit 106 coupled, with the part 106 ₂ that affects the magnitude bits, as with an arrow 226 is implied, and the part 106 ₃ that affects the first status bits, as with an arrow 228 is indicated, wherein the first status bits indicate the significance of corresponding coefficients with respect to the current bit plane, as will be discussed in more detail below.

To an output of the analysis / prediction unit 200 closes the register 218 to from the analysis / prediction unit 200 to obtain the result of the prediction in the form of a 4-bit vector having per magnitude bit of the next current tuple by a corresponding bit i _ae , j _ae , k _ae and l _ae indicating whether the respective magnitude bit q _m , r _m, s _m, t _m or hereinafter shift cycle by the Bitmodelliereinheit 108 ₁ to process or not.

Both an input of the multiplexer 216 as well as an input of the coefficient selector 222 are with the register 218 coupled. The coefficient selector 222 is designed to be based on the register contents of the register 218 to select the amount bits of the pass 1 to be modeled or prescoded and this selection in the form of a multiplexer control signal to the multiplexer 210 . 212 . 204 . 206 and 216 or the demultiplexer 214 tell. The analysis / prediction unit 200 Further, there is a prediction about the number of magnitude bits associated with pass 1 in the next in-line tuple, to the clock counter 220 in this way at the beginning of each shift cycle or after a shift operation in the shift register 106 is preinitialized to a value corresponding to the number of magnitude bits associated with the pass 1 in the current magnitude bitmap. The clock counter 220 For example, then it decrements its counter content based on a processing clock the same from the coefficient selector 222 receives, in the processing clock, the multiplexer signal sequentially to the amount associated with the pass 1 magnitude bits, as in the register 218 are displayed.

The multiplexer 216 is configured to be dependent on the multiplexer signal from the coefficient selector 222 the bit indicated by the multiplexer signal from the register 218 as a valid bit or valid bit to its cache 110 ₁ issue. The multiplexer 204 is the input side with special register cells or register locations of the shift register unit from the part 106 ₂ for the magnitude bits, and is configured to be dependent on the multiplexer control signal from the coefficient selector 222 a bit bit register cell storing the bit indicated by the multiplexer signal, having an input of the magnitude bit precoding unit 202 and optionally an input of the sign bit precoding unit 208 to couple by a corresponding one of the inputs of the multiplexer 204 to a corresponding output of the multiplexer 204 to be led. The same applies to the multiplexer 210 . 212 and 206 , The multiplexer 210 For example, the input side with special sign bit cells from the part 106 ₁ the shift register unit 106 coupled and configured to, depending on the multiplexer signal, a corresponding subset of these register contents or sign bits via the output of the multiplexer 210 to another input of the sign bit precoding unit 208 issue. Similarly, the multiplexer 212 between special register cells from the part 106 ₃ for the first status bits of the shift register unit 106 and another input of the sign bit precoding unit 208 and the multiplexer 206 between special register cells in the part 106 ₃ the shift register unit 106 and another input of the magnitude bit pre-encoding unit 202 switched to output a part of the first status bits of these special register cells to the respective unit, depending on the multiplexer signal.

The incoming signals are from the precoding units 208 and 202 used to each a pair of data bits 230 respectively. 232 and context index consisting of 2 bits 234 respectively. 236 where the data bit indicates the bit value of the sign bit or the magnitude bit of the transform coefficient currently being processed by the multiplexer signal, while the context index points to the associated context to be used respectively.

As it is in 4 through an arrow 238 is displayed, it may be provided that the sign bit precoding 208 additionally with your coding or context formation a bypass mode bit 240 used by the control bit control 224 next to a pass-end bit 242 is issued. The meaning of these control bits 240 and 242 will be discussed in more detail below. The bits 230 . 242 together form a 12-bit word 244 that in the cache 110 ₁ is entered. The cache 110 ₁ can be designed to only data words 244 to cache in which the simultaneously arriving validity bit 246 that from the multiplexer 216 is output, indicating that the current multiplexer signal pointed to an amount bit associated with the pass 1.

As it is in 4 It will also be seen that this is done by the magnitude bit pre-encoding unit 202 output data bit 232 to an input of the demultiplexer 214 fed back. The latter is the output side with register cells from the area 106 ₃ coupled, namely the one containing the first status bits for the current magnitude bits (shown hatched), depending on the multiplexer signal, the data bit 232 to use for updating the first status bit associated with the magnitude bit currently being generated by the magnitude bit precoding unit 202 has been modeled. In this way, namely, the significance of the corresponding coefficient is updated.

The preceding description was only roughly related to the construction and single-function manner of the components of the bit-modeling unit 108 ₁ one. In the following, therefore, the interaction of the individual components of the Bitmodelliereinheit 108 ₁ in interaction with the shift register unit 106 the cache 110 ₁ as well as the Bitextraktor 104 with simultaneous reference to 8th and 3 be explained in more detail. 8th symbolizes a section of the storage unit 102 ( 3 ) namely a section of the magnitude bits and sign bits of the transformation coefficients of a code block currently to be coded. In particular, the individual sign bits and magnitude bits are cubes 250 respectively. 252 symbolizes. In particular, the sign bits 250 shown juxtaposed in rows and columns, corresponding to the corresponding transform coefficients in the code block to be coded. Only a section of the sign bits 250 is shown, a section of sign bits 250 in a current strip 254 plus the adjacent lines 256 respectively. 258 the strip above and below it. Also the amount bits 252 the current bit plane are shown as juxtaposed in rows and columns, wherein also only a part or section of the current bit plane is shown, which corresponds to the part of the sign bit plane, ie a part of a corresponding strip 260 with the amount bits 252 the line above and below 262 and 264 , For the sake of completeness, it is pointed out that magnitude and sign bits aligned in the vertical direction are arranged in lines corresponding to one another among the lines 254 - 264 in 8th should belong to the same transformation coefficients.

The magnitude bits of less significant bit-planes than the current bit-plane are in 8th not shown. Signi fikantere and thus already encoded magnitude bits of the more significant bit planes are, however, in 8th recognizable and are behind the current bit level in turn.

As already described above, the bitextractor fills 104 every time the shift register unit slides 106 by means of memory accesses 114 ( 2 ) the latter again with sign bits 250 or amount bits 252 from the storage unit 102 . 3 , so in the shift register 106 always a section of the sign bit plane or the current amount bit plane is always located. These cutouts are in 8th at 266 and 268 highlighted. As can be seen, is located at a given time in the part 106 ₁ the shift register unit is a section of the sign bit array of five consecutive columns and six superimposed lines, namely the four lines of the current strip 254 and the neighboring lines 256 and 258 , In a similar way is located in the part 106 ₂ the shift register 106 at any time a section of the current magnitude bit-plane of four columns length of six lines each 260 - 264 ,

As it is in 8th it can be seen, are the cutouts 266 and 268 the one in the lines 106 ₁ and 106 ₂ the shift register unit 106 stored sign bits 250 or amount bits 252 aligned such that to a transformation coefficient, for the momentary magnitude bits 252 in the part 106 ₂ is cached, including the corresponding sign bit 250 the respective transformation coefficient in the part 106 ₁ is cached. In particular, a register cell is provided in the shift register unit for each bit to be stored, which in 8th also as through the cubes in the corresponding sections 266 and 268 can be regarded as symbolized. The register cells of the parts 106 ₁ and 106 ₂ are interconnected in such a way that the register contents in 8th be shifted from right to left ver, so that each shift a column of sign bits 250 or amount bits 252 the shift register unit 106 on the one hand, in 8th namely left, leaves, and at the other end of the shift register the corresponding parts 106 ₁ and 106 ₂ with a next column 270 respectively. 272 of sign bits 250 or amount bits 252 be filled. In 8th this corresponds to a shift of the cached portion 266 respectively. 268 in the sign bit plane or amount bit plane per shift virtually by one column to the right. The Bitextraktor 104 is now designed such that it is the filling of the part 106 ₁ and 106 ₂ with sign bits 250 or amount bits 252 which relates to a column of transform coefficients associated with each other, so that the offset between the contents of the sign bit part 106 ₁ and the momentary Content of amount bit content 106 ₂ the shift register unit 106 at the rear shift register end, where sign bits in the part 106 ₁ are cached that leave this part at the next shift, and no more magnitude bits in the part 106 ₂ are cached.

As already mentioned above, the bit modeling units require 108 ₁ and 108 ₂ for their processing also status bits, namely first and second status bits. The first status bits each indicate, for a transform coefficient, whether or not it is significant with respect to the current magnitude bit-plane. Again, it should be noted that the state of significance of the current magnitude bit-plane for a transform coefficient may change after-or during-virtual-first pass. The part 106 ₃ the shift register unit 106 is now dimensioned to be for six consecutive columns of transform coefficients in the rows 260 - 264 corresponding lines each have a status bit 274 stores in 8th are also shown as cubes. In particular, the shift register unit stores 106 in the part 106 ₃ first status bits at any time 274 for transform coefficients of six adjacent six-row columns, five of which contain the first status bits of transform coefficients, including the sign bits 250 in the clipping 266 of the part 106 ₁ are included. In addition, first status bits for transform coefficients are contained in a 6-column of transform coefficients, with their sign bits 250 or amount bits of the current bit plane the parts 106 ₁ and 106 ₂ the shift register unit 106 be filled only at the next shift.

In the presentation of 8th can also do the dice 274 at the same time be regarded as the corresponding register cells interconnected to shift their contents column by column, in 8th also from right to left in the same bar as the other parts 106 ₁ and 106 ₂ , The filling also takes over the Bitextraktor 104 by bit combination, such. A logical OR between bits arranged in a significant direction on the basis of the magnitude bits emphasized by hatching 276 in the more significant amount bit-planes than the current magnitude-bit-plane for transform coefficients that appear at the positions of the column 272 with their magnitude bits of the current bit plane, the register cells at the front end of the part 106 ₂ the shift register unit 106 be filled only at the next shift pulse. The filling process, which is among the most recent entries in the first status bit part 106 ₃ has been in is 8th with the arrow 278 indicated.

Finally, also in the shift register 106 a part 106 ₄ provided in the second status bits are stored, whose meaning and relevance will become apparent from the following description. Anyhow, the part saves 106 ₄ the second status bits for transform coefficients of only one column in only four lines corresponding to the lines of the strip 260 respectively. 254 correspond, wherein the second status bits are also symbolized as cubes, denoted by the reference numeral 280 are displayed. Every time you shift in the shift register unit 106 become the second status bits 280 updated such that they are always defined for the transform coefficients, their magnitude bits in the output-side column in the stripe 260 are cached to the next shift from the part 106 ₂ the shift register unit 106 to be displaced. The bit extractor 104 updates the second status bits 280 with each shift of the shift registers 106 hatched bits of magnitude highlighted 282 in more significant magnitude bit-planes than the current magnitude bit-plane for the just-mentioned transform coefficients in the strip 260 by the bitextractor 104 for each transform coefficient, check the corresponding magnitude bits for at least two of these magnitude bits to be one or significant.

Returning to 4 is now the analysis / prediction unit 200 so with the parts 106 ₂ and 106 ₃ the shift register unit 106 coupled to predict the magnitude membership of the next magnitude bit tuple to be modeled, the contents of the register cells of the part 106 ₂ and the first status bits in those register cells of the part 106 ₃ the shift register unit 106 receives, indicated by dashed lines and by the reference numeral 282 respectively. 284 are provided. To illustrate this a little closer, in the following specifically addressed register cells or bits in the parts 106 ₁ - 106 ₄ each with an index pair #, # coded in the column number and line number starting from the top left corner indicates the register cell or bit position. That's how the area spans 282 for example, the range of the range of magnitude bits 252 _3.2 to 252 _4.5 on and the area 284 the range of bits 274 _4.1 to 274 _6.6 , The analysis / prediction unit 200 now uses the information supplied to it to determine the affiliation of the magnitude bits at the positions 252 _4.2 to 252 _4.5 to predict to the first pass which magnitude bits form the next-ranked tuple that, at least in the case that among the magnitude bits is one associated with pass 1, from the precode units 202 . 208 is processed.

The amount bits in the range 282 uses the analysis / prediction unit 200 to capture to be aware that not all status bits are in the second area 284 are updated as they will be in the case of decoding in the decoder at the same location in the decoding of the passport 1. In addition, the analysis / prediction unit uses 200 to their prediction the last forecast result that they sent to the registers 218 and in the shift register storage state of 8th the transform coefficient positions that are in the part 106 ₃ with the dash-dot-dot line 286 are marked, which also simultaneously mark the transformation coefficient positions which correspond to the tuple currently to be modeled. For example, the analysis / prediction unit 200 a not-yet-updated first status bit 274 _4.2 dependent on ANDing the bit i _{ae of} the last prediction result with the magnitude bit 252 _3.2 take into account the result of this AND operation with the first status bit 274 _4.2 ORed.

For the first status bit 274 _5.2 can be the analysis / prediction unit 200 address the not-yet-updated by being the result of ORing the eight immediate neighbor bits 274 with the above-described update compensation for the status bits 274 _4.2 and 274 _4.3 with the amount bit 252 _4.2 ANDed. With such virtually updated first control bits, the analysis / prediction unit 200 the affiliation of, for example, the amount bit 252 _4.3 by an OR operation of the eight first control bits of the eight direct neigh neighboring coefficients, followed by an AND operation with the inverse or the negation of the status bit 274 _5.3 determine. Thus, the analysis / prediction unit checks in this way 202 for each of the magnitude bits to be modeled 252 _4.2 , to 252 _4.5 whether the corresponding transformation coefficients that they represent are still insignificant, as well as whether the direct neighboring coefficients are already significant or at least one of them is already significant, already a column in front of the column currently to be modeled 252 _3.2 to 252 _3.5 and taking into account the significances, such as they are in proper passage of the passport 1 to the respective amount bit in 252 _3.2 to 252 _3.5 would have resulted.

The analysis result is then from the unit 200 as previously described, as a 4-bit vector to the register 218 is issued after the next shift operation of the shift register unit 106 at the input of the multiplexer 216 or the coefficient selector 222 to rest. With just one additional arithmetic adding operation among the bit values, the same to the registers 218 can output the analysis / prediction unit 200 also deliver the prediction result and to the bit counter 220 before starting the next shift into the shift register unit 106 which indicates how many of the magnitude bits in the next tuple to be modeled belong to pass 1. Shows the register 218 that none of the magnitude bits of the current tuple 252 _3.2 to 252 _3.5 belongs to the passport 1, so sets the coefficient selector 222 the multiplexer signal as desired, such. To a predetermined value that is not from the register contents of the register 218 depends, causing the multiplexer 216 one of the unset bits in the register 218 as valid bit 246 to the cache 210 ₁ outputs. So even if the precoding units 202 . 208 and the control bit control 224 together a 12-bit word 244 form and to the cache 110 ₁ spend, so takes the cache 110 ₁ For example, the caching of this data word 244 not available because the validity bit is not set. However, to save power, it may be provided that, for example, the operation of the precoding units 202 . 208 is prevented in such a case, as exemplified by an arrow 288 in 4 is indicated. Of course, it would also be possible for the cache to work 110 ₁ the storage of data words 244 regardless of whether the validity bit is set or not, in which case the cache 110 ₁ the valid bit is simply cached along with the 12-bit word, but this approach takes up more space in the cache 110 ₁ required.

Otherwise, however, ie in the case of at least one set bit in the register 218 indicating that the corresponding magnitude bit is below the magnitude bits currently to be modeled 252 _3.2 to 252 _3.5 belongs to Pass 1, sets the coefficient selector in successive cycles 222 the multiplexer signal sequentially down corresponding to the set bits in the register 218 to the coefficients belonging to Pass 1. In the processing clock then generate the control bit control 224 and the precoding units 202 and 208 for each of these pass bits belonging to the 1 a 12-bit data word 244 , which together with a set validity bit 246 to the cache 110 ₁ is output, which stores these data words in the incoming order due to the valid bit set. In particular, the coefficient selector goes 222 the amount bits associated with pass 1 within the column 252 _3.2 to 252 _3.5 from top to bottom as it also expects according to the scanning order of the decoder.

In each processing cycle, the precoding units process 202 and 208 the information available to them according to a respective coding scheme, the data bits 230 respectively. 232 and the associated context indexes 234 and 236 to determine. The precoding unit 202 performs a so-called significance propagation or SP coding scheme. After that, the context index 236 formed by logically linking the significances of the neighbor coefficients. Thus, for example, shows the current multiplexer signal on the amount bit 252 _3.3 so does the multiplexer 206 the first status bits 274 _3.2 to 274 _5.2 . 274 _3.4 to 274 _5.4 . 274 _3.3 and 274 _5.3 further. Overall, therefore, the input side of the multiplexer 206 coupled to the register cells by the dashed line 290 in 8th are surrounded. The multiplexer 204 is input side with the register positions in the area 106 ₂ coupled, which corresponds to the currently modeled tuple and with a dashed line 292 is marked. The multiplexer 204 indicates the magnitude bit value indicated by the multiplexer signal to the precode unit 202 off, so that this is the data bit 232 can adjust accordingly.

The sign bit precoding unit 208 can, as it is in 4 through the dashed connecting line 294 is also displayed, the amount bit value of the magnitude bits indicated by the multiplexer signal is received to inhibit or perform processing depending thereon. On the decoder side, the decoder expects an encoding of the sign bit of a transformation coefficient anyway only if it becomes significant the first time, namely immediately after receipt of the corresponding data bit of this magnitude coefficient, so that in this case in the data word 244 the corresponding bits 230 and 234 are irrelevant. The by the unit 208 output data bits and context indices 230 . 234 in other words, they are only relevant if the data bit 232 by the amount pre-encoding unit 202 is issued, is significant or set. The connection 294 between the output of the multiplexer 204 and the precoding unit 208 However, it can also be missing, in which case the values that the data bit 230 or the context index 234 assume, for the subsequent revision, however, is irrelevant.

In any case, the sign bit precoding unit performs 208 a so-called sign coding or SC (SC = sign coding) scheme, after which the data bit 230 the value of the sign to the transform coefficient indicated by the multiplexer signal and the associated context index 234 is set to a context which depends on a logical combination of the significances and signs of the neighboring coefficients, according to the JPEG2000 standard, which is hereby addressed by way of example, only the neighboring coefficients in column and row direction. For example, shows the multiplexer signal on the magnitude bit 252 _3.3 , so determines the Vorkodiereinheit 208 the data bit 230 from the sign bit 250 _4.3 and the sign bits adjacent thereto 250 _3.3 . 250 _5.3 . 250 _4.2 and 250 _4.4 taking into account that not all sign bits are yet known for the decoder, which is taken into account here by evaluating the first control bits of the neighboring bits, namely 274 _3.3 and 274 _4.2 , Accordingly, the multiplexer 210 input side with register cells within the dashed line 294 coupled area while the multiplexer 212 on the input side with part of the register cells within the range 290 is coupled to each a part of these register cells depending on the multiplexer signal from the coefficient selector 222 with the sign bit precoding unit 208 to pair.

The control bit control 224 sets in each processing cycle of the precoding units 202 and 208 the control bits 240 and 242 representing the subsequent arithmetic coding device 112 ( 3 ) should inform, for example, whether the bypass mode for the respective transformation coefficient of the data word 244 should be active, and whether the current coding pass is over. More specifically, the control bit control sets 224 the pass-end bit 242 in the case that the current tuple to be modeled includes the last magnitude bits in the current magnitude bit-plane, e.g. B. the magnitude bits u _i , v _i , w _i and x _i in the current bit plane i in the example of 2 , The bypass mode bit 240 provides the control bit control 224 For example, depending on the depth of the current magnitude bit plane, so that, for example, after the fourth coded bit plane, the bit 240 indicates the bypass mode, indicating that from this point on the pass-1 data is raw or uncompressed into the data stream at the output of the arithmetic encoder 112 should be introduced.

Finally, it should be noted that the cache 110 ₁ in the case that he is trained to data words 244 depending on the validity bit 246 temporarily store or discard, in particular, is designed so that the cache 210 ₁ the data word 244 in the case of a set pass-end bit 242 but also cached if the corresponding valid bit 246 not set. Various measures can be provided in this case for the data word to be the actual unactivated validity bit 246 reflects, such as B. coding the remainder of the data word 244 except for the pass-end bit for an otherwise invalid state, since Pass 1 associated with the magnitude bit does not occur.

As already mentioned, the clock counter becomes 220 after each shift to the prediction preinitializes how many coefficients in a column are modulated or to be modeled. Since this prediction already executes one column before the column currently being modeled, the result is for the clock counter 22 already at Schiebevor yourself. If the result or the preinitialization is 0 or 1, the next shift operation of the shift register unit can be immediate with the next cycle 106 be triggered, what the clock counter 220 prompted accordingly. For larger preinitialized values, the clock counter delays 220 according to the output of the shift pulse 296 to the shift register unit 106 , As will be further mentioned below, the clock counter takes into account 220 further, whether the parallel processing by the bit-modeling units 108 ₂ respectively. ₃ has progressed far enough. The prediction result regarding the number of associated magnitude bits, as mentioned above, is logically combined from the 4-bit vector for the register 218 and the significance status variable.

Although previously indicated, it is emphasized once again how to update the first status bits via the demultiplexer 214 runs. As already mentioned, the first status bits show 274 whether a respective transformation coefficient is already significant or not, relative to the current bit-plane. An update can therefore only mean a transition from insignificant to significant. The coupling of the data bit 232 over the demultiplexer 214 with the corresponding register cell within the range 286 of the part 106 ₃ the shift register unit 106 Therefore, it is preferably designed so that the feedback to an update of the current register cell state of the data bit 232 corresponding first status bits with a value that a logical OR of the current state with the data bit 232 equivalent. In addition, appropriate precautions should be taken so that the data bit 232 0 is when the validity bit 246 not set. In other words, the demultiplexer 214 on the output side with the register cells within the range 286 coupled and adapted to be dependent on the multiplexer signal from the coefficient selector 222 the data bit output of the precode unit 102 in the above-described OR operation, to the corresponding first status bit register cell of the transform coefficient indicated by the multiplexer signal.

After above, the operation of the first coding pass associated with the bit-modeling unit 108 ₁ In the following, the mode of operation of the bit modeling unit responsible for the second coding pass will be described below 108 ₂ what's up to 5 Reference is made. In contrast to the first coding pass or pass 1, the second coding pass or pass 2 is responsible for magnitude bits which belong to already significant transformation coefficients. The second encoding pass is also called Magnitude Refinement Pass according to the JPEG2000 coding scheme, which is relevant to magnitude bits belonging to coefficients already significant before any coding pass of the current magnitude bit-plane, but not significant only by the first pass become. That is, the decision on the membership of a magnitude bit to the second coding pass is based on the status bits in the part 106 ₃ the shift register unit 106 should not be taken, yet not by the feedback on the demultiplexer 214 inside the store 286 has been updated, ie the first status bits in register cells to the right thereof from the perspective of 8th , Conversely, however, contexts of the magnitude bits associated with the second pass, as described in more detail below, are determined based on the updated first status bits, for which reason the bit modeling unit 108 ₂ as well as the bit modeling unit described below ₃ make the modeling in terms of magnitude bits that are from the currently modeled magnitude bits of the bit modeling unit 108 ₁ are sufficiently in time in units of the shift register ranks. In the exemplary case described herein exemplary is assumed by a fixed offset of two shift pulses, although, as will be explained in more detail below, also a variable design of this offset while maintaining a minimum distance, such. B. the two shift registers, may be provided.

5 shows the structure of the bit modeling unit 108 ₂ according to an embodiment of the present invention. Analogous to 4 she is back together with the sliding gistereinheit 106 and the associated cache 110 ₂ shown. The bit modeling unit 108 ₂ includes an application decision maker 300 , a precoder 302 , a control bit control 304 , a 4-bit register 306 and a sum threshold decision maker 308 , The application decision maker 300 is with the part 106 ₃ the shift register unit 106 coupled on the input side and output side with the 4-bit register 306 , Both an input of the precoder 302 as well as an input of the sum threshold decision maker 308 are with the register 306 coupled. On the input side is the precoder 302 also with parts 106 ₂ . 106 ₃ and 106 ₄ the shift register unit 106 coupled. Internally, the precoder includes 302 four mutually corresponding magnitude bit pre-encoding units 302 ₁ to 302 ₄ , one for each amount bit of the current tuple, which is also in 5 hatched are symbolized. Each of the precoding units 302 ₁ to 302 ₄ includes an exit 310 for a data bit and a 2-bit output 312 for a context index. The control bit control 304 includes an exit 314 for a pass end bit and an output 316 for a bypass mode bit, with the outputs 310 to 316 together a 14-bit output for a 14-bit word 318 define that with an input of the cache 110 ₂ is coupled. Also an output of the Sumschwellwertentscheiders 308 is with another input of the cache 110 ₂ coupled to a valid bit 320 to the cache 110 ₂ issue.

After the construction of the bit modeling unit 108 ₂ has been described, their operation will be described below. The application decision maker 300 is designed to be based on its input information in the register 306 for each amount bit to be currently modeled, form an information bit i _ae , j _ae , k _ae, and l _ae indicating whether or not the respective magnitude bit belongs to the pass 2, and the same by a suitable number of shift pulses of the shift register unit delayed in the register 306 to write. The delay is due to the fact that the input side of the precoder 102 with register cells of the magnitude bit part 106 ₂ the shift register unit 106 which is opposite to the register positions of the magnitude bits to which the application decision maker 300 currently evaluates the first control bits, here by example by three slide length downstream, the former register positions within the part 106 ₂ with a dash-dot line 322 are marked. In particular, the input side is now the precoding unit 302 ₁ with the register cell 252 _1.2 and within the register 306 coupled to the entry i _ae , the precoding unit 302 ₂ with the register cell 252 _1.3 and the bit j _{ae of} the register 306 etc. Each of the precoding units 302 ₁ to 302 ₄ is thus for a different one of the magnitude bits in the 4-er column currently to be modeled 322 responsible.

Each precoding unit 302 ₁ to 302 ₄ puts its data bit out of cells according to its amount bit 322 one. They determine the context index depending on the updated significances of the neighboring coefficients, for which the precoder 302 with the register cells of the part 106 ₃ the shift register unit 106 is coupled in 8th with a dash-dot line 324 is marked. In particular, for example, the Vorkodiereinheit 302 ₁ with the register cells 274 _1.1 to 274 _3.1 . 274 _1.3 to 274 _3.3 . 274 _1.2 and 274 _3.2 coupled, which thus affect coefficients that that of the magnitude bits 252 _1.2 surround. In particular, each coding unit sets 302 ₁ to 302 ₄ their context index 312 by forming a logical combination of the first control bits 274 of these neighboring coefficients. Should, however, the associated entry in the register 306 the respective precoding unit 302 ₁ to 302 ₄ indicate that their respective amount bit does not belong to pass 2, it sets the context index bits 312 to a bit combination that does not correspond to a meaningful context index and thus can be seen by itself that the corresponding data bit 310 is invalid.

In addition, the precoder is 302 with the register cells 280 from the part 106 ₄ the shift register unit coupled, in particular each Vorkodiereinheit 302 ₁ to 302 ₄ with the corresponding register cell for the second status bit assigned to the respective magnitude bit. Here are the Vorkodiereinheiten 302 ₁ to 302 ₄ designed so that the context indexes 312 which they output depend not only on the logic operation just described, but also on the respective second status bit, ie on whether the transformation coefficient concerned already had an amount bit in the previous more significant amount bit planes, that the second coding pass 2 went through or not. The coupling of the precoder 302 with the register cells of the part 106 ₄ is in 8th with the dash-dot line 326 indicated.

The control bit control 304 sets the bypass mode bit 316 for example, similar to the above with reference to the controller 224 described. The same applies to the pass-end bit 314 , Also the control bit control 304 thus sets the control bits 314 and 316 to provide the subsequent arithmetic encoder information indicating whether the so-called bypass mode should be active or whether the current coding pass is over.

As already mentioned, the bits form 310 - 316 the data word 318 , The cache 310 ₂ is now trained, for example, the 14-bit word 318 to include in the cache only if the valid bit 320 is set unless the pass-end bit 314 is set, in which case the data word 318 definitely in the cache 310 ₂ is stored. The summary of valid bit and 14-bit word 318 to a larger data word with storage in any case is of course also possible, as already referring to 4 had been described.

The sum threshold decision maker 308 sums the bits in the register 306 and checks if the sum is greater than or equal to 1 to the valid bit 320 in accordance with the result of the check, and thereby set the validity bit if at least one of the currently modifiable magnitude bits in the current tuple belongs to the pass2.

The bit modeling unit 108 ₂ is thus able, the amount bits associated with the pass 2 within a current tuple 322 in a processing cycle into a data word 318 precode. How many of the pairs of data bits and context index in the 14-bit data word 318 are actually valid or in the data stream to be coded at the output of the arithmetic coder 124 ( 3 ) are inherent in these pairs themselves, having in the negative case a special bit combination which is not a valid combination of data bit and context index or valid context. In this respect, the bit modeling unit needs 108 ₂ also no shift pulse output capability, since it is at least as fast as the described bit modeling unit 108 ₁ , which requires at least one processing cycle per amount bit associated with pass 1.

The following describes the structure and mode of operation of the bit modeling unit ₃ for the third coding pass. This refers to 6 taken. The structure is similar to the case of the bit modeling unit in terms of the blocks and their coupling to each other 108 ₁ from 4 , To avoid unnecessary repetitions are therefore in 6 Elements that basically perform the same tasks as elements 4 provided with reference numerals, which are different from those of 4 differ only by the first digit or the hundredth place, in such a way that they have a four instead of a two. In particular, all elements are off 4 also in 6 shown, with the difference that it is in the in 6 Of course, the cache shown around the cache 110 ₃ with the difference being that the control bit control is next to the pass end bit 442 a block end bit 440 outputs and no bypass end bit, and with the difference that the sign bit precoding unit 408 no coupling with the control bit control 424 having. Differences in functionality and more precise connection with the shift register unit 106 the corresponding elements in 4 and 6 will be apparent from the following description, so that functionality descriptions, which will be explained below, corresponding function descriptions with respect to the corresponding elements with reference to 4 in this respect should replace. Incidentally, regarding functionality and interconnection, the description of 4 directed.

In addition to the aforementioned elements, the bit modeling unit includes ₃ a run length encoding unit 500 having an input connected to the register 418 coupled to an input connected to another output of the analysis / prediction unit 400 is coupled. An output of the run length encoding unit 500 is intended to be a run length symbol 502 with three bits to output together with the other output bits 430 - 436 and 440 . 442 that in the cache 110 ₃ incoming data word 444 thus forming a 15-bit data word 444 is.

The third coding pass for which the bit modeling unit ₃ is responsible, comes into play when the coefficient to be modeled for the current bit-plane is still insignificant, and was not covered by the first pass. He is therefore also referred to as a "clean-up pass". The operation of the third coding pass is similar in terms of context formation and precoding to the first pass, but is extended by a so-called run length or RL (RL = one length) primitive. In other words, the third coding pass is responsible for the remaining magnitude bits which belong to neither the first nor the second coding pass, the coding of the pass-3 magnitude bits in the current 4-er column being the same as in the case of pass 1, with Exception that in the case that all magnitude bits in the current 4-er column are assigned a not yet significant transformation coefficient and have only insignificant neighboring coefficients, in which case the run-length mode sets in, from top to bottom the run of insignificant magnitude bits in indicates the current tuple and is thus only interrupted if any of the magnitude bits of the current 4-er column in the current bit-plane becomes significant or has an magnitude-bit-value of 1, from where to the subsequent magnitude bits in that 4-er column in the case of pass 1 and the sign of the RL primitive interrupting coefficients is encoded.

After this brief overview of the Pass 3 is again in synopsis of 6 and 8th the functioning of the unit ₃ explained. Since pass 3 is by definition the last among the sequential passes, the significance checks each already refer to those already performed by the bit modeling unit 108 ₁ updated first status bits, ie the first status bits left of the range 286 in 8th , Taking into account the adjacency coefficient significance checks, the range of the current 4-column should be at least two shift register ranks beyond the current range 282 the bit modeling unit 108 ₁ lie. According to the embodiment of 6 The current range is exactly two shift register rings behind this range. However, as explained above with reference to the passport 2, it may also be provided that the structure of the shift register unit faces 8th is also modified to allow a variable offset, so that the processing speed of the two units 108 ₁ and ₃ is decoupled.

The following is intended to refer to the 6 and 8th be taken in synopsis to the operation of the bit modeling unit ₃ to illustrate. The analysis / prediction unit 400 again checks in advance the 4-tuple of magnitude bits 252 _2.2 to 252 _2.5 next to the Mo formation in the unit ₃ is provided, which belong to the passport 3, ie which do not belong to the passport 1 or the passport 2, and is about the coupling 428 with register cells of the part 106 ₃ the shift register unit 106 coupled, these shift register cells in 8th with the dash 3-point line 504 are framed. Among these first status bits in the range 504 require the status bits within the range 286 an updating or taking into account that they may become significant during the first pass, for which the analysis / prediction unit also includes the previous prediction result of the analysis / prediction unit obtained with respect to the previous shift cycle 200 the bit modeling unit 108 ₁ used and the magnitude bits in the associated area 292 including the analysis / prediction unit 400 over the coupling 446 also with the register cells in the area 292 is coupled. In addition, the analysis / prediction unit uses 400 analogous to the case of 4 its last prediction result for the prediction, which for the current prediction naturally relates to the magnitude bits in the area currently to be modeled, namely the updates of the significances in the positions 274 _2.2 to 274 _2.5 due to its own coding pass, ie the coding pass 3, which takes place only in the current shift cycle, including the analysis / prediction unit 400 also with further magnitude bit register cells within the range 106 ₂ the shift register 106 is coupled, namely those of the current 4-er column within the dashed 3-point line 506 marked area. The prediction result gives the analysis / prediction unit 400 as in the case of 4 in the register 418 for the next shift cycle.

The run-length coding unit 500 evaluates at the beginning of the shift cycle, in which therefore the predicted with respect to their Pass 3 membership amount bits in the part 106 ₂ the shift register unit 106 have been advanced to represent the current magnitude bit, along with the current magnitude bits to which the prediction in the register 418 and according to the example of 6 from the analysis / prediction unit 400 gets the 4-bit vector in the register 418 to first determine whether the run-length primitive is to be used, ie, all of the magnitude bits of the current 4-time tuple are assigned to the third encoding pass and, if so, whether to break them at any point due to a significant magnitude bit below them is dependent on this evaluation, the run length symbol 502 adjust. From the significant amount bit, ie all amount bits after the becoming significant to below, including the significant, since this is still the sign in the coded data stream to be coded are from the coefficient selector 422 converted into a corresponding multiplexer signal, so that the coding units 402 and 408 in the manner described above for these magnitude bits corresponding pairs of data bits and context bits 430 - 436 produce. As already mentioned above, the precoding units require 402 and 408 this one processing cycle per amount bit. It is therefore only a single word 444 for a 4-column by the bit modeling unit ₃ in the run-length coding case is only generated as long as there is no more than one significant amount bit among the four current magnitude bits. Otherwise, multiple 15-bit data words 444 generated, only in the first data word 444 the run length symbol 502 indicates that the run-length primitive was used, and otherwise indicates that it is irrelevant.

Although pass 3 is the last pass, the amount data bit becomes 432 at the exit of the precoding unit 402 over the demultiplexer 414 in the part 106 ₃ the shift register unit 106 fed back, depending on the multiplexer signal from the coefficient selector 422 into the corresponding register cell within the 4-column of register cells 274 _2.2 to 274 _2.5 , the reason for this is that at the next shift, this 4's column in 8th is shifted one position to the left, with respect to which significances should be updated. On the output side is the demultiplexer 414 with the register cells 274 _2.2 to 274 _2.5 coupled. The input side is the multiplexer 404 with the register cells within the range 506 coupled. The multiplexer 406 is input side with the register cells within the range 508 which includes the first status bits for an area that the current 4's column of magnitude bits 506 including adjacent coefficients. The multiplexer 410 is with the corresponding range of register cells within the range 106 ₁ the shift register unit 106 coupled in 8th With 510 is highlighted. The multiplexer 412 is input side with register cells within the range 508 coupled, for example, the register cells 274 _1.2 to 274 _1.5 and 274 _2.1 to 274 _2.4 ,

Consequently, the bit modeling unit provides the prescribed manner ₃ for an analysis of the coefficients to be modeled, whether they are still insignificant, and an analysis of the direct neighboring coefficients, whether they are already significant, and in such a way that the analysis already takes place one column in front of the column currently to be modeled. The analysis result is again output as a 4-bit vector, in the register 418 on the basis of which vector the decision is made whether the RL primitive is applied to the four current coefficients. If the condition is met, what of the runlength coding unit 500 is checked, of course, via the multiplexer 516 also set the valid bit since every bit in the register 418 is set, and the coding unit 500 executes the run-length encoding scheme, which defines the icon 502 which represents whether the RL primitive was used and, where appropriate, at which position a coefficient becomes significant. If at least one coefficient in the current tuple becomes significant, it will also become significant by the precoding unit 408 for which the run interrupting magnitude bit encodes the associated sign (the bits 432 and 436 are irrelevant in this processing cycle). The bit positions following the magnitude bit interrupting the RL primitive are processed by the precode unit 402 executing the SP encoding scheme already described above for each successive coefficient in the current column, which involves establishing a data bit and matching context index formed by logically linking the significances of the neighbor coefficients. In addition, for these subsequent bit positions, when the data bit of the SP encoding scheme or the corresponding magnitude bit is set at the respective bit position, what happens over the connection 494 is verifiable by the precoding unit 408 execution of the SC scheme is carried out, which involves establishing a data bit and a matching context index formed by logically linking the significances and signs of the neighbor coefficients. The control bits 440 and 442 be from the control bit control 424 are set, which tell the subsequent arithmetic encoder whether the current coding pass or the current code block are over. The latter applies in the example of 2 for example, with the tuple u _n , v _n , w _n , x _n . Data bits and context indices of the SP and SC schemas and the symbol 502 and the control bits 440 and 424 become the 15-bit data word 444 summarized in the cache 110 ₃ if valid bit is set and in any case if the pass-end bit 442 is set, is stored.

Of course, from the analysis prediction unit 400 also predicted how many coefficients are modeled in a column, this prediction already being performed one column ahead of the column currently being modeled, so that the result is already present during the shift, and if the result is "0" or "1" is, with the next bar could immediately follow the next shift, which is the clock counter 426 the shift register unit 106 telling. The prediction result is formed by logically combining the four-bit vector and the significance status variable, as described above, in the shift register unit 106 appropriate precautions are taken that the sliding operation is actually only performed when both units 108 ₁ and ₃ its shift pulse to the shift register unit 106 to make sure that you do not start pushing too soon.

After the description of the three Bitmodelliereinheiten 108 ₁ to ₃ is briefly on again 3 With reference to the detailed description of the internal construction of the continuous flow separator 122 is continued according to an embodiment of the present invention. As described above, the three bit modeling units work 108 ₁ to ₃ largely independent of each other and especially parallel to each other in a common scan with a slight offset to each other from the magnitude bits of the current amount bit plane. The data words are each in their own the cache 110 ₁ to 110 ₃ filed in sequence. The buffers 110 ₁ to 110 ₃ are executed so that the order of the respective stored data words is retained during reading. This could be the cache 110 ₁ to 110 ₃ For example, be designed as FIFO memory (First-In-Fist-Out). Other versions are of course also possible, such. As implementations as a ring memory, but also directly addressable or content-addressable memory in the case of appropriate arrangements for the appropriate reading sequence, and accordingly the memory must not be present separately for each modeling unit.

The pass decision maker 122 Now decodes the data words in a suitable order and converts them into corresponding control signals for the arithmetic coder 124 , In particular, the pass decision maker reads 122 the data words first of the first pass until it is finished, which is indicated by the pass-end bit, then the data words of the second encoded pass from the buffer 110 ₂ until the pass-end bit is set, and then the data words from the cache 110 ₃ ... This respects the coding order as expected by the decoder.

7 shows the internal structure of the flow separator 122 according to an embodiment of the present invention in one with the arithmetic coder 124 on the one and the latches 110 ₁ . 110 ₂ and 110 ₃ coupled state on the other side. In particular, the pass decision maker comprises 122 from 7 three data word decoders 600 ₁ , 600 ₂ and 600 ₃ between each one of the caches 110 ₁ to 110 ₃ on the one hand and according to the inputs of a multiplexer 602 switched on the other side. Furthermore, the pass decision maker includes 122 a controller 604 ,

Between each pair of buffers 110 ₁ to 110 ₃ and data word decoder 600 ₁ to 600 ₃ is a respective data word line 606 ₁ . 606 ₂ respectively. 606 ₃ provided to read the next data word from the respective cache. Request and acknowledge signal lines 608 ₁ to 608 ₂ and 608 ₃ are also provided between these pairs to read the data words in a handshake procedure. On the output side, each data word decoder 600 ₁ to 600 ₃ five signal connections 610 ₁ . 610 ₂ and 610 ₃ to corresponding inputs of the multiplexer 602 on. The signal connections 610 ₁ to 610 ₃ each comprise a data bit, context index, valid bit, bypass mode bit, and pass end bit connection. Only the bypass mode bit connection is in the case of the data word decoder 600 ₃ replaced by a block end-bit connection. On the input side is the controller 604 each with the pass-end bit outputs of the data word decoders 600 ₁ to 600 ₃ and with the block end bit output of the data word decoder 600 ₃ coupled. The controller further includes an output connected to a control input of the multiplexer 602 is coupled. In addition, the data word decoders swap 600 ₁ to 600 ₃ Control signals with the controller 604 from, for example, can also serve the realization of a handshaking process. On the output side, the multiplexer includes 602 six signal connections 612 to the arithmetic coder 124 Namely, the above-mentioned signal connections for data bit, context index, validity bit, bypass mode bit, pass end bit and block end bit. In addition, the arithmetic coder 124 via a feedback path 614 with the controller 604 to inform the latter if it is resumable to receive further data on the signal links 612 to process.

During operation, the data word decoders now read 600 ₁ to 600 ₃ successively the data words from the respective one of the three latches 110 ₁ to 110 ₃ off and decode the data words. The data word decoder 600 ₁ each encodes the 12-bit data words back into one or two bursts of data to the multiplexer in one or two consecutive clocks 602 over the signal connections 610 ₁ forward, namely a burst having the magnitude data bit and the associated context index for coefficient bit modeling, and another burst if the magnitude data bit is set, with a data bit indicating the sign, and the associated context index. If the data bit is valid, the decoder continues 600 ₁ also the validity bit. The bypass mode bit and the pass end bit on the signal lines 610 ₁ conducts the decoder 600 ₁ directly from the 12-bit data word.

The decoder 600 ₂ behaves similarly. He also takes a decoding of the data words from the cache 110 ₂ back into data bits and context indices for coefficient modeling of up to four coefficients, so as to provide each 14-bit data word in the form of one to four consecutive bursts on the signal lines 610 ₂ to the multiplexer 602 forward. The data word decoder 600 ₃ Similarly, it behaves the incoming 15-bit data words from the cache 110 ₃ back in run-length symbols, data bits, and context indices for coefficient modeling, and when the data bit is set, converts sign-bit modeling and in one or two consecutive bursts on the signal lines 610 ₃ at the multiplexer 602 forwards. However, if the RL primitive comes to fruition, as indicated by the RL symbol, then the conversion is done by the data word decoder 600 ₃ in a - in the case of the complete run length or no significant amount bit among pass 3 bits - to four - in the case of a significant magnitude bit among pass 3 bits at the second position from the top within the tuple burst. The control 604 evaluates the pass-end bits to successively first the signal lines 610 ₁ with the corresponding signal lines of the signal lines 612 to connect, then the signal lines 610 ₂ and then turn the signal lines 610 ₃ , In this way, the arithmetic coder gets 124 with each data bit and context index also information on whether to use the bypass mode for the respective coefficient and whether the current coding pass or code block is over. In the former case, the arithmetic coder interrupts 124 namely, its arithmetic interval division, and inserts the corresponding data bit in clear text into the arithmetic data stream when the bypass mode bit is set, and in the second case the arithmetic encoder resets its current interval back to the predetermined value, as well as probability estimates of the individual contexts in the case that the arithmetic coder is adaptive. Through the handshake connections described above, the flow of information within the flow decision maker becomes 122 depending on whether the caches 110 ₁ to 110 ₃ Data or whether the arithmetic coder is ready to accept data.

The above-described block coder after the 3 - 8th can be implemented in hardware and in this case represents a hardware-based JPEG2000 block coder in which the number of process steps required in the context modeling is reduced by the above-illustrated parallel processing and the pass prediction. Depending on the coding pass, a coefficient bit was equalized either in one step modeled in time with its sign bit or in one step a column of up to four coefficient bits simultaneously modeled or modeled in one step a column of up to four coefficient bits in a so-called run-length primitive, wherein in the same step the significant coefficient is modeled together with its sign bit.

Of Furthermore, a prediction was provided, how many coefficients can be modeled in a column in one step. These Effect measures in a clocked process at the same clock frequency coding a coding pass in less time, since waiting times for register set operations are eliminated, up to four coefficients can be modeled simultaneously to four modeling operations can be done in one step, already known at the beginning of the modeling process of a column how many coefficients can be modeled in one step, thereby time-consuming test functions while the modeling is omitted.

moreover enabled the bite extraction a reduction of the to be logged and to update separate status variables for each Coefficients of a code block, which on the one hand reduces the required memory size and on the other hand speeds up the coding of a coding cycle can be, because additional Read and write operations omitted.

An advantage of the block coder of 3 - 8th consists, in particular, in the fact that, depending on the encoding cycle, up to four coefficient bits lying in a strip underneath were modeled simultaneously in order to generate information words which may possibly even contain compressed information for up to four bit context pairs. These information words are latched and fed by appropriate evaluation in a decoder to the downstream arithmetic coder in a suitable representation and in the correct order in the manner described above. By the above measures, coefficient bit modeling has been improved to allow easier hardware implementation.

As described above, the bitextractor of a memory unit contains a vector of coefficients for extracting from each coefficient k of the vector for the bit plane to be coded m information comprising the magnitude bit km, the sign bit k _vz and status bits k _st , the status bits again consist of the bit which indicates whether the coefficient in the bit plane m is already significant, for which it is checked for all magnitude bits above the current level whether a bit is set. Where, if at least one bit is set, the coefficient in that bit-plane is significant and the bit indicating whether the MR-coding scheme has been applied to that coefficient for the first time or already before, for which all magnitude bits above that current bit-plane is checked whether one of these bits is set, where if at least two bits are set, then the MR-coding scheme for the coefficient has already been applied once. As mentioned above, this extraction eliminates the need for separate state variables for each coefficient of a coding block since this information must be redetermined for each strip and held only for the duration of the coding, thereby reducing the amount of memory required and the coding the coding cycle can be accelerated because additional read and write operations omitted.

A hardware implementation according to the 3 - 8th Thus, it can be expected that in a clocked process at the same clock frequency the encoding of a coding cycle can be done much faster, because as mentioned above waits for register-setting processes omitted, up to four coefficients can be modeled simultaneously, up to five modeling can be done in one step It is already known at the beginning of the modeling process of a column how many coefficients can be modeled in one step, which eliminates time-consuming test functions during modeling and eliminates additional read and write operations for the status variables. These benefits are for a compressor, as in 1 is shown, and in which the encoder of 3 can be used, of high value. For it has already been stated in several studies that the block coder and above all the coefficient bit modeling represent the most complex operation within the JPEG2000 coding process. In the already mentioned in the introduction to the present application by Lian et al. For example, we present a test result that requires nearly 52% of the computational power of a computer for the sum of all three encoding cycles. Acceleration of the coefficient bit modeling process thus significantly affects the entire coding process. In implementations in which a higher coding speed is achieved by multiple instantiation of the block coder, resources can thus be saved, thus according to the exemplary embodiment 3 - 8th less coding units are required to obtain the same coding speed.

Implementations just mentioned can be implemented, for example, on FPGAs (Field Programmable Logic Array) but also as an integrated circuit or ASIC (Application Specific Integrated Circuit). A hardware implementation has already been implemented for an FPGA, for which the corresponding functional units have been described by VHDL and translated with suitable tools and synthesized for the target platform.

Various modifications may be made to the embodiments 3 - 8th be made. For example, the shift register 106 be executed differently. In particular, it may for example have more shift register ranks, ie in 8th so be widened to the left. Furthermore, the offset between the current 4's vectors 292 . 322 and 506 also be larger than the two shift register ranks, as in 8th is shown. In addition, it is possible that the offset is variable. For this purpose, for example, the shift register unit is not executed uniformly, as in 8th but as two shift registers, one for the bit modeling unit 108 ₁ and another for the bit-modeling units 108 ₂ and ₃ in which a FIFO memory is arranged between them to serve as a variable buffer between the shift registers.

In the foregoing, it has been mentioned that the sign bit pre-coding units based on the first control bits determine whether or not the respective sign bits of the neighboring coefficients are known on the decoder side. Normally, then, the first control bit of the Transformationko efficient, which is adjacent to the top of the respective current coefficient, than the demultiplexer 214 respectively. 414 to be updated. However, should that, because of signal propagation delays, cause the processing cycles to be delayed, it would also be possible for the sign bit pre-coder units to virtually update a not yet updated first next adjacent coefficient control bit by the corresponding magnitude bit of that adjacent coefficient.

In the foregoing, for the sake of simplicity of illustration, marginal problems such as at the edge of bit planes, at the end and at the beginning of a stripe, etc. have not been further deepened so as not to unduly complicate the above description. Unavailable data or data that is not available to the decoder can be set according to agreement to predetermined values in a manner preferably known on the decoder side. It may also be in the block encoder after 3 when encoding the magnitude bits of the stripes, the respective adjacent rows of the adjacent stripes are disregarded. In that case, for example, the shift register would also be smaller to fit in each of the parts 106 ₁ to 106 ₃ just to cover the four lines of the strips.

9 shows a more general example of a block encoder. The block coder of 9 who is generally with 700 is displayed, as well as the previous embodiment is intended to encode a block of transform coefficients, each represented by a plurality of magnitude bits defining a sequence of magnitude bit planes. In 9 are these amount bits 252 illustrated with the same reference numerals and the same shape and arrangement, that is arranged as a cube in rows and columns and in depth in magnitude bit planes, wherein the resulting three-dimensional block 701 of amount bits 252 shown in section, so its current magnitude bitmap 704 is visible, while the already coded less significant magnitude bit-planes are further behind and the more significant bit-planes are not visible. The block encoder 700 has an encoder 702 on which is provided, the magnitude bits 252 to go through the amount bit by bit by going through the respective current amount bit level 702 in a predetermined order individually or as in 9 on the basis of the preceding exemplary embodiment, shown in tuples of adjacent magnitude bits 252 , The coding device encodes in the current amount bit level 702 in order of passing predetermined amount bits into a coded data stream 706 , Passing through the magnitude bits 252 the current amount bit level 704 thus takes place either individually or tupleweise, as was the case in the previous embodiment. In particular, in 9 a currently to be coded tuple by hatching at 708 highlighted.

The coding device 702 now has a cache 710 , a bitextractor 712 and an encoder 714 on, the bitextractor traversing the magnitude bits 252 first status bits 716 which determines the transform coefficients by magnitude bits of the current magnitude bit-plane 702 which are next in line at the earliest according to the order of passage, and for the representative possible magnitude bits in FIG 9 with a rectangle 718 are highlighted, a significance related to the current amount bit level 704 Show. In particular, the bite extractor determines 712 these status bits are of magnitude bits representing the same transform coefficients as the magnitude bits 718 but in more significant bit planes are the same. With these first status bits 716 The bitextractor is constantly filling 712 the memory memory 710 that temporarily stores these first status bits, namely as long as the first status bits by the encoder 714 needed, ie accessible and updatable, must be cached. The cache 710 may be performed as a FIFO memory, for example. The encoder 714 performs the coding of the predetermined among the magnitude bits 252 in the coded data stream 706 using the first status bits in the cache 710 by.

In spite of of the amount-side-wise iterating through the amount-bit-planes it is therefore not necessary that the first status bits for all the transformation coefficients and thus over the entire coding of the have to be stored in individual amount bit levels.

In the embodiment of 9 is passing through the amount bits of the current amount bit plane 104 not limited to a tuple-by-pass procedure. Rather, the magnitude bits 252 also through individually or in pairs, etc. The cache 710 can be provided as in the previous embodiments, in addition to the first status bits also store more information. Examples are the temporary storage of amount bits 252 and / or associated sign bits and optionally second status bits. Although in the embodiment of 9 only predetermined ones of the magnitude bits from the encoder 714 can be detected and thus a lossy compression of the transform coefficients is made, analogous to the previous embodiment, the encoder 714 Also, a further encoder may be connected in parallel to encode further other predetermined magnitude bits, then downstream of these two encoders a suitable entropy coding means may be arranged with a multiplexer or only one multiplexer / decision maker to determine the order in which the different different predetermined ones Amount bits in the encoded data stream 706 be involved. Furthermore, additionally or alternatively, between the buffer and the encoder 714 a predictor may be switched which, similarly to the prediction units in the preceding embodiments, predicts whether or not they are predetermined ones for non-in-order carry bits.

Depending on The circumstances can be described procedures for transform coefficient block coding not only in hardware, but of course also be implemented in software. The implementation can be on a digital storage medium, in particular a floppy disk, a CD or a DVD with electronically readable control signals, which interact with a programmable computer system can, that the corresponding procedure is carried out. Generally exists the invention thus also in a computer program product with a program code stored on a machine-readable medium to carry out an above procedure when the computer program product on a Calculator expires. In other words Thus, the invention can be thought of as a computer program with a program code to carry out an above procedure can be realized when the computer program runs on a computer. Here, under a computer is any form of processor to understand that is designed to be a program or a program code perform, So in particular also microcontroller or the like.

Claims (30)

Device for coding a block ( 34 ) of transform coefficients, wherein the transform coefficients are each determined by means of several magnitude bits ( 252 ), so that they are a sequence of amount bit planes ( 38 ₁ ... 38 _n ) with an encoder for traversing the magnitude bits of a predetermined one of the magnitude bit-planes ( 38 ₁ .... 38 _n ) and encode predetermined ones of the magnitude bits into a coded data stream, the encoder comprising: a buffer memory ( 106 ; 710 ); a bitextractor ( 104 ; 712 ) for, upon passing through the magnitude bits, determining first status bits indicative of the significance of the predetermined magnitude bit-plane for the transform coefficients represented by magnitude bits of the predetermined magnitude bit-plane next in order according to an order of traversal at the earliest Magnitude bits representing the same transform coefficients as the earliest next-ranked magnitude bits but at more significant bit-planes than the same and filling the cache with the first status bits detected; and an encoder ( 112 . 108 ₁ ; 108 ₂ ; ₃ ; 714 ) for encoding the predetermined magnitude bits into the encoded data stream using the first status bits in the buffer memory ( 106 ), wherein the latch is arranged to store the first status bits for only a portion of the transform coefficients at any one time, and wherein the encoder is adapted to traverse a less significant magnitude bit plane upon passing through the predetermined magnitude bit plane and the predetermined magnitude bits encode the less significant magnitude bit-plane into the data stream, detecting the first status bits and filling the buffer by the bit-extractor. Apparatus according to claim 1, wherein the bit extractor and the encoder are arranged such that the first status bits with which the bit extractor fills the buffer indicate the significance for transform coefficients represented by magnitude bit plane magnitude bits corresponding to a constant offset according to FIG of the Order of the pass through the encoder are processed to encode the predetermined magnitude bits among the magnitude bits of the current magnitude bit-plane. Device according to claim 1 or 2, wherein the buffer formed as a shift register The bitextractor is designed to apply the shift register to fill a front end thereof and the encoder formed is to encode the predetermined magnitude bits in the encoded one Data stream at least also using register contents perform the shift register, the at least one slide behind the front end of the shift register are arranged, and in an evolution of the coding also an update register contents of the shift register to perform at least one slide gate are arranged before the register contents, the be used for coding. Apparatus according to claim 1, wherein the coding means is arranged to adjust the magnitude bits of the predetermined magnitude bit-plane ( 38 ₁ .... 38 _n ) in tuples ( 292 ; 322 ; 506 each of a plurality of adjacent magnitude bits, the encoder comprising: a precoder for, upon passing through the magnitude bits, encoding predetermined ones of the magnitude bits of the tuples into data words such that a predetermined magnitude bit together with an associated sign bit in one of the data words ( 244 ; 444 ) or that a predetermined amount bit together with another predetermined magnitude bit of the same tuple is encoded into one of the data words ( 318 ; 444 ) is encoded; a data word buffer ( 110 ₁ ; 110 ₂ ; 110 ₃ ) for temporarily storing the data words ( 244 ; 318 ; 444 ); and an entropy coder ( 112 ) for encoding the data words ( 244 ; 318 ; 444 ) from the data word buffer into the encoded data stream. Apparatus according to claim 4, wherein the transform coefficients are each determined by means of the plurality of magnitude bits ( 252 ) and an associated sign bit ( 250 ) and the precoder ( 108 ₁ ; ₃ ) is designed such that the coding of the predetermined magnitude bits also depends on the sign bit associated with this predetermined magnitude bit. Apparatus according to claim 5, wherein the precoder ( 108 ₁ ; ₃ ) such that the coding of the predetermined magnitude bits also depends on sign bits associated with the magnitude bits adjacent to the predetermined magnitude bits. Apparatus according to claim 6, wherein the precoder ( 108 ₁ ; ₃ ) is formed such that the coding of the predetermined magnitude bits also of first status bits ( 274 ) indicative of significance to the predetermined magnitude bit-plane for the transform coefficients represented by the predetermined magnitude bits and magnitude bits adjacent to the predetermined magnitude bits. Device according to one of Claims 5 to 7, in which the precoder ( 108 ₁ ; ₃ ) the cache ( 106 ) as well as the Bitextraktor ( 104 ), wherein the bitextractor is designed in order to pass through the buffer memory (when passing through the magnitude bits in tuples). 106 ), having a tuple of a plurality of adjacent magnitude bits of the predetermined magnitude bit-plane, which according to an order of traversal at the earliest next tuple, corresponding sign bits to the magnitude bits of the earliest next-row tuple, and first status bits corresponding to the Transform coefficients indicated by a plurality of adjacent magnitude bits of the predetermined magnitude bit-plane of a tuple at the earliest next in order of traversal, indicating significance with respect to the predetermined magnitude bit-plane, the precoder configured to encode based on a content of the cache. Apparatus according to claim 8, wherein the bite extractor ( 104 ) is designed to fill the buffer ( 106 ) the first status bits ( 274 ) from amount bits ( 276 ), which are the same transform coefficients as the magnitude bits of the earliest next-in-order tuple, but in more significant magnitude bit-planes are the same. Apparatus according to claim 8 or 9, wherein the bitextractor ( 104 ) is designed to fill the buffer ( 106 ) the plurality of adjacent magnitude bits of the earliest next to be coded tuple and the associated sign bits by a memory access ( 114 ) to a memory ( 102 ), which stores the magnitude bits and sign bits. Device according to claim 9 or 10, in which the buffer stores a shift register ( 106 ), the first status bits ( 274 ), with which the cache ( 106 ), only after more than five shift operations loses, and / or amount bits ( 252 ), with which the cache ( 106 ) after more than three shift operations and / or sign bits ( 250 ), with which the cache ( 106 ) is filled, only after loses more than four shift operations. Device according to one of Claims 7 to 11, in which the precoder ( 108 ₁ ), an amount bit precoding unit ( 202 ), which is designed to determine on the basis of an input amount bits among the adjacent magnitude bits of a tuple currently in line according to an order of passage ( 282 ), and first status bits ( 290 ) for the transform coefficients represented by a first plurality of magnitude bits of the predetermined magnitude bit plane adjacent to the supplied magnitude bit to generate a first sub-data word from which the supplied magnitude bits ( 232 ) and an associated amount bit context ( 236 ) and a sign bit precoding unit ( 208 ) which is adapted to be based on the sign bit associated with the supplied magnitude bit ( 250 ); of a second plurality of magnitude bits of the predetermined magnitude bit plane which are adjacent to the inputted magnitude bit, sign bits (FIG. 294 ); and the first status bits ( 290 ) for the transform coefficients represented by the second plurality of magnitude bits of the predetermined magnitude bit plane, to generate a second sub-data word from which the sign bit associated with the input magnitude bit ( 234 ) and an associated sign bit context ( 236 ) are determinable, and is designed such that the data word ( 244 ) of the supplied magnitude bits comprises the first sub-data word and the second sub-data word, and wherein the entropy coder ( 112 ) is configured to determine from the first partial data word the supplied amount bit and the associated magnitude bit context and encode the supplied amount bit using the supplied amount bit context context-dependent arithmetic in the data stream, and, if the supplied amount bit is significant, from the second sub-data word to determine the sign bit associated with the supplied magnitude bit as well as the same sign bit context associated therewith, and to arithmetically code the sign bit associated with the supplied magnitude bit using the associated sign bit context context-dependently into the data stream. Apparatus according to claim 12, wherein the precoder ( 108 ) comprises a multiplex circuit comprising a first multiplexer circuit ( 204 ) which, by means of a control signal, is any one of the magnitude bits of the tuple currently in the row ( 282 ) and which is arranged to derive the indicated magnitude bit as the supplied magnitude bit of the magnitude bit pre-encoding unit ( 202 ); a second multiplexer circuit ( 206 . 212 ), which is controllable by the control signal to the first status bits ( 290 ) for transform coefficients represented by a third plurality of magnitude bits of the predetermined magnitude bit plane adjacent to the displayed magnitude bit as the first control bits for the transform coefficients represented by the first plurality of magnitude bits, the magnitude bits precoding unit (FIG. 202 ), and the first status bits ( 290 ) for transform coefficients represented by a fourth plurality of magnitude bits of the predetermined magnitude bit plane adjacent to the displayed magnitude bit as the first control bits for the transform coefficients represented by the second plurality of magnitude bits, the sign bit precoding unit (FIG. 208 ); a third multiplexer unit ( 210 ) controllable by the control signal to correspond to the sign bits (16) associated with the displayed magnitude bit and the fourth plurality of magnitude bits of the predetermined magnitude bit-plane ( 294 ) as the sign bit associated with the predetermined magnitude bit and the sign bits of the sign bit precoding unit sign associated with the second plurality of magnitude bits ( 208 ). Device according to one of Claims 7 to 13, in which the precoder ( 108 ₁ ; ₃ ) a predictor ( 200 ; 400 ) for predicting whether and, if so, which of the magnitude bits among the adjacent magnitude bits of the predetermined magnitude bit-plane of a tuple next in line according to the order of traversal ( 274 _5.2 to 274 _5.5 ; 274 _3.2 to 274 _3.5 ) to the predetermined magnitude bits, the predicting means being adapted to calculate the prediction on the basis of the magnitude bits ( 282 ) of the predetermined magnitude bit-plane of the next-ranked tuple and the currently-ranked tuple and the first status bits (FIG. 284 ; 504 ) for the transform coefficients represented by the magnitude bits of the predetermined magnitude bit-plane of the next-ranked tuple, the currently-ranked tuple, and the next-to-next-ranked tuple. Device according to Claim 14, in which the predicting device ( 200 ) is arranged such that the prediction of whether and, if so, which of the magnitude bits among the adjacent magnitude bits of the predetermined magnitude bit-plane of a next-in-order tuple according to the order of traversal belongs to the predetermined magnitude bits also depends on a previous prediction ( 218 ) of the predictor depends on whether and, if so, which of the magnitude bits are below the adjacent magnitude bits of the predetermined magnitude bits ne of a tuple currently in line according to the order of traversal belongs to the predetermined magnitude bit. Device according to Claim 14, in which the predicting device ( 200 ) is configured such that the prediction of whether and, if so, which of the magnitude bits among the adjacent magnitude bits of the predetermined magnitude bit-plane of a next-in-order tuple according to the order of traversal belongs to the predetermined magnitude bit also of first status bits ( 274 _3.2 to 274 _3.5 ) for the transform coefficients represented by the magnitude bits of the predetermined magnitude bit-plane of the most recently ranked tuple according to the order of traversal. Device according to one of Claims 14 to 16, in which the prediction device ( 200 ) is adapted to produce a result of the prediction in the form of a bit vector ( 218 ) outputting a vector bit (i _ae , j _ae , k _ae , l _ae ) indicative of membership or disagreement of the respective magnitude bit of the next-ranked tuple per magnitude bit of the next-ranked tuple , Device according to one of claims 14 to 17, wherein the precoder ( 108 ₁ ) further comprises a shift pulse generator ( 200 . 220 ) adapted to be based on the magnitude bits of the predetermined magnitude bit planes of the next ranked tuple and the currently ranked tuple and the first transform coefficient control bits, which are next in magnitude by magnitude bits of the predetermined magnitude bitplane representing the tuples currently being ranked and the tuple next in line, predict how many of the magnitude bits among the adjacent magnitude bits of the predetermined magnitude bit-plane of the next-ranked tuple belong to the predetermined magnitude bits, and based on the predicted number and a processing clock in units of which the encoding of the predetermined magnitude bits in data words is performed to delay no, one or more clock cycles of the processing clock, a shift pulse to a shift register ( 106 ). Device according to one of Claims 7 to 18, in which the precoder ( 108 ₁ ; ₃ ) a multiplexer drive ( 422 . 222 ), which is designed to be connected to a multiplexer circuit ( 204 . 206 . 210 . 212 ) output a control signal sequentially indicating, in a predetermined order among the adjacent magnitude bits of a currently ranked tuple, those magnitude bits belonging to the predetermined magnitude bits. Device according to one of Claims 4 to 19, in which the precoder ( 108 ₁ . 108 ₂ . ₃ ) is designed to also generate a data word for tuples during its passage, under whose adjacent magnitude bits none of the predetermined magnitude bits belongs, and a validity bit ( 246 ; 320 ; 446 ) depending on whether there is a predetermined amount bit among the magnitude bits in a tuple currently in line according to the order of the run, and the data word buffer ( 110 ₁ ; 110 ₂ ; 110 ₃ ) is designed so that only in the case of a set validity bit the respective data word ( 244 ; 318 ; 444 ) or when the respective data word ( 244 ; 318 ; 444 ) has been generated for the last tuple in the predetermined amount bit plane. Device according to one of Claims 5 to 20, in which the precoder ( 108 ₁ . 108 ₂ . ₃ ) is arranged such that it traverses the amount bits of the predetermined magnitude bit plane in stripes such that the adjacent bits of each tuple are in one column of the block, and contiguous tuple columns are adjacent to one another in columns or in immediately adjacent strips of rows of the block with one of the two tuples at one end of one of the immediately adjacent strips and the other of the two tuples at an opposite end of the other of the immediately adjacent strips. Device according to one of Claims 5 to 21, in which the precoder ( 108 ₁ . 108 ₂ . ₃ ) is configured such that it passes through a less significant amount bit plane upon passing through the predetermined amount bit plane and encodes the predetermined magnitude bits of the less significant amount bit plane into data words. Device according to one of Claims 5 to 22, in which the precoder ( 108 ₁ . ₃ ) is designed such that, for each predetermined magnitude bit, it carries a bypass mode bit ( 240 . 440 ) of the respective data word depending on a bit depth assigned to the predetermined amount bit plane. Apparatus according to claim 7, wherein the precoder is arranged such that the coding of each tuple of a plurality of adjacent magnitude bits also of first status bits ( 274 ) indicative of significance to the predetermined magnitude bit plane for the transform coefficients represented by the predetermined magnitude bits and magnitude bits adjacent the predetermined magnitude bits, and second status bits (Fig. 280 ), which for the transformation coefficients determined by predetermined Be trage bits, indicate whether there are two or more magnitude bits among the magnitude bits representing the respective transform coefficients and being in more significant magnitude bit-planes than the predetermined magnitude bit-plane, which are significant, for the respective transform coefficients. Apparatus according to claim 24, wherein the precoder ( 108 ₂ ) an amount bit precoding unit (s) per magnitude bit of the plurality of adjacent magnitude bits of the tuples 302 _# ) arranged to be based on the respective magnitude bits among the adjacent magnitude bits of a tuple currently in line according to an order of traversal ( 322 ), the first status bits ( 324 ) for the transform coefficients represented by a seventh plurality of magnitude bits of the predetermined magnitude bit plane adjacent to the respective magnitude bits and the second status bit (Fig. 280 ) for the transformation coefficient represented by the respective magnitude bit to generate a respective partial data word from which the respective magnitude bit ( 310 ) and an associated amount bit context ( 312 ) can be determined, and is designed such that the partial data words together the data word ( 318 ) of the predetermined magnitude bit of the currently ranked tuple, and that it is possible to determine only from the data word which of the partial data words have been generated for magnitude bits belonging to the predetermined magnitude bits, the entropy encoder being arranged to extract from the partial data words to determine which of them have been generated for magnitude bits belonging to the predetermined magnitude bits, and to determine therefrom the respective magnitude bit and the associated magnitude bit context, and arithmetically code the respective magnitude bit into the data stream using the associated magnitude bit context context-dependently. Apparatus according to claim 25, wherein the precoder includes a predictor ( 300 ) for predicting whether, and if so, which one or more of the magnitude bits among the adjacent magnitude bits of the predetermined magnitude bit-plane of a tuple at the earliest next in the order of running belongs to the predetermined magnitude bits, the predicting means being arranged; to make the prediction based on the first status bits for the transform coefficients represented by the magnitude bits of the predetermined magnitude bit-plane of an earliest next-in-line-ranked tuple. Apparatus according to claim 14, wherein the precoder ( ₃ ), a run length encoding unit ( 500 ) based on a prediction result ( 418 ) of the prediction device ( 400 ) in the state where the next-ranked tuple is next in line, a run length data word ( 446 ) from which it is possible to determine how many of the magnitude bits of the ranked tuple in a predetermined magnitude bit order among them are consistently insignificant, and if one of the magnitude bits of the ranked tuple exists, which is significant rather than the first magnitude bit in this tuple in the magnitude bit order, at which position the first significant magnitude bit in the magnitude bit order is, a coefficient selector unit ( 422 ), which is designed to be based on a prediction result ( 418 ) of the prediction device ( 400 ) in the state where the next-ranked tuple is currently at issue, output a control signal sequentially in the magnitude bit order, the first significant magnitude bit in the magnitude bit order and the magnitude bit following the first significant magnitude bit in the magnitude bit order pretending tuple, and a magnitude bit precoding unit ( 402 ) which is adapted to generate, in dependence on the control signal, in each case on the basis of a respective predetermined magnitude bit among the adjacent magnitude bits of the series-coming tuple, and first status bits ( 510 ) for the transform coefficients represented by a first plurality of magnitude bits of the predetermined magnitude bit plane adjacent to the respective predetermined magnitude bits to generate a first sub-data word from which the respective predetermined magnitude bits ( 432 ) and an associated amount bit context ( 436 ) and a sign bit precoding unit ( 408 ) which is designed to be dependent on the control signal on the basis of the sign bit associated with the respective predetermined magnitude bit; of a second plurality of magnitude bits of the predetermined magnitude bit plane which are adjacent to the respective magnitude bit, associated sign bits ( 510 ); and the first status bits ( 508 ) for the transform coefficients, which are represented by the second plurality of magnitude bits of the predetermined magnitude bit plane, to generate a second sub-data word, from which the sign bit associated with the respective predetermined magnitude bit ( 434 ) and an associated sign bit context ( 436 ) are determinable, and is designed such that one of the data words ( 444 ) the first partial data word, the two te part data word and the runlength data word comprises, and wherein the entropy ( 112 ) is designed to extract from the runlength data word ( 446 ) to determine information about the amount bits insignificant in the predetermined magnitude bit order and encode it arithmetically into the data stream, from the first partial data word - except in the case of the first significant magnitude bits in the magnitude bit order - determine the respectively given magnitude bit and the associated magnitude bit context and encode the respective magnitude bit arithmetically into the data stream using the supplied magnitude bit context, and, if the respective predetermined magnitude bit is significant, also in the case of the first significant magnitude bit in the magnitude bit order, from the second partial data word corresponding to the respectively predetermined one Determine amount bit associated sign bit and the same sign bit context associated and the associated each bit of the given amount bit sign bit using the associated sign bit context context-dependent arithmetic to encode in the data stream. The apparatus of any one of claims 5 to 27, wherein the precoder is further configured to encode other magnitude bits of the tuples other than the predetermined magnitude bits into further data words such that one of the other magnitude bits together with an associated sign bit in one of the data words ( 244 ; 444 ), or one of the other magnitude bits together with another of the other magnitude bits of the same tuple in one of the data words ( 318 ; 444 ), wherein the device further comprises a further latch for latching the further data words, and the entropy coder is adapted to first encode the data words in the buffer and then the further data words in the further buffer in the coded data stream. Method for coding a block ( 34 ) of transform coefficients, wherein the transform coefficients are each determined by means of several magnitude bits ( 252 ), so that they are a sequence of amount bit planes ( 38 ₁ ... 38 _n ), comprising the steps of: traversing the magnitude bits of a predetermined one of the magnitude bit-planes ( 38 ₁ .... 38 _n by encoding predetermined ones of the magnitude bits into a coded data stream, by performing the steps of: by passing the magnitude bits, determining first status bits representing the transform coefficients represented by magnitude bits of the predetermined magnitude bit-plane which, at the earliest, next at the Rows are, indicative of significance to the predetermined magnitude bit-plane, of magnitude bits representing the same transform coefficients as the earliest next-ranked magnitude bits but at more significant bit-planes than the same; Filling a buffer with the determined first status bits; and encoding the predetermined magnitude bits into the encoded data stream using the first status bits in the buffer ( 106 ), wherein the first status bits are stored in the cache for only a portion of the transform coefficients at any one time, and passing through the predetermined magnitude bit plane through a less significant magnitude bit plane encoding the predetermined magnitude bits of the less significant magnitude bit plane into the first Data stream and again determining the first status bits and refilling the buffer. Program with a program code for performing the The method of claim 29 when the program is on a processor expires.