DE102006051292B4 - Clock generating circuit, multi-phase clock generator, storage element, method for generating clock signals and method for locking the phase - Google Patents

Abstract

A clock generation circuit comprising:
an inverter (I0) directly receiving an external clock signal (ECLK) and outputting an inverted external clock signal;
M loop circuits (LC _{1 ... M} ) connected in series, where M is an integer ≥ 2, the first loop circuit (LC ₁ ) receives the inverted external clock signal, each of the M loop circuits (LC _{1 ... M} ) N nodes (A, B, C, D), where N is an integer ≥ 4, and each of the first through (M-1) th loop circuits (LC _{1 ... M-1} ) N internal T intermediate clock signals each one associated with the N nodes (A, B, C, D) generated; and
N groups of inverters (INV _{1 ... N} ), each having at least M - 1 inverters (I9 _{1 ... (M-1)} , I10 _{1 ... (M-1)} , I11 _{1 ... ( M-1)} , I12 _{1 ... (M-1)} ) connected in series, each of the M-1 inverters (I9 _{1 ... (M-1)} , I10 _{1 ... (M -1)} , I11 _{1 ... (M-1)} , I12 _{1 ... (M-1)} ) receives a corresponding internal intermediate clock signal from a preceding loop circuit and outputs a corresponding internal intermediate clock signal to a next loop circuit,
where N internal clock signals ...

Description

The The invention relates to a clock generating circuit, a multi-phase clock generator, a memory element, a method for generating clock signals and a method of locking the phases.

1A illustrates a conventional phase locked loop having a phase detector (PD) 10 , a charge pump (CP) 12 , a loop filter (LP) 14 , a voltage controlled oscillator (VCO) 16 , one or more dividers 18-1 . 18-2 and / or one or more dividers 20 may contain.

The phase detector (PD) 10 may receive an external clock signal ECLK and generate an UP or DN signal in response to a phase difference between the external clock signal ECLK and a feedback clock signal or feedback clock signal DCLK. If the phase of the external input signal ECLK precedes that of the feedback clock signal DCLK, the UP signal is activated. When the phase of the ECLK lags behind that of the DCLK, the DN signal is activated.

The charge pump (CP) 12 and / or the loop filter (LP) 14 may increase the level of a control voltage Vc in response to the activated UP signal and decrease the level of the control voltage Vc in response to the activated DN signal.

For example, if the frequency of the ECLK is 1 GHz, a conventional Voltage Controlled Oscillator (VCO) may be used. 16 to obtain one or more final internal clocks having a frequency of 2 GHz, generate two clock signals CLK0 and CLK180 each having a frequency of 4 GHz. The divider 18-1 may divide down the clock signal CLK0 to produce two clock signals ICLK0, ICLK180 each having a frequency of 2 GHz. The divider 18-2 can down-divide the inverted clock signal CLK180 to generate two clock signals ICLK90, ICLK270 each having a frequency of 2 GHz.

The divider 20 may receive one of the clock signals ICLK0, ICLK180, ICLK90 and ICLK270 and output the feedback clock signal DCLK at a frequency of 1 GHz which corresponds to the frequency of the ECLK.

This means that the divider 20 is required to obtain final internal clock signals ICLK0, ICLK180, ICLK90 and ICLK270 at a higher frequency than that of the ECLK. In other words, if a PLL is not the divider 20 , the frequencies of the final internal clocks ICLK0 ~ ICLK270 are not equal to the frequency of the external input clock ECLK.

As a result, a conventional phase-locked loop has the problem that if noise is affected by a supply voltage, this noise may cause the output final clock signals ICLK0, ICLK180, ICLK90, and ICLK270 to include error components. One reason for this is that the control voltage Vc is easily changed by an unstable supply voltage. The frequency of the VCO's output clock signals 16 depends on the voltage level of the control voltage Vc. Moreover, conventional PLLs may have the disadvantage of requiring a relatively long time before the lock operation is completed.

1B illustrates another conventional phase locked loop. The conventional phase locked loop in 1B contains partially the same elements as the one in 1A , In addition to one or more dividers 18-1 . 18-2 and one or more dividers 20 can the conventional phase-locked loop according to 1B continue one or more dividers 18-3 . 18-4 . 18-5 and 18-6 exhibit. As shown, the frequency of CLK and CLKB is eight times higher than that of ECLK, while the frequency of each of clocks iCLK0 ~ iCLK270 is four times higher than that of ECLK. Furthermore, the frequency of each of the clocks ICLK0 ~ ICLK315 is twice that of ECLK.

For example, when the frequency of ECLK is 1 GHz, the frequency of CLK and CLKB is 8 GHz, the frequency of iCLK0~iCLK270 is 4 GHz, and the frequency of ICIK0~ICLK315 is 2 GHz. Under low supply voltage conditions (eg, less than 2VDD), a conventional VCO 16 do not generate the output clocks CLK and CLKB at a frequency of 8 GHz.

Similar to the phase locked loop according to 1A depends on the phase locked loop of 1B the frequency of the VCO's output clock signals 16 from the voltage level of the control voltage Vc. Furthermore, the conventional PLL in 1B have the disadvantage that it takes a relatively long time before the locking operation is completed.

2 illustrates a conventional voltage controlled oscillator, such as VCO 16 in 1 , The conventional voltage controlled oscillator 16 can be a first ring oscillator 16-1 with one or more inverters I1, I2, I3 arranged in a loop configuration net, a second ring oscillator 16-2 comprising one or more inverters I4, I5, I6 arranged in a loop configuration (for example, the same configuration as the first ring oscillator) 16-1 ), and a latch circuit 16-3 comprising one or more inverters I7, I8 for latching CLK and CLKB.

The Frequency of the output clock CLK / CLKB may vary depending on the level of the Control voltage Vc are controlled. When the level of the control voltage Vc is raised, the frequency of the output clock CLK / CLKB elevated become. When the level of the control voltage Vc is lowered, can the frequency of the output clock CLK / CLKB be reduced.

3 illustrates a conventional delay locked loop having a phase detector (PD) 30 , a charge pump (CP) 32 , a loop filter (LP) 34 , a voltage-controlled delay line or delay line (VCDL) 36 , a selector and phase interpolator 38 , a control circuit (CC) 42 and a phase detector (PD) 40 may include. As in 3 shown, the voltage-controlled delay line (VCDL) generates 36 a plurality of clock signals CLK0, CLK90, CLK180, CLK270 having an identical phase difference between adjacent clock signals delayed in response to the control voltage Vc by a desired time from the external clock signal ECLK. In the in 3 Illustrated example generates the VCDL 36 four clock signals.

The selection and phase interpolation circuit 38 generates final internal clock signals ICLK0, ICLK90, ICLK180 and ICLK270 in response to a control signal CON after selecting two input clock signals and interpolating phases between the two selected clock signals. The control circuit (CC) 42 generates the control signal CON in response to the UP or DN signal.

The in 3 The conventional delay locked loop shown has a double loop configuration, with the first loop being detected by the phase detector (PD). 30 , the charge pump (CP) 32 , the loop filter (LP) 34 and the voltage-controlled delay line (VCDL) 36 and the second loop through the selection and phase interpolation circuit 38 , the control circuit (CC) 42 and the phase detector (PD) 40 is formed. A problem with the conventional delay locked loop according to 3 is that the loop lock time is relatively long.

4 illustrates an exemplary implementation of the voltage controlled delay line (VCDL) 36 in 3 , As in 4 shown, the voltage-controlled delay line (VCDL) 36 have four delay cells D1-D4. Each of the delay cells D1-D4 may output a corresponding clock signal CLK0-CLK270. The voltage-controlled delay line (VCDL) 36 outputs a feedback clock signal FCLK which is delayed from the external clock signal ECLK in response to the control voltage Vc.

As stated above, the control voltage Vc of a DLL can easily be changed by an unstable supply voltage. This causes the frequency of the output clock signals (CLK0-CLK270 and FCLK) of the voltage-controlled delay line VCDL 36 is also variable, which depends on the voltage level of the control voltage Vc. If the control voltage Vc includes noise, the output clock signals (CLK0, CLK270 and FCLK) will contain errors, such as phase errors. Moreover, as just mentioned, the conventional DLL has the disadvantage that the loop lock time is relatively long.

The US 6,617,936 B2 shows a phased-controlled oscillator.

The US 2004/0032300 A1 shows a multi-phase oscillator for generating a plurality of output signals organized in groups of four.

The US 5,565,817 A shows a ring oscillator with an accelerated charge or discharge of capacitors.

The US 6,570,420 B1 shows a programmable current source setting of a leakage current for a DLL.

The DE 698 05 628 T2 shows a synchronous clock generator with delay locked loop.

The DE 103 36 300 A1 shows a duty cycle correction delay control circuit and associated correction method.

The US 2003/0222694 A1 shows a method and a circuit for generating multi-phase clock signals.

The US 2004/0095195 A1 shows a phase locked loop with a deglitch circuit with a short lock time.

The DE 43 12 086 C2 shows a semiconductor memory device and an associated method of operation.

The US 2005/0140417 A1 shows a gene and a method for generating signals with variable delay.

Of the The invention is based on the technical problem of providing a clock generation circuit, a multi-phase or multi-phase clock generator, a memory element Method for generating clock signals and a method for locking indicate the phase, which is a reduced time to completion need the locking operation and which less vulnerable across from Fluctuations in the supply voltage are.

The Invention solves This problem by means of a clock generating circuit with the features of Patent claim 1 or 5, a multi-phase clock generator with the Features of claim 9, a memory element with the Features of claim 27, a method of generating of clock signals with the features of claim 28 and a Method for locking the phase with the features of the patent claim 29th

advantageous Embodiments of the invention are specified in the subclaims, the text of which is hereby incorporated by reference into the description will be unnecessary To avoid repeated text.

exemplary Embodiments of the present invention are directed to clock generating circuits, Method for generating clock signals and methods for locking the phase of a feedback clock signal based on an external clock signal.

exemplary Embodiments of the present invention are directed to multi-phase clock generators, the clock generating circuits and memory elements, the Have multi-phase clock generator.

exemplary Embodiments of the present invention are directed to storage systems and method for writing data to a memory and to Reading data from a memory comprising a plurality of memory elements contains.

exemplary Embodiments of the present invention are directed to clock generating circuits, Multiphase clock generators and memory elements that use a hyper-ring oscillator included.

exemplary Embodiments of the present invention are directed to clock generating circuits, Multiphase clock generators and memory elements containing one or more Have loop circuits.

exemplary Embodiments of the present invention are directed to clock generating circuits, Multiphase clock generators and memory elements that have a reduced Time to complete the lock operation.

exemplary Embodiments of the present invention are directed to clock generating circuits, Multiphase clock generators and memory elements that are less prone to fluctuations in a Supply voltage are.

exemplary Embodiments of the present invention are directed to clock generating circuits, which receive an external clock signal directly.

According to one exemplary embodiment of the present invention a clock generating circuit comprises an inverter which is an external clock signal receives directly and outputs an inverted external clock signal, M (where M is a integer ≥ 1 is) series connected loop circuits, wherein the first Loop circuit receives the inverted external clock signal, wherein each of the M or N loop circuits has n nodes (where n is an integer ≥ 2), where each of the M - 1 Loop circuits generate n internal intermediate clock signals, each at a corresponding one of the n nodes, wherein a frequency of the n internal intermediate clock signals a multiple of a frequency of the external Clock signal and the inverted external clock signal, and n Groups of inverters, each with M - 1 inverters connected in series , each of the M - 1 Inverter a corresponding internal intermediate clock signal from a preceding loop circuit receives and a corresponding outputs internal intermediate clock signal to a next loop circuit.

at another exemplary embodiment of the present invention The M loop circuits have a hyper ring oscillator.

at another exemplary embodiment of the present invention For example, each of the n groups of inverters M includes inverters that are in Are connected in series, and the clock generating circuit further comprises a (M + 1) th loop circuit connected in series with the M loop circuits is switched, wherein the (M + 1) -th loop circuit n nodes each of which has a corresponding internal intermediate clock signal from each of the Mth inverters receives and n internal clock signals generated, each at a corresponding one of the n nodes.

In another exemplary embodiment of the present invention Each of the (M + 1) -th loop circuits includes a plurality of loops.

In another exemplary embodiment of the present invention Each of the (M + 1) -th loop circuits includes a single loop.

In another exemplary embodiment of the present invention is n chosen from a group, which is formed of the values 4, 5, 6, 8, 9, 10, 12, 15 and 18.

In another exemplary embodiment of the present invention For example, each of the n groups of inverters M includes inverters that are in Series, wherein the clock generating circuit continues has a (M + 1) th loop circuit and an (M + 2) th Loop circuit and an (M + 1) -th group of inverters, wherein the (M + 1) th loop circuit and the (M + 2) th loop circuit in series with the M loop circuits and parallel to each other are arranged, wherein the (M + 1) -th loop circuit n nodes some of which have a corresponding internal intermediate clock signal from the Mth inverters receive, wherein the (M + 2) -th loop circuit has n nodes, some of which have a corresponding internal intermediate clock signal from the Mth inverters receive the n internal clock signals generate, each at a corresponding one of the n nodes, a first one Group of n inverters, each of which has a corresponding internal Receiving an intermediate clock signal from the (M + 1) -th loop circuit; a second group of n inverters, each of which has a corresponding one internal intermediate clock signal from the (M + 2) -th loop circuit receives; and a third group of n inverters, each of which outputs the corresponding inverter from the first group of n inverters and the second group of n inverters receive and n internal clock signals generated.

In another exemplary embodiment of the present invention a memory element comprises a memory cell array, a multi-phase clock generator, receiving an external clock signal and a feedback clock signal, and has at least one clock generating circuit directly at least n (where n is an integer ≥ 2 ) generates internal clock signals, a control signal generation circuit for receiving the at least n internal clock signals and for generating of p control signals (where p is an integer ≥ 2), at least one serial-to-parallel converter for receiving bits of a serial bit stream and for converting of the serial bit stream into a parallel bit stream entering the Memory cell array can be written in dependence from each of the p control signals, and at least one parallel-to-serial converter for receiving a parallel bit stream from the memory cell array and converting the parallel bitstream into a serial bitstream dependent on from each of the p control signals.

In another exemplary embodiment of the present invention includes a method of generating n internal clock signals (where n is an integer ≥ 2 is), directly receiving an external clock signal and Invert the external clock signal, a M-times (where M is a integer ≥ 1 is) phase interpolating the n internal intermediate clock signals to to generate the n internal clock signals.

In another exemplary embodiment of the present invention includes a method of locking the phase of a feedback clock signal In response to an external clock signal, receiving an external clock Clock signal and the feedback clock signal, outputting an up signal, when a phase of the external clock signal is one phase of the feedback clock signal leading, and outputting a down signal when a phase the external clock signal lags behind the phase of the feedback clock signal Generating at least one control signal in response to the up signal and the down signal and directly generating at least n (where n is an integer ≥ 4), internal clock signals, wherein the at least one control signal is a phase change controls at least one of the n internal clock signals, and a Generating the feedback clock signal from at least one of the n internal clock signals.

advantageous Embodiments of the invention, which are described in detail below and to facilitate the understanding of the invention above explained Embodiments of the prior art are shown in the drawing. It shows / shows:

1A a conventional phase locked loop;

1B another conventional phase locked loop;

2 a conventional voltage controlled oscillator;

3 a conventional delay locked loop;

4 an exemplary implementation of the conventional voltage-controlled delay line (VCDL) in 3 ;

5A a clock generating circuit according to an exemplary embodiment of the present invention, wherein N = 4;

5B an exemplary equivalent representation of the clock generating circuit in 5A ;

6A a clock generating circuit according to another exemplary embodiment of the present invention, wherein N = 4;

6B an exemplary equivalent representation of the clock generating circuit in 6A ;

7A a clock generating circuit having a single-loop or latch configuration according to another exemplary embodiment of the present invention, wherein N = 4;

7B an exemplary equivalent representation of the clock generating circuit in 7A ;

8th an exemplary equivalent representation of a clock generating circuit according to another exemplary embodiment of the present invention, wherein N = 5;

9 an exemplary equivalent representation of a clock generating circuit with a latch configuration according to another exemplary embodiment of the present invention, wherein N = 5;

10 an exemplary equivalent representation of a clock generating circuit according to another exemplary embodiment of the present invention, wherein N = 6;

11 an exemplary equivalent representation of a clock generating circuit with a latch configuration according to another exemplary embodiment of the present invention, wherein N = 6;

12 an exemplary equivalent representation of a loop circuit according to another exemplary embodiment of the present invention;

13 a multi-phase clock generator according to an exemplary embodiment of the present invention;

14A a multi-phase clock generator according to another exemplary embodiment of the present invention;

14B a multi-phase clock generator according to another exemplary embodiment of the present invention;

15A a multi-phase clock generator according to another exemplary embodiment of the present invention;

15B a multi-phase clock generator according to another exemplary embodiment of the present invention;

16 a phase detector according to another exemplary embodiment of the present invention;

17A - 17D a selection and interpolation circuit according to another exemplary embodiment of the present invention;

17E the relationship between different phases of clock signals for exemplary combinations of control values according to an exemplary embodiment of the present invention;

18 a control circuit according to an exemplary embodiment of the present invention;

19 a weighting control generator according to an exemplary embodiment of the present invention;

20 a selection control signal generator according to an exemplary embodiment of the present invention;

21 a charge pump and a loop filter according to another exemplary embodiment of the present invention;

22 a voltage controlled delay line (VCDL) according to an exemplary embodiment of the present invention;

23 a memory system having a multi-phase clock generator according to an exemplary embodiment of the present invention; and

24 a memory element with a multi-phase clock generator according to an exemplary embodiment of the present invention.

It It should be noted that an element, which as with a other element "connected" or "coupled" described is directly connected or coupled to the other element or the intermediate elements may be present. In contrast to this are then, if one element is "directly connected" or "directly" with another element coupled "described is, no intermediate elements available. Other formulations that used to describe the relationship between elements should be interpreted in the same way (for example, "between" versus "directly between "," adjacent "directly" adjacent ", etc.).

5A FIG. 10 shows a clock generating circuit according to an exemplary embodiment of the present invention including an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M} arranged in series, and N (where N is an integer ≥ 2) has groups of inverters INV _{1 ... N.}

As in 5A ₁ , each of the loop circuits LC _{1 ... M} N (where N is an integer ≥ 2) may include nodes, the node number being equal to the number of groups of inverters INV _{1 ... N.} In the exemplary embodiment shown in FIG 5A is shown, N = 4.

Each of the N groups of inverters INV _{1 ... N} includes M - 1 inverters, where M is the number of loop circuits LC _{1 ... M.} In the exemplary embodiment according to 5A is N = 4, and the four groups of inverters are labeled INV _{1 ... 4} . In the exemplary embodiment according to 5A The groups of inverters INV ₁ , INV ₂ , INV ₃ and INV ₄ each comprise M - 1 inverters represented as I9 _{1 ... (M-1)} , I10 _{1 ... (M-1)} , I11 _{1 .. (M-1)} and I12 _{1 ... (M-1) are} designated.

As in 5A 1, the inverter I0 directly receives an external clock signal ECLK and outputs an inverted external clock signal to the first loop circuit LC ₁ .

The first loop circuit LC ₁ generates N internal intermediate clock signals, each at a respective node, wherein a frequency of the N intermediate clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal. In the exemplary embodiment according to 5A the N (= 4) nodes are labeled A ₁ , B ₁ , C ₁ and D ₁ . As in 5A shown, the N intermediate internal clock signals from the nodes A _1, B _1, C ₁ and D ₁ off or in the inverters I9 _{1, 1} I10, I11 input ₁ and I12. ₁

As in 5A The loop circuit LC ₂ receives the output signals of the inverters I9 ₁ , I10 ₁ , I11 ₁ and I12 ₁ at nodes A ₂ , B ₂ , C ₂ and D _2, respectively. N intermediate internal clock signals off from the nodes A _2, B _2, C ₂ and D _2, and input to inverter I9 _2, I10 _2, I11 and I12 _{2. 2}

The Mth loop circuit LC _M receives the output signals of inverters I9 _(M-1) , I10 _(M-1) , I11 _(M-1) and I12 _(M-1) at nodes A _M , B _M , C _M and _M, respectively D _M and outputs clock signals CLK1, CLK2, CLK3 and CLK4, respectively.

As stated above, each loop circuit LC _{M has} N nodes, for example four nodes A, B, C and D, each of which generates an internal intermediate clock signal.

As in 5A As shown, the loop circuits LC _2-M are substantially the same as the loop circuit LC ₁ , except that the loop circuits LC _2-M do not receive an inverted internal clock signal.

As in 5A As shown, each loop circuit may include LC _M inverters I1-I8. The inverters I1-I8 of each of the loop circuits LC _M are arranged to form a first loop formed of inverters I1 _M -I4 _M , a second loop of inverters I1 _M , I2 _M and I7 _M , a third loop Inverters I3 _M , I4 _M and I8 _M , a fourth loop of inverters I2 _M , I3 _M and I6 _M , a fifth loop of inverters I7 _M and I8 _M , a sixth loop of inverters I5 _M and I6 _M and a seventh loop Inverters I1 _{M ,} I5 _M and I4 _M.

As stated above, a plurality of inverters I9 _{1 ... (M-1)} , I10 _{1 ... (M-1)} , I11 _{1 ... (M-1)} and I12 _{1 ... (M -1)} for each of nodes A _M , B _M , C _M and D _M of each of the loop circuits LC _M are connected in series with each other and generate a plurality of clock signals CLK1, CLK2, CLK3, CLK4 as in 5A shown.

If the external clock signal ECLK is input to the clock generating circuit is followed by the frequency of the internal clock signal CLK1, CLK2, CLK3 and CLK4 of that of the external clock signal ECLK. Furthermore is each of the internal clock signals with a phase difference of 90 ° between outputted to adjacent clock signals, d. H. CLK1 can be set as CLK0 CLK2 as CLK90, CLK3 as CLK180 and CLK4 as CLK270.

5B FIG. 12 is an exemplary equivalent representation of the clock generating circuit according to FIG 5A ,

As in 5B Node A ₁ receives the inverted external clock signal as an input signal as well as input signals from inverters I _{4 1} and I 7 ₁ . The node A ₁ supplies an output signal to inverters I1 ₁ and I9 ₁ . As a result, the node A ₁ receives three input signals and outputs two output signals.

Similarly, node B receives ₁ inputs from inverters I3 ₁ and I5 ₁ and provides an output to inverters I4 ₁ and I10 ₁ . As a result, the node B ₁ receives two input signals and outputs two output signals.

Node C ₁ receives inputs from inverters I _{2 1} and I 8 ₁ and provides an output to inverters I _{3 1} and I 11 ₁ . As a result, the node C ₁ also receives two input signals and outputs two output signals. Node D ₁ receives input signals from inverters I1 ₁ and I6 ₁ and supplies an output signal to inverters I2 ₁ and I12 ₁ . As a result, node D ₁ also receives two input signals and outputs two output signals.

Node A ₂ receives input signals from inverters I4 ₂ , I7 ₂ and I9 ₁ . The node A ₂ supplies an output signal to inverters I1 ₂ and I9 ₂ . As a result, the node A ₂ receives three input signals and outputs two output signals. Node B ₂ receives input signals from inverters I3 ₂ , I5 ₂ and I10 ₁ . The node B ₂ provides an output signal to inverters I4 ₂ and I10 ₂ . As a result, the node B ₂ receives three input signals and outputs two output signals.

Node C ₂ receives input signals from inverters I2 _2, I8 and I11 _{2. 1} The node C ₂ supplies an output signal to inverters I _{3 2} and I 11 ₂ . As a result, the node C ₂ receives three input signals and outputs two output signals. Node D ₂ receives input signals from inverters I1 ₂ , I6 ₂ and I12 ₁ . The node D ₂ provides an output signal to inverters I _{2 2} and I 12 ₂ . As a result, the node D ₂ receives three input signals and outputs two output signals.

The nodes A ₃ , A ₃ , C ₃ , D ₃ to A _M-1 , B _M-1 , C _M-1 and D _M-1 work in the same way as the nodes A ₂ , B ₂ , C described above ₂ , D ₂ . The nodes A _M , B _M , C _M , D _M receive comparable input signals as the above-described nodes A _M-1 , B _M-1 , C _M-1 , D _M-1 , and give internal clock signals CLK1, CLK2, CLK3 or CLK4 off.

As in the 5A and 5B ₂ , phase interpolation is performed at each of the nodes A ₁ , B ₁ , C ₁ , D ₁ to A _M , B _M , C _M , D _M. For example, at the node A _{1 of} the loop filter LC _1, the inverted external clock signal from the inverter I0 is combined and interpolated with two outputs from the inverters I4 ₁ and I7 ₁ to produce the two output signals supplied to the inverters I1 ₁ and I9 ₁ , Similarly, at node A ₂ of loop filter LC _2, the output of inverter I9 _{1 is} combined and interpolated with two output signals of inverters I4 ₂ and I7 ₂ to produce the two output signals supplied to inverters I1 ₂ and I9 ₂ , All other nodes A _{3 ... M} work in the same way.

At the node B of the loop filter ₁ LC _1, the output signals from inverters I3 and I5 _{1 1} are combined and interpolated to generate the two output signals, which are supplied to the inverters I4 ₁ and I10. ₁ Similarly, in node B _{2 of} the loop filter LC _2, the output of the inverter I10 _{1 is} combined and interpolated with two outputs of inverters I3 ₂ and I5 ₂ to produce the two output signals supplied to the inverters I4 ₂ and I10 ₂ , All other nodes B _{3 ... M} work in the same way.

At the node C _{1 of} the loop filter LC ₁ , the outputs of inverters I _{2 1} and I 8 _{1 are} combined and interpolated to produce the two output signals supplied to the inverters I _{3 1} and I 11 ₁ . Similarly, in node C ₂ of loop filter LC _2, the output of inverter I11 _{1 is} combined and interpolated with the two output signals of inverters I _{2 2} and I ₂ to produce the two output signals supplied to inverters I _{3 2} and I 11 ₂ become. All other nodes C _{3 ... M} work in the same way.

At the node D _{1 of} the loop filter LC ₁ , the outputs of inverters I1 ₁ and I6 _{1 are} combined and interpolated to produce the two output signals supplied to the inverters I2 ₁ and I12 ₁ . Similarly, at node D ₂ of loop filter LC _2, the output of inverter I12 _{1 is} combined and interpolated with the two outputs of inverters I1 ₂ and I6 ₂ to produce the two output signals supplied to inverters I2 ₂ and I12 ₂ become. All other nodes D _{3 ... M} work in the same way.

The phase difference between adjacent clock signals generated by the loop filter LC ₁ is approximately 90 °. The phase difference between adjacent clock signals generated by the loop filter LC ₂ is closer to exactly 90 °, compared to the loop filter LC ₁ . The phase difference between adjacent clock signals generated by loop filter LC ₃ is even closer to exactly 90 ° than to loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2, CLK3, CLK4 approaches closer and closer to exactly 90 ° as more loop filters LC _M are added to the clock generating circuit.

As stated above, the above-described phase interpolation is performed in each of the nodes when the external clock signal ECLK is input, and an internal clock signal latching operation is completed in a relatively short time as compared with the prior art. Furthermore, a clock generating circuit as shown in FIGS 5A and 5B is more robust in terms of power noise compared to conventional clock generating circuits.

6A FIG. 12 shows a clock generating circuit according to another exemplary embodiment of the present invention including an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M + 1} arranged in series, and N (where N is an integer ≥ 2) has groups of inverters INV _{1 ... N.}

As in 6A ₁ , each of the loop circuits LC _{1 ... M + 1} N (where N is an integer ≥ 2) may include nodes, the node number being equal to the number of groups of inverters INV _{1 ... N.} In the exemplary embodiment according to 6A N = 4. The inverter I0 which is M (where M is an integer ≥ 1) has loop circuits LC _{1 ... M + 1} arranged in series and N (where N is an integer ≥ 2) Groups of inverters INV _{1 ... N} may be arranged and operated as those in the 5A and 5B ,

The clock generating circuit according to 6A may further comprise a (M + 2) -th loop circuit LC _{M + 2 arranged} in parallel with the loop circuits LC _{1 ... M + 1} .

The internal arrangement of the loop circuits LC _{M + 1} and LC _{M + 2} may be the same as for the loop circuits LC _{1 ... M.}

As in 6A ₂ , some of the nodes of the loop circuit LC _{M + 1} receive input signals from inverters I9 _M , I10 _M , I11 _M and I12 _M. For example, receive as in 6A represented, nodes A _{M + 1} and C _{M + 1} input signals from inverters I9 _M and I11 _M. Furthermore, some of the nodes of the loop circuit LC _{M + 2} inputs of inverters I9 _{M, M} I10, I11 and I12 _{M M} received. For example, receive as in 6A shown, node B _{M + 2} and D _{M + 2} inputs of I10 _M and I12 _M.

The clock generating circuit according to 6A further comprises a first group of N inverters I13 _{M + 1} , I14 _{M + 1} , I15 _{M + 1} and I16 _{M + 1} , each of which receives an output signal from nodes A _{M + 1} , B _{M + 1} , C _{M + 1} and D _{M + 1} , and a second group of inverters I 13 _{M + 2} , I 14 _{M + 2} , I 15 _{M + 2,} and I 16 _{M + 2} , each of which receives an output of nodes A _{M + 2} , B _{M + 2} , C _{M + 2} and D _{M + 2} , respectively. Output signals of the first group of N inverters UI13 _{M + 1} , I14 _{M + 1} , I15 _{M + 1} and I16 _{M + 1} and the second group of N inverters I13 _{M + 2} , I14 _{M + 2} , I15 _{M + 2} and I16 _{M +2} are input to a third group of inverters I13, I14, I15 and I16, respectively, to generate internal clock signals CLK1, CLK2, CLK3 and CLK4, respectively.

6B FIG. 12 is an exemplary equivalent representation of the clock generation circuit in FIG 6A ,

As in the 6A and 6B In each of the nodes A ₁ , B ₁ , C ₁ , D ₁ to A _{M + 2} , B _{M + 2} , C _{M + 2} , D _{M + 2,} phase interpolation is performed. The phase difference between adjacent clock signals generated by the loop filter LC ₁ is about 90 °. The phase difference between adjacent clock signals, which are generated by the loop filter LC ₂ , is closer to exactly 90 ° in comparison with the loop filter LC ₁ . The phase difference between adjacent clock signals generated by the loop filter LC ₃ is even closer to exactly 90 ° than to the loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2, CLK3, CLK4 is closer to exactly 90 ° as more loop filters LC _m are added to the clock generating circuit.

As stated above, the above-described phase interpolation is performed in each node when the external clock signal ECLK is input, and the internal clock signal latching operation is completed in a relatively short time as compared with the prior art. In addition, a clock generating circuit as shown in the 6A and 6B is more robust in terms of power noise compared to conventional clock generating circuits.

7A FIG. 10 shows a clock generating circuit according to another exemplary embodiment of the present invention including an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M} arranged in series, and N (where N is an integer ≥ 2) groups of inverters INV _{1 ... N.} The exemplary embodiment according to 7A is similar to the exemplary embodiment according to 5A with the exception that the internal configuration of each of the loop circuits LC _{1 ... M} includes a number of N inverters arranged as a latch circuit. In the exemplary embodiment according to 7A is N = 4, and thus each loop circuit LC _{1 ... M} includes four inverters I1, I2, I3 and I4 and a single loop.

7B FIG. 12 is an exemplary equivalent representation of the clock generating circuit according to FIG 7A ,

As in the 7A and 7B In each of the nodes A ₁ , B ₁ , C ₁ , D ₁ to A _M , B _M , C _M , D _M, phase interpolation is performed. The phase difference between adjacent clock signals generated by the loop filter LC ₁ is approximately 90 °. The phase difference between adjacent clock signals, which are generated by the loop filter LC ₂ , is closer to exactly 90 ° in comparison with the loop filter LC ₁ . The phase difference between adjacent clock signals generated by the loop filter LC ₃ is even closer to exactly 90 ° than to the loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2, CLK3, CLK4 approaches closer to exactly 90 ° as more loop filters LC _m are added to the clock generating circuit.

As described above, the phase interpolation in each node becomes as described above is performed when the external clock signal ECLK is applied, and an internal clock signal latching operation is completed in a relatively short time as compared with the prior art. In addition, a clock generating circuit as shown in the 7A and 7B is more robust in terms of power noise compared to conventional clock generating circuits.

8th FIG. 10 shows an equivalent circuit of a clock generation circuit according to another exemplary embodiment of the present invention, which includes an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M} arranged in series, and N (where N is an integer ≥ 2) has groups of inverters INV _{1 ... N.}

As in 8th ₁ , each of the loop circuits LC _{1... M may have} a number of N (where N is an integer ≥ 2) nodes, the number of nodes being equal to the number of groups of inverters INV ₁ . In the exemplary embodiment according to 8th is N = 5.

As in 8th ₁ , each of the N groups of inverters INV includes _{1 ... N} M - 1 inverters, where M is the number of loop circuits LC _{1 ... M.} In the exemplary embodiment according to 8th N = 5, and the five groups of inverters are labeled INV _{1 ... 5} . In the exemplary embodiment according to 8th The groups of inverters INV ₁ , INV ₂ , INV ₃ , INV ₄ and INV ₅ each comprise _M-1 inverters represented as I11 _{1 ... (M-1)} , I12 _{1 ... (M-1)} , I13 _{1 ... (M-1)} , I14 _{1 ... (M-1)} and I15 _{1 ... (M-1) are} designated.

As in 8th 1, the inverter I0 directly receives an external clock signal ECLK and outputs an inverted external clock signal to the first loop circuit LC ₁ .

As in 8th ₁ , the first loop circuit LC generates ₁ N internal intermediate clock signals, each at a corresponding node, wherein a frequency of the N internal intermediate clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal. In the exemplary embodiment according to 8th the N (= 5) nodes are labeled A ₁ , B ₁ , C ₁ , D ₁ and F ₁ . As in 8th 9, the N internal intermediate clock signals from nodes A ₁ , B ₁ , C ₁ , D ₁ and E _{1 are} output and input to inverters I11 ₁ , I12 ₁ , I13 ₁ , I14 ₁ and I15 ₁ , respectively.

As in 8th ₂ , the second loop circuit LC ₂ receives the output signals of inverters I11 ₁ , I12 ₁ , I13 ₁ , I14 _1, and I15 ₁ at nodes A ₁ , B ₁ , C ₁ , D _1, and E _1, respectively. N internal intermediate clock signals are output from nodes A ₁ , B ₁ , C ₁ , D ₁ and E ₁ and input to inverters I11 ₂ , I12 ₂ , I13 ₂ , I14 ₂ and I15 ₂ , respectively.

As in 8th 5, the Mth loop circuit LC _M receives the output signals from inverters I11 _(M-1) , I12 _(M-1) , I13 _(M-1) , I14 _(M-1), and I15 _(M-1) at nodes A _M , B _{M M} , C _M , D _M and E _M and outputs clock signals CLK1, CLK2, CLK3, CLK4 and CLK5, respectively.

As stated above, each loop circuit LC _{M has} a number of N nodes, for example five nodes A, B, C, D and E, each of which generates an internal intermediate clock signal.

As in 8th ₁ , the loop circuits LC _2-M substantially correspond to the loop circuit LC ₁ , except that the loop circuits LC _2-M do not receive an inverted external clock signal.

As in 8th As shown, each loop circuit may include LC _M inverters I1-I10. As above with reference to 5A As described, the inverters I1-I10 of each of the loop circuits LC _{M may} be arranged to form a plurality of loops, each of which is formed of a subset of the inverters I1-I10.

As stated above, a plurality of inverters I11 _{1 ... (M-1)} , I12 _{1 ... (M-1)} , I13 _{1 ... (M-1)} , I14 _{1 ... (M-) 1)} , I15 _{1 ... (M-1)} for each of the nodes A _M , B _M , C _M , D _M and E _M of each of the loop circuits LC _M in series with each other and generate a plurality of clock signals CLK1 , CLK2, CLK3, CLK4 and CLK5, as in 8th shown.

If the external clock signal ECLK is input to the clock generating circuit the frequencies of the internal clock signals CLK1, CLK2, CLK3, CLK4 and CLK5 of that of the external clock signal ECLK. Farther is each of the internal clock signals with a phase difference of 72 ° between outputted to adjacent clock signals, d. H. CLK1 can be set as CLK0 CLK2 can be set as CLK72, CLK3 can be set as CLK144 CLK4 can be set as CLK216 and CLK5 can be used as CLK288 be set.

9 FIG. 12 is an exemplary equivalent representation of a single loop or latched clock generation circuit according to another exemplary embodiment of the present invention, where N = 5.

As in 8th and 9 is shown, phase interpolation is performed in each of the nodes A ₁ , B ₁ , C ₁ , D ₁ , E ₁ to A _M , B _M , C _M , D _M , E _M. The phase difference between adjacent clock signals generated by the loop filter LC ₁ is approximately 72 °. The phase difference between adjacent clock signals generated by the loop filter LC ₂ is closer to exactly 72 °, compared to the loop filter LC ₁ . The phases difference between adjacent clock signals generated by the loop filter LC ₃ is even closer to exactly 72 ° than to the loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2, CLK3, CLK4, CLK5 approaches to exactly 72 ° when more loop filter LC _m are added to the clock generation circuit.

As stated above, the phase interpolation in each of the nodes is performed as described above when the external clock signal ECLK is applied, and an internal clock signal latching operation is completed after a relatively short time as compared with the prior art. In addition, a clock generating circuit as shown in the 8th and 9 is more robust in terms of power noise compared to conventional clock generating circuits.

10 FIG. 10 shows an equivalent circuit of a clock generation circuit according to another exemplary embodiment of the present invention, which includes an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M} arranged in series, and N (where N is an integer ≥ 2) has groups of inverters INV _{1 ... N.}

As in 10 ₁ , each of the loop circuits LC _{1... M may have} a number of N (where N is an integer ≥ 2) nodes, the number of nodes being equal to the number of groups of inverters INV ₁ . In the exemplary embodiment according to 10 is N = 6.

As in 10 ₁ , each of the N groups of inverters INV _{1... N} M - 1 has inverters, where M is the number of loop circuits LC _{1... M.} In the exemplary embodiment according to 10 is N = 6, and the six groups of inverters are labeled INV _{1 ... 6} . In the exemplary embodiment according to 10 The groups of inverters INV ₁ , INV ₂ , INV ₃ , INV ₄ , INV ₅ and INV ₆ each have M - 1 inverters connected to I 17 _{1 ... (M + 1)} , I18 _{1 ... (M-). 1)} , I19 _{1 ... (M-1)} , I20 _{1 ... (M-1)} , I21 _{1 ... (M-1)} and I22 _{1 ... (M-1),} respectively.

As in 10 1, the inverter I0 directly receives an external clock signal ECLK and outputs an inverted external clock signal to the first loop circuit LC ₁ .

As in 10 ₁ , the first loop circuit LC generates ₁ N internal intermediate clock signals, each at a corresponding node, wherein a frequency of the N internal intermediate clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal. In the exemplary embodiment according to 10 For example, the N (= 6) nodes are labeled A ₁ , B ₁ , C ₁ , D ₁ , E _1, and F ₁ . As in 8th are shown, the N internal intermediate clock signals of the nodes A ₁ , B ₁ , C ₁ , D ₁ , E ₁ and F ₁ off and in inverters I17 ₁ , I18 ₁ , I19 ₁ , I20 ₁ , I21 ₁ and I22 ₁ entered.

As in 10 ₂ , the second loop circuit LC ₂ receives the output signals of inverters I17 ₁ , I18 ₁ , I19 ₁ , I20 ₁ , I21 _1, and I22 ₁ at nodes A ₂ , B ₂ , C ₂ , D ₂ , E _2, and F _2, respectively. N internal intermediate clock signals are output from nodes A ₂ , B ₂ , C ₂ , D ₂ , E ₂ and F ₂ and input to inverters I17 ₂ , I18 ₂ , I19 ₂ , I20 ₂ , I21 ₂ and I22 ₂ , respectively.

As in 10 The Mth loop circuit LC _M receives the output signals from inverters I17 _(M-1) , I18 _(M-1) , I19 _(M-1) , I20 _(M-1) , I21 _(M-1), respectively. I22 _(M-1) at nodes A _M , B _M , C _M , D _M , E _M and F _M and outputs clock signals CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6, respectively.

As stated above, each loop circuit LC _{M has} a number of N nodes, for example six nodes A, B, C, D, E and F, each of which generates an internal intermediate clock signal.

The loop circuits LC _2-M are substantially similar to the loop circuit LC ₁ , except that the loop circuits LC _2-M do not receive an inverted external clock signal.

As in 10 As shown, each loop circuit may include LC _M inverters I1-I18. As in 10 As shown, the inverters I1-I18 of each of the loop circuits LC _M are arranged to form a plurality of loops, each of which is formed of a subset of the inverters I1-I18.

As stated above, a plurality of inverters I17 _(M-1) , I18 _(M-1) , I19 _(M-1) , I20 _(M-1) , I21 _(M-1) and I22 _{(M-1) are.} for each of the nodes A _M , B _M , C _M , D _M , E _M and F _M of each of the loop circuits LC _M are connected in series with each other and generate a plurality of clock signals CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6, as in 10 shown.

If the external clock signal ECLK is input to the clock generating circuit the frequencies of the internal clock signals CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6 of those of the external clock signal ECLK. Furthermore, each of the internal clock signals becomes a phase difference from 60 ° between outputted to adjacent clock signals, d. H. CLK1 can be set as CLK0 CLK2 can be set as CLK60, CLK3 can be used as CLK120 be set, CLK4 can be set as CLK180, CLK5 can be set as CLK240 and CLK6 be set as CLK300.

As in 10 shown becomes a phase in terpolation performed in each of the nodes A ₁ , B ₁ , C ₁ , D ₁ , E ₁ and F ₁ to A _M , B _M , C _M , D _M , E _M and F _M.

The phase difference between adjacent clock signals generated by the loop filter LC ₁ is approximately 60 °. The phase difference between adjacent clock signals generated by the loop filter LC ₂ is closer to exactly 60 °, compared to the loop filter LC ₁ . The phase difference between adjacent clock signals generated by the loop filter LC ₃ is even closer to exactly 60 ° than to the loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2 CLK4, CLK5 and CLK6 approaches, CLK3, closer to exactly 60 ° to when more loop filter LC _m are added to the clock generation circuit.

As stated above, the above-described phase interpolation is performed in each of the nodes when the external clock signal ECLK is applied, and an internal clock signal latching operation is completed after a relatively short time as compared with the prior art. In addition, a clock generation circuit as shown in 10 is more robust in terms of power noise compared to conventional clock generating circuits.

11 FIG. 10 shows an equivalent circuit of a clock generation circuit according to another exemplary embodiment of the present invention, which includes an inverter I0, M (where M is an integer ≥ 1) loop circuits LC _{1... M} arranged in series, and N (where N is an integer ≥ 2) has groups of inverters INV _{1 ... N.} The exemplary embodiment of 11 is similar to the exemplary embodiment according to 10 with the exception that the internal configuration of each of the loop circuits LC _{1... M has} a number of N inverters arranged as a latch circuit. In the exemplary embodiment according to 11 is N = 6, and thus each loop circuit LC _{1 ... M has} six inverters I1, I2, I3, I4, I5 and I6 and a single loop.

As in 11 In each of nodes A ₁ , B ₁ , C ₁ , D ₁ , E ₁ and F ₁ to A _M , B _M , C _M , D _M , E _M and F _M, phase interpolation is performed. The phase difference between adjacent clock signals generated by the loop filter LC ₁ is approximately 60 °. The phase difference between adjacent clock signals generated by the loop filter LC ₂ is closer to exactly 60 ° in comparison with the loop filter LC ₁ . The phase difference between adjacent clock signals generated by the loop filter LC ₃ is even closer to exactly 60 ° than to the loop filter LC ₂ . As a result, the phase difference of the internal clock signal CLK1, CLK2, CLK3, CLK4, CLK5, CLK6 approaches closer to at exactly 60 ° when more loop filter LC _m are added to the clock generation circuit.

As stated above, the above-described phase inpolation is performed in each of the nodes when the external clock signal ECLK is input, and an internal clock signal latching operation is completed in a relatively short time as compared with the prior art. In addition, a clock generation circuit as shown in 11 is more robust in terms of power noise compared to conventional clock generating circuits.

12 FIG. 10 is an exemplary equivalent representation of a loop circuit according to another exemplary embodiment of the present invention, illustrating a plurality of inverters, eight (8) nodes A-H and clock signals ICLK0, ICLK45, ICLK90, ICLK135, ICLK180, ICLK225, ICLK270 and ICLK315. In an exemplary embodiment, the phases of nodes A-H may differ by 45 °. In an exemplary embodiment according to 12 For example, each of the nodes A-H may receive four input signals and output three output signals.

As described above, a clock generating circuit according to exemplary embodiments of the present invention may have a serial configuration such as those in FIGS 5A . 5B . 7A . 7B and 8th - 11 is shown, or a serial-parallel configuration, such as in the 5A and 5B is shown.

As described above, a loop circuit according to exemplary embodiments of the present invention may have a multiple loop configuration, such as in FIGS 5A . 5B . 6A . 6B . 8th . 10 and 12 or a single-loop or latch configuration, such as in the 7A . 7B . 9 and 11 is shown. Furthermore, a loop circuit according to exemplary embodiments of the present invention may include N nodes, where N is an integer ≥ 2, for example, 4, 5, 6, 8, 9, 10, 12, 15, or 18. In addition, a clock generation circuit according to FIG exemplary embodiments of the present invention include any combination of clock generation circuit configurations, loop circuit configurations, and node numbers N.

13 FIG. 12 shows a multi-phase clock generator according to an exemplary embodiment of the present invention, which may include any of the clock generating circuits which with reference to the above 5A - 12 have been described.

As shown, the multi-phase clock generator according to 13 a clock generation circuit (CGC) 50 , a phase change circuit (PMC) 52 , a phase detector (PD) 56 and / or a control signal generator (CSG) 58 exhibit. The clock generation circuit (CGC) 50 receives an external clock, for example, the above-described clock ECLK, and generates N first internal clock signals such as CLK1, CLK2, CLK3, CLK4 in accordance with 5A - 7B as N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270'. CLK0 ', CLK90', CLK180 ', CLK270' have the same frequency as ECLK.

The phase change circuit (PMC) 52 receives the N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' and at least one control signal CS from the control signal generator (CSG) 58 as input signals and generates N second clock signals ICLK0, ICLK90, ICLK180, ICLK270. Any of the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 may be used as a feedback signal applied to the phase detector (PD). 56 is output, as explained below.

The phase detector (PD) 56 receives the external clock signal ECLK and one of the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 as a feedback clock signal or feedback clock signal DCLK, and outputs an UP signal when a phase of the signal ECLK leads one phase of the feedback clock signal DCLK, and outputs a DOWN Signal when the phase of the ECLK signal lags behind the phase of the feedback clock signal DCLK.

The control signal generator (CSG) 58 receives the UP signal and the DOWN signal from the phase detector (PD) 56 and supplies the at least one control signal CS to the phase change circuit (PMC) 52 out.

14A shows a multi-phase clock generator according to another exemplary embodiment of the present invention, which may further include any of the clock generating circuits described above with reference to FIGS 5A - 12 have been described.

As shown, the multi-phase clock generator according to 14A continue a multiplier (MP) 54 and a divider (DIV) 60 , the phase change circuit (PMC) 52 includes a selection and phase interpolation circuit (SN / PI) 521 , and the control signal generator (CSG) 58 comprises a control circuit (CC) 581 , In an exemplary embodiment according to 14A the at least one control signal comprises selection signals S1, S2 and a weighting signal W.

The N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' have identical phase differences (90 °) between adjacent clock signals. The selection and phase interpolation circuit (SN / PI) 521 selects two clock signals among the N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' in response to the selection signals S1, S2 and interpolates the phases of the two selected clock signals in response to the weighting signal W by N second internal clock signals CLK0, CLK90, CLK180, CLK270 which are synchronized with the signal ECLK.

The multiplier (MP) 54 multiplies a frequency of the second internal clock signals CLK0, CLK90, CLK180, CLK270 to generate the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 having a higher frequency than the second internal clock signals CLK0, CLK90, CLK180, CLK270. For example, the signal ECLK, the N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' and the second internal clock signals CLK0, CLK90, CLK180, CLK270 may have a frequency of 1 GHz, whereas the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 may have a frequency of XGHz (where X is an integer> 1).

The control circuit (CC) 581 generates the selection signals S1, S2 and the weighting signal W as a function of the UP or DOWN signals from the phase detector (PD) 56 , The divider (DIV) 60 divides a frequency of the one of the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 selected as the feedback signal from X GHz (where X is an integer> 1) down to the frequency of the signal ECLK. The output signal of the divider (DIV) 60 is referred to as the feedback clock DCLK in the phase detector (PD) 56 entered.

14B shows a multi-phase clock generator according to another exemplary embodiment of the present invention, which may further include any of the clock generating circuits described above with reference to FIGS 5A - 12 have been described.

As shown, the multi-phase clock generator according to 14B not the multiplier (MP) 54 or the divider (DIV) 60 , In this way, the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 have the same frequency as the signal ECLK.

As in the 14A and 14B shown, For example, instead of a loop configuration circuit, a multi-phase clock generator according to exemplary embodiments of the present invention may include a clock generating circuit formed of a phase detector, a charge pump, a loop filter, and / or a voltage-controlled delay line, as shown in FIGS 1A and 1B are shown. In this way, when an external clock signal ECLK is input, a plurality of clock signals CLK0 ', CLK90', CLK180 ', CLK270' can be generated at a higher speed than in the prior art, wherein the plurality of clock signals have the same frequency as the signal ECLK together with a desired phase difference (eg 90 °) between adjacent clock signals. As a result, the lockup time in a multi-phase clock generator may be reduced in accordance with exemplary embodiments of the present invention.

Farther an external clock signal ECLK is directly input to a clock generation circuit according to exemplary Embodiments of the present invention entered so that the Plurality of clock signals CLK0 ', CLK90 ', CLK180', CLK270 'compared to the State of the art through changes supply voltage caused by noise less impaired become. In this way, a clock generating circuit according to exemplary Embodiments of the present invention provide more precise clock signals with less or spend without error.

15A shows a multi-phase clock generator according to another exemplary embodiment of the present invention, which may further include any of the clock generating circuits described above with reference to FIGS 5A - 12 have been described.

As shown, the multi-phase clock generator according to 15A continue a multiplier (MP) 84 and a divider (DIV) 92 on, the phase change circuit (PMC) 52 contains a voltage-controlled delay line (VCDL) 82 instead of the selection and phase interpolation circuit 52 according to the 14A and 14B , and the control signal generator (CSG) 58 includes a charge pump 88 and a loop filter 90 instead of the control circuit (CC) 581 according to the 14A and 14B , In the exemplary embodiment according to 15A the at least one control signal contains the control voltage Vc.

The N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' have identical phase differences (90 °) between adjacent clock signals. The voltage-controlled delay line (VCDL) 82 sets a delay time of the first internal clock signals (CLK0'-CLK270 ') to generate second internal clock signals (CLK0-CLK270) in synchronization with the external clock signal ECLK in response to the control voltage Vc.

The multiplier (MP) 54 multiplies a frequency of the second internal clock signals CLK0, CLK90, CLK180, CLK270 to generate the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 having a higher frequency than the second internal clock signals CLK0, CLK90, CLK180, CLK270. For example, the signal ECLK, the N first internal clock signals CLK0 ', CLK90', CLK180 ', CLK270' and the second internal clock signals CLK0, CLK90, CLK180, CLK270 may have a frequency of 1 GHz, whereas the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 may have a frequency of X GHz (where X is an integer> 1).

The control signal generator (CSG) 58 which is the charge pump 88 and the loop filter 90 generates the control voltage Vc in response to the UP or DOWN signals from the phase detector (PD) 86 , The divider (DIV) 92 divides a frequency of the one of the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 selected as the feedback signal from X GHz (where X is an integer> 1) back down to the frequency of the signal ECLK. The output signal of the divider (DIV) 92 is referred to as the feedback clock DCLK in the phase detector (PD) 86 entered.

15B shows a multi-phase clock generator according to another exemplary embodiment of the present invention, which may further comprise any of the clock generating circuits described above with reference to FIGS 5A - 12 have been described.

As shown, the multi-phase clock generator requires according to 15B not the multiplier (MP) 84 or the divider (DIV) 92 , In this way, the N second clock signals ICLK0, ICLK90, ICLK180, ICLK270 have the same frequency as the signal ECLK.

As in the 15A and 15B 10, a multi-phase clock generator according to exemplary embodiments of the present invention may include a clock generating circuit instead of a loop configuration circuit which may be formed of a phase detector, a charge pump, a loop filter, and / or a voltage-controlled delay line such as those in FIGS 1A and 1B shown. In this way, when an external clock signal ECLK is input, a plurality of clock signals CLK0 ', CLK90', CLK180 ', CLK270' of higher Ge speed are generated as in the prior art, wherein the plurality of clock signals may have the same frequency as the signal ECLK together with a desired phase difference (for example 90 °) between adjacent clock signals. As a result, the lockup time in a multi-phase clock generator may be reduced in accordance with exemplary embodiments of the present invention.

Furthermore an external clock signal ECLK is directly input to a clock generation circuit according to exemplary Embodiments of the present invention entered so that the Plurality of clock signals CLK0 ', CLK90 ', CLK180', CLK270 'compared to the State of the art through changes supply voltage caused by noise less impaired become. In this way, a clock generating circuit according to exemplary Embodiments of the present invention provide more precise clock signals with less or spend without error.

16 shows a phase detector according to another exemplary embodiment of the present invention, for example, the phase detector 56 . 86 with reference to the above 13 - 15B has been described.

The phase detector 56 . 86 may comprise two or more flip-flops DF1, DF2 and a NAND gate NA. A voltage VCC is provided as an input to both flip-flops DF1, DF2. The external clock signal ECLK is supplied as a clock signal for flip-flop DF1, and the feedback clock DCLK, for example, from the phase change circuit 52 in 13 , the selection and phase interpolation circuit 421 in 14A , the divider 60 in 14B , the voltage-controlled delay line (VCDL) 82 in 15A , the divider 92 in 15B is supplied as the clock for the flip-flop DF2. The stored data output Q of the flip-flop DF1 supplies the UP signal, and the stored data output Q of the flip-flop DF2 supplies the DOWN signal.

Of the Output Q for stored data of the flip-flop DF1 and the output Q for stored data of the flip-flop DF2 provide the inputs to the NAND gate NA, and the The result of the NAND operation is applied to flip-flop DF1 and flip-flop DF2 back delivered.

The phase detector 56 . 86 measures a phase difference between the external clock ECLK and the feedback clock DCLK and generates the UP or DN control signals, for example for the control circuit (CC) 581 to generate the selection signals S1, S2 and the weighting signal W, or for the charge pump 88 to the loop filter 90 to load and unload. The control circuit (CC) 581 can set the selection signals S1, S2 and the weighting signal W, and the charge pump 88 can set the control voltage (Vc), depending on UP or DN control signals.

17A - 17D show a selection and phase interpolation circuit according to another exemplary embodiment of the present invention, for example, the selection and phase interpolation circuit 521 , referring to the above 14A - 14B has been described.

If a first control signal S1, for example, by the control circuit (CC) 581 of the 14A - 14B is supplied with a low level, a first selection circuit M1 outputs first and second first internal clock signals CLK0 'and CLK90'. When the first control signal S1 has a high level, the first selection circuit M1 outputs third and fourth first internal control signals CLK180 'and CLK270'.

If a second control signal S2 has a low level a second selection circuit M2 second and third first internal Clock signals CLK90 'and CLK180 'off. If the second control signal S2 has a high level, gives the second Selection circuit M2 fourth and first internal clock signals CLK270 'and CLK0' off. As described above, to lead the first selection circuit M1 and the second selection circuit M2 a rough phase selection by.

Of the Phase Interpolator (PI) outputs second internal clock signals CLK0 and CLK90 or second clock signals ICLK0 and ICLK90 after interpolating two first internal clock signals from the selection circuits M1 and M2 dependent on from the weighting signal W.

If the first control signal S1 has a low level, gives the first selection circuit M1 outputs third and fourth first internal clock signals CLK180 'and CLK270', and when the first control signal S1 has a high level, gives the first Selection circuit M1 first and second internal clock signals CLK0 'and CLK90' off.

When the second control signal S2 has a low level, the second selection circuit M2 outputs fourth and first internal clock signals CLK270 'and CLK0', and when the second control signal S2 has a high level, the second selection circuit M2 outputs second and third first internal clock signals CLK90 'and CLK180' off. Each phase interpolation PI indicates second internal clock signals CLK180 and CLK270 or second clock signals ICLK180 and ICLK270 after interpolation two selected clock signals of the selection circuits M1 and M2 in response to the weighting signal W from. As described above, the phase interpolator (PI) performs fine or accurate phase interpolation.

The operation of the selection and phase interpolation circuit 521 will be described below in connection with the description of the weighting control generator 72 in 19 described in more detail.

17E shows the relationship between different phases of the signals ECLK, CLK0 ', CLK90', CLK180 'and CLK270' for all combinations of values generated by the control signal generator 58 according to 13 to be delivered.

18 shows a control circuit according to another exemplary embodiment of the present invention, for example the control circuit (CC) 581 , the above in conjunction with the 14A - 14B has been described.

A select signal generator (SSG) 70 performs an UP or UP counting operation in response to a first selection control signal SUP and a down-counting operation in response to a second selection control signal SDN.

Under the example assumption that the initial value of S1, S2 is "00", the value of S1, S2 may be changed in an order "10" → "11" → "01" depending on the activated SUP signal. When the SDN signal is activated, the value of S1, S2 may be changed in an order of "01" → "11" → "10". The control signals can be sent to the selection and phase interpolation circuit (SN / PI). 521 of the 14A - 14B to be delivered.

A Weight Control Generator (WCG) 72 generates a first weighting signal WUP in response to the UP signal from the phase detector (PD) 56 . 86 and generates a second weighting control signal WDN in response to the DN signal from the phase detector (PD) 56 . 86 when the value of S1, S2 becomes "00" and "11", respectively.

Furthermore, the weighting control generator (WCG) generates 72 the second weighting control signal WDN in response to the UP signal from the phase detector (PD) 56 . 86 and generates the first weighting control signal WUP in response to the DN signal from the phase detector (PD) 56 . 86 when the value of S1, S2 becomes "01" and "10", respectively. A weighting signal generator (WSG) 74 performs an up-counting operation in response to an UP signal and a down-counting operation in response to a WDN signal and outputs the weighting signal W. The weighting signal W may be formed of a plurality of bits.

A weighting minimum / maximum detector (WD) 76 generates a first weighting detection signal (WMAX) when all the bits of the weighting signal W are high, for example "111 ... 11", and generates a second weighting detection signal WMIN when all the bits of the weighting signal W are low, for example "000 ... 00" , The first weighting detection signal WMAX and the second weighting detection signal WMIN are input to a selection control signal generator (SCSG) along with the first weighting control signal WUP and the second weighting control signal WDN. 78 which generates the first selection control signal SUP and the second selection control signal SDN and sends them to the selection signal generator (SSG). 70 supplies.

19 shows a weighting control generator (WCG), for example the weighting control generator (WCG) 72 according to 18 in accordance with an exemplary embodiment of the present invention. The Weight Control Generator (WCG) 72 includes an exclusive-OR (XOR) gate, an inverter I1, 2 ^S AND gate and OR gate S, where S is equal to the number of the selection signals. In exemplary embodiments for the above indications, S = 2, and thus the weighting control generator (WCG) comprises 72 according to 19 four AND gates AND1-AND4 and two OR gates OR1-OR2.

The two selection signals S1, S2 from the control circuit (CC) 581 are processed by the XOR gate by means of an XOR operation, and the result is inverted by the inverter I1. The output of the XOR gate is input as an input to two of the four AND gates AND1-AND4. The output of the inverter I1 is input as an input to the other two two of the four AND gates AND1-AND4. The UP signal from the phase detector (PD) 56 is also input as an input to two of the four AND gates AND1-AND4. The DOWN signal from the phase detector (PD) 56 is input as an input to the other two two of the four AND gates AND1-AND4.

The output signals of the four AND gates AND1-AND4 are subjected to a logical OR operation in the two OR gates OR1-OR2. The output of the OR gates OR1 and OR2 provides the first weighting control signal WUP and the second weighting control signal WDN, respectively, to the weighting signal generator (WSG). 74 and the selection signal generator (SSG) 70 according to 18 be issued.

20 shows a selection control signal generator according to another exemplary embodiment of the present invention, for example the selection control signal generator (SCSG) 78 that related with above 18 has been described.

The selection control signal generator (SCSG) 78 comprises two AND gates AND5-AND6 and two OR gates OR3-OR4. A pair of AND / OR gates, AND5-OR3, receives the first weight detection signal WMAX and the second weight detection signal WMIN from the weighting minimum / maximum detector (WD). 76 and the first weighting control signal WUP from the weighting control generator (WCG) 72 and generates a first selection control signal (SUP).

The other pair of AND / OR gates, OR4-AND6, receives the first weighting detection signal WMAX and the second weighting detection signal WMIN from the weighting minimum / maximum detector (WD). 76 and the second weighting control signal WDN from the weighting control generator (WCG) 72 and generates a second selection control signal SDN.

The first selection control signal SUP is activated when the first weight detection signal WMAX and the first weight control signal WUP are activated or when the second weight detection signal WMIN is activated. The second selection control signal SDN is activated when the first weighting recognition signal WMAX and the second weighting detection signal WMIN are activated or when the second weighting control signal WDN is activated. The first selection control signal SUP or the second selection control signal SDN are applied to the selection signal generator (SSG). 70 in 18 delivered.

21 shows a charge pump and a loop filter according to another exemplary embodiment of the present invention, for example, the charge pump 88 and the loop filter 90 that are related to the above 15A - 15B have been described.

The charge pump 88 may comprise a first current source I1, a second current source I2, a PMOS transistor P1 and an NMOS transistor N1. The loop filter 90 may comprise a first capacitor C1, a second capacitor C2 and a resistor R.

When an inverted UP signal UPB is activated, an output terminal is charged by the first current source I1 and by means of the loop filter 90 filtered, so that the control voltage Vc increases.

When an inverted DN signal is activated, an output terminal is charged by the second current source I2 and by the low-pass filter 90 filtered, so that the control voltage Vc decreases. Upon completion of a latching operation, the PMOS transistor P1 and the NMOS transistor N1 are turned off so that the control voltage Vc maintains the desired voltage value.

22 shows a voltage-controlled delay line (VCDL) in dependence on a further exemplary embodiment of the present invention, for example the voltage-controlled delay line (VCDL) 82 , the above in conjunction with the 15A - 15B has been described.

The voltage-controlled delay line (VCDL) 82 may comprise a plurality of variable delay lines VD1-VD4 (for N = 4) each including a plurality of delay cells D1-D4. Each of the plurality of variable delay lines VD1-VD4 and each of the plurality of delay cells D1-D4 is controlled by the control voltage Vc. In this way, the first internal clock signals (CLK0'-CLK270 ') are delayed by a desired time in response to the control voltage Vc to generate second internal clock signals CLK0-CLK270 or second clock signals ICLK0-ICLK270.

23 shows an example of a memory system and 24 shows an example of a memory element, for example the memory element 200-1 in 23 having associated control logic according to an exemplary embodiment of the present invention. Specifically, the memory module 200 according to the 23 and 24 one or more of the multi-phase clock generator as a phase locked loop 24 included above in conjunction with the 5A - 12 have been described.

As shown, a memory system according to an exemplary embodiment of the present invention may include a memory controller 100 and a memory module 200 include. The memory module 200 may further comprise a plurality of memory elements 200-1 . 200-2 . 200-x which may be implemented in the form of DRAMs, for example.

The storage control unit 100 may include an external clock signal ECLK, one or more command signals COM, one or more address signals ADD and / or one or more data signals DATA to the memory module 200 output.

The memory module 200 can continue one or a plurality of data signals DATA to the memory controller 100 output. In the in 23 example shown can or can be the plurality of data signals DATA formed of a serial stream of 2 ⁿ bits, by one or shown DATAxj [1: 2 ^n] DATA11 bis [2 ⁿ 1]. As in 23 shown, the memory element 200-1 the external clock signal ECLK receiving the one or more command signals COM, the one or more address signals ADD and the data signals DATA11 to DATA1j. In the same way, the memory element 200-2 the external clock signal ECLK receiving the one or more command signals COM, the one or more external address signals ADD and the data signals DATA21 to DATA2j, and the memory element 200-x may receive the external clock signal ECLK, the one or more command signals COM, the one or more address signals ADD and the data signals DATAx1 to DATAxj.

As shown, in the exemplary memory system of the 23 each storage element 200-1 . 200-2 . 200-x Receive or output signals DATA during one clock cycle of the external clock signal ELCK formed of 2 ⁿ serial bits. In addition, signals DATA of j bits can be written or read at the same time.

As in 24 shown, the associated control logic can an address buffer (ADD BUF) 10 , an instruction decoder (COM DEC) 12 , one or more serial-to-parallel converters 14-1 to 14-j (j corresponds to j in 1A ), one or more parallel-to-serial converters 16-1 to 16-j , the memory cell array 18 , a row decoder 20 , a column decoder 22 , a PLL 24 and / or a control signal generating circuit (CSG Ckt) 26 exhibit. The address buffer (ADD BUF) 10 may receive one or more external input addresses (ADD) to generate, in response to an active command signal (ACT), a row address (RA) applied to the row decoder 20 is delivered.

The row decoder 20 may activate a main word line enable signal (MWE) corresponding to a plurality of column addresses generated by a plurality of column address buffers such that a desired word line (not shown) in the memory cell array 18 can be selected. The address buffer (ADD BUF) 10 may also generate a column address (CA), which may be sent to the column decoder, in response to a read command (RE) or a write command (WE) decoded from the one or more command signals COM 22 is delivered.

The column decoder 22 may receive a plurality of column addresses to activate a corresponding column select line (CSL). A plurality of bit lines of the memory cell array 18 may be selected depending on the selected CSL so that a plurality of data may be written to or read from the selected memory cells.

As stated above, the instruction decoder 12 generate an active command, a read command, and a write command after having received a plurality of external command signals (COM), such as RASE, CASE, WEB, etc.

Each serial-to-parallel converter ( 14-1 to 14-j ) can receive serial data DATA formed from 2 ^n- bit data, and can simultaneously send 2 ⁿ bits of parallel data over 2 ⁿ data bus lines to the memory cell array 18 in response to a write command signal (WE) and a plurality of control signals (P1 ~ P ( ²ⁿ )). If the number of data input / output pins (DQ) is j, the number of serial-to-parallel converters is also j. In addition, each of the serial-to-parallel converters ( 14-1 to 14-j ) with the memory cell array 18 be coupled via 2 ⁿ data bus lines.

Each parallel-to-serial converter ( 16-1 to 16-j ) can receive 2 ^n- bit data from a memory cell array 18 receive in parallel and output 2 ⁿ bits of serial data in response to a read command signal (RE) and a plurality of control signals (P 1 -P (2 ⁿ )). If the number of data input and output pins (DQ) is equal to j, the number of parallel-to-serial converters is also j.

The phase locked loop 24 may receive the external clock signal ECLK and perform a latching operation to output an internal clock signal CLK1 latched with the signal ECLK. Upon completion of the lock operation, the phase locked loop 24 a plurality of internal clock signals (CLK1~CLKl) to the control signal generation circuit (CSG Ckt.) 26 output corresponding to the N second clock signals ICLKn described above in connection with FIGS 14A - 15B have been described. The control signal generation circuit (CSG Ckt.) 26 may generate the plurality of control signals (P1~P ( ²ⁿ )).

Claims (29)

A clock generation circuit comprising: an inverter (I0) directly receiving an external clock signal (ECLK) and outputting an inverted external clock signal; M loop circuits (LC _{1 ... M} ) connected in series, where M is an integer ≥ 2, the first loop circuit (LC ₁ ) receives the inverted external clock signal, each of the M loop circuit N (A, B, C, D), where N is an integer ≥ 4, and each of the first to (M-1) -th loop circuits (LC _{1 ... M} ) _{. M-1} ) generates N internal intermediate clock signals at respective ones of the N nodes (A, B, C, D); and N sets of inverters (INV _{1 ... N} ), each of which has at least M - 1 inverters (I9 _{1 ... (M-1)} , I10 _{1 ... (M-1)} , I11 _{1 ... (M-1)} , I12 _{1 ... (M-1)} ) connected in series, each of the M-1 inverters (I9 _{1 ... (M-1)} , I10 _{1 ... ( M-1)} , I11 _{1 ... (M-1)} , I12 _{1 ... (M-1)} ) receives a corresponding internal intermediate clock signal from a preceding loop circuit and outputs a corresponding internal intermediate clock signal to a next loop circuit, N being internal Clock signals are generated at the N nodes of the Mth loop circuit, wherein the N internal clock signals have the same frequency as the external clock signal and an identical phase difference of 360 ° / N. Clock generating circuit according to claim 1, characterized characterized in that each of the M loop circuits has a plurality of loops. Clock generating circuit according to claim 1, characterized characterized in that each of the M loop circuits is a single one Loop. Clock generating circuit according to one of claims 1 to 3, characterized in that N is selected from a group, which is formed of 4, 5, 6, 8, 9, 10, 12, 15 and 18. A clock generation circuit comprising: an inverter (I0) directly receiving an external clock signal (ECLK) and outputting an inverted external clock signal; M loop circuits (LC _{1 ... M} ) connected in series, where M is an integer ≥ 2, the first loop circuit (LC ₁ ) receives the inverted external clock signal, each of the M loop circuits (LC _{1 ... M} ) N nodes (A, B, C, D), where N is an integer ≥ 4, and each of the M loop circuits (LC _{1 ... M} ) has N internal intermediate clock signals at each associated one of the N nodes (A, B , C, D) generated; N groups of inverters (INV _{1 ... N} ), each having at least M inverters (I9 _{1 ... (M)} , I10 _{1 ... (M)} , I11 _{1 ... (M)} , I12 _{1. .. (M)} ) connected in series, each of the M inverters (I9 _{1 ... (M)} , I10 _{1 ... (M)} , I11 _{1 ... (M)} , I12 _{1. .. (M)} ) receives a corresponding internal intermediate clock signal from a preceding loop circuit and outputs a corresponding internal intermediate clock signal to a next loop circuit, an (M + 1) th loop circuit; and an (M + 2) -th loop circuit, wherein the (M + 1) -th loop circuit and the (M + 2) -th loop circuit are connected in series with the M loop circuits and in parallel with each other, the (M + 1) -th loop circuit comprises N nodes, some of which receive a corresponding internal intermediate clock signal from the Mth inverters; wherein the (M + 2) th loop circuit comprises N nodes, some of which receive a corresponding internal intermediate clock signal from the Mth inverters generating N internal clock signals, each at a corresponding one of the N nodes; a first group of N inverters, each receiving a corresponding internal intermediate clock signal from the (M + 1) th loop circuit; a second group of N inverters, each receiving a corresponding internal intermediate clock signal from the (M + 2) th loop circuit; and a third group of N inverters each receiving output signals from the respective inverters of the first group of N inverters and the second group of N inverters and generating N internal clock signals, the N internal clock signals having the same frequency as the external clock signal and an identical one Phase difference of 360 ° / N have. Clock generating circuit according to claim 5, characterized characterized in that each of the (M + 1) -th loop circuits has a Having a plurality of loops. Clock generating circuit according to claim 5, characterized characterized in that each of the (M + 1) -th loop circuits has a has single loop. Clock generating circuit according to one of claims 5 to 7, characterized in that N is selected from a group, which is formed of 4, 5, 6, 8, 9, 10, 12, 15 and 18. Multiphase clock generator containing the clock generation circuit according to one of the claims 1 to 8. Multiphase clock generator according to claim 9, characterized by: a phase detector ( 56 ) receiving the external clock signal (ECLK) and a feedback clock signal (DCLK) and outputting an up signal (UP) when one phase of the external clock signal (ECLK) leads one phase of the feedback clock signal (DCLK) and one down signal (DN) when the phase of the external clock signal (ECLK) lags the phase of the feedback clock signal (DCLK). A multi-phase clock generator according to claim 10, characterized by: a control signal generator which outputs the up signal and receiving the down signal from the phase detector and outputting at least one control signal; and a phase change circuit receiving the at least one control signal and the N internal intermediate clock signals output from the Mth loop circuit as N first internal clock signals to generate N second clock signals, the phase change circuit outputting at least one of the N second clock signals as the feedback clock signal outputs. Multiphase clock generator according to claim 11, characterized characterized in that the control signal generator comprises a loop filter circuit is that has a charge pump and a low-pass filter, and that the at least one control signal includes a control voltage (Vc), wherein the charge pump charges or discharges the low-pass filter to one Control the level of the control voltage (Vc) until a latch operation is completed. Multiphase clock generator according to claim 12, characterized characterized in that the phase change circuit is a voltage controlled delay line that has a plurality of variable delay lines, each containing a plurality of delay cells, the are each controlled by the control voltage (Vc), wherein the voltage-controlled delay line the N first internal clock signals in response to the control voltage delayed to generate N second clock signals. Multi-phase clock generator according to claim 12 or 13, characterized in that the phase change circuit comprises: a voltage-controlled delay line with a plurality of variable delay lines, respectively a plurality of delay cells each controlled by the control voltage (Vc), wherein the voltage controlled delay line is the first N internal clock signals in dependence delayed by the control voltage, to generate N second internal clock signals; a multiplier, which multiplies a frequency of the N second internal clock signals, to generate N second clock signals having a frequency, the higher is as a frequency of the N second internal clock signals; and one Divider having a frequency of at least one of the N second internal Clock signals divides the feedback clock signal to create. Multiphase clock generator according to one of claims 11 to 14, characterized in that the control signal generator is a control circuit is, and that the at least one control signal a plurality of Includes selection signals and a weighting signal, the Control circuit comprises: a selection signal generator, the an up-counting operation dependent on from a first selection control signal (SUP) and the one down counting operation dependent on from a second selection control signal (SDN); one Weighting controller generating a first weighting control signal (WUP) and a second weighting control signal (WDN) are generated; one Weighting signal generator making an upward counting operation dependent on from the first weighting control signal (WUP) and the a down-counting operation dependent on from the second weighting control signal (WDN) and which outputs a weighting signal (W); a weighting minimum / maximum detector, the detects and inputs a maximum value of the weighting signal (W) generates first weight detection signal (WMAX) and the one Minimum value of the weighting signal (W) detects and a second weight detection signal (WMIN) generated; and a selection control signal generator which the first weight detection signal (WMAX), the second weight detection signal (WMIN), the first weighting control signal (WUP) and the second Weighting control signal (WDN) receives and the first selection control signal (SUP) and the second selection control signal (SDN) generated at the Selection signal generator are supplied. Multiphase clock generator according to one of claims 11 to 15, characterized in that the phase change circuit is a selection and Phase interpolation circuit, which is the N first internal Receives clock signals, two of the N first internal clock signals in response to control signals selects Phases of the two selected among the N first internal clock signals clock signals dependent on interpolated from the weighting signal to N second clock signals generate, which are synchronized with the external clock signal, and the at least one of the N second clock signals as the feedback clock signal outputs. A multi-phase clock generator according to any one of claims 11 to 16, characterized in that the phase change circuit comprises: a selection and phase interpolation circuit receiving the N first internal clock signals, selecting two of the N first internal clock signals in response to control signals, phases of the two among the Interpolating N first internal clock signals selected clock signals in response to a weighting signal to produce N second internal clock signals; a multiplier that multiplies a frequency of the N second internal clock signals to produce N second clock signals having a frequency is higher than a frequency of the N second internal clock signals; and a divider that divides a frequency of at least one of the N second internal clock signals to generate the feedback clock signal. Multiphase clock generator according to one of claims 11 to 15, characterized in that the phase change circuit is a voltage controlled delay line , which has a plurality of variable delay lines, of each comprising a plurality of delay cells, the are each controlled by the control voltage (Vc), wherein the voltage-controlled delay line the N first internal clock signals in response to the control voltage delayed to generate N second clock signals. Multiphase clock generator according to one of claims 10 to 18, characterized in that the phase detector comprises: one first flip-flop, which is the external clock signal, a return signal and receives a voltage Vcc and the up signal outputs; a second flip-flop containing the feedback clock signal, the return signal and the voltage Vcc is received and outputs the down signal; and one Nand gate to performing a logical NAND operation with the up signal and the down signal, around the return signal to create. Multiphase clock generator according to one of claims 10 to 19, characterized in that the up signal and the down signal be used to phase in the corresponding internal intermediate clock signals to control. Multiphase clock generator according to one of claims 16 to 20, characterized in that the selection and phase interpolation circuit between selects adjacent clock signals and interpolated. Multiphase clock generator according to one of claims 16 to 21, characterized in that the selection and phase interpolation circuit comprises: a Plurality of selection circuits, each one corresponding from the plurality of selection signals and at least two of the N first ones receive internal clock signals; and a phase interpolation circuit, which is an output of each of the plurality of selection circuits receives and second clock signals in dependence from the weighting signal. Multiphase clock generator according to one of claims 15 to 22, characterized in that the control circuit the up signal and the down signal receives from a phase detector and generates the plurality of selection signals and the weighting signal. A multi-phase clock generator according to claim 22 or 23, characterized in that said weighting control generator comprises: an XOR gate for performing an XOR operation with S select signals, where S ≥ 2, an inverter for inverting an output of said XOR gate, 2 ^S AND gates, part of which receives an output of the XOR gate and a remaining part receives an output of the inverter, and part of which receives an up signal and a remaining part receives a down signal; and S OR gates performing an OR operation on the outputs of the 2 ^S AND gates to generate the first weight control signal (WUP) and the second weight control signal (WDN). A multi-phase clock generator according to any one of claims 22 to 24, characterized in that the selection control signal generator comprises: at least two AND / OR gate pairs, a first one of the first weighting detection signal (WMAX) and the second weighting detection signal (WMIN) of the weighting minimum / Maximum detector (WD) receives and receives the first weighting control signal (WUP) from the weighting control generator (WCG) and generates the first selection control signal (SUP), a second one of which the first weighting detection signal (WMAX) and the second weighting detection signal (WMIN) Weighting Minimum / Maximum Detector (WD, 76 ) and receives the second weighting control signal (WDN) from the weighting control generator (WCG) and generates the second selection control signal (SDN). Multiphase clock generator according to one of claims 12 to 25, characterized in that that the charge pump has: a first current source (I1), a second current source, a PMOS transistor and an NMOS transistor connected in series, and the Low-pass filter comprises: a first capacitor and a second Capacitor / resistor pair connected in parallel, wherein if an inverted UP signal (UPB) at a gate terminal of the PMOS transistor is applied, an output terminal through the first current source (I1) is charged and filtered through the loop filter becomes, so that the control voltage (Vc) increases, and when a DN signal is activated, the output terminal through the second Power source is discharged and filtered by the low pass filter, so that the control voltage (Vc) decreases. A memory element comprising: a memory cell array ( 18 ); a multi-phase clock generator ( 24 ) receiving an external clock signal (ECLK) and a feedback clock signal (CLK1) and having at least one clock generating circuit directly generating at least N internal clock signals (CLK1~CLKl), where N is an integer ≥ 4; a control signal generation circuit ( 26 ) for receiving the at least N internal clock signals (CLK1~CLKl) and for generating p control signals, where p is an integer ≥ 4; at least one serial-parallel converter ( 14-1 ~ 14-j ) for receiving bits of a serial bit stream and for converting the serial bit stream into a parallel bit stream entering the memory cell array (US Pat. 18 ) is writable, depending on each of the p control signals; and at least one parallel-to-serial converter ( 16-1 ~ 16j ) for receiving a parallel bit stream from the memory cell array ( 18 ) and for converting the parallel bit stream into a serial bit stream in response to each of the p control signals, characterized in that the clock generating circuit is a clock generating circuit according to any one of claims 1 to 9. Method for generating N internal clock signals in a clock generation circuit with M series-connected loop circuits, where N is an integer ≥ 4 and M is an integer 2, with the steps: direct reception an external clock signal (ECLK) and inverting the external clock signal (ECLK); Receive the inverted external clock signal for generating N internal Intermediate clock signals from the first of the M loop circuits; and (M - 1) -maliges Interpolate the phase of the N internal intermediate clock signals below Use the second to Mth loop circuit to the N internal To generate clock signals, wherein the N internal clock signals the same Frequency like the external clock signal and an identical phase difference of 360 ° / N exhibit. A method of locking the phase of a feedback clock signal (DCLK) with an external clock signal (ECLK) of a multi-phase clock generator with M series-connected loop circuits, where M is a whole Number ≥ 2 is, with the steps: Receive the external clock signal (ECLK) and the feedback clock signal (DCLK); Output an upward signal (UP) when one phase of the external clock signal (ECLK) of one phase of the Feedback clock signal (DCLK) leads, and outputting a down signal (DN) when the phase the external clock signal (ECLK) of the phase of the feedback clock signal (DCLK) lags; Generating at least one control signal (CS) in dependence from the up signal (UP) and the down signal (DN); Receiving the external clock signal to generate N internal intermediate clock signals from the first of the M loop circuits, where N is an integer ≥ 4 is; (M - 1) -maliges Interpolate the phase of the N internal intermediate clock signals below Use the second to M th loop circuit to N internal clock signals to generate, wherein the at least one control signal, a phase change controls at least one of the N internal clock signals; and Produce the feedback clock signal (DCLK) from at least one of the N internal clock signals, in which the N internal clock signals have the same frequency as the external clock signal and have an identical phase difference of 360 ° / N.