DE102006051137A1 - Electrical circuit for electronic system, has arrangement of vertical selection transistors vertically formed in substrate, and gate-electrode-ditches filled with gate-electrode-material - Google Patents

Abstract

The circuit has an arrangement of vertical selection transistors (120, 121) vertically formed in a substrate and selecting memory cells (110, 111) by selection of a word line (150) and a bit line (140). A primary surface of the substrate defines a horizontal reference plane, and a set of gate-electrode-ditches is filled with a gate-electrode-material. A set of gate-electrodes is connected with the word line that is positioned perpendicular to the gate-electrode-ditches and above the reference plane. Independent claims are also included for the following: (1) an electronic system (2) a method for producing an electrical system.

Description

The The invention relates to an array of vertical, in a substrate formed transistors to select one of a variety resistive switching memory cell, a memory device comprising a Arrangement of vertical transistors, an electronic system, and a method of forming an array of vertical transistors.

In a "resistive" or "resistively switching" memory cell an "active" or "active" material, which is usually between two suitable electrodes, that is an anode and a cathode, is arranged, between an electrically conductive and an electrically less conductive state by means of a suitable switching process be switched. The electrically conductive state, a logical one and the less conductive state a logical zero be assigned, or vice versa.

For phase change memory For example, (phase change random access memory) can a suitable chalcogenide compound, for example Ge-Sb-Te (GST) or an In-Sb-Te compound, as an active material can be used, which between two corresponding electrodes is arranged. This switching active material can be between a be switched amorphous and a crystalline state. The amorphous Condition is a relatively weak conductive state, the corresponding a logical zero can be assigned. The crystalline state, the is called the relatively well-conductive state, can accordingly a logical One to be assigned.

Around a change from the amorphous, ie the weakly conductive state of the switching active material, in the crystalline state, that is the relative good conductive condition, to bring about the material has to be heated. For this purpose, a heating current pulse passed through the material which the switching active material on the Heated crystallization temperature and thus reduces the resistance. In this way, the value of a memory cell in a first be brought logical state.

Vice versa can the switching active material by applying a relatively high Electricity to be heated to the cell, so the switching active material melts and by subsequent Schockabkühlen in an amorphous, that is relatively weakly conductive, state can be brought to the second logical state can be assigned.

For PCRAM memory cells various concepts have been proposed, for example from SJ Ahn, "Highly Manufacturable High Density Phase Change Memory of 64MB and Beyond", IEDM 2004 and from H. Horii et al "A novel cell technology using N-doped films for phase change RAM" VLSI, 2003, , or from YN Hwang et al. "Phase-change RAM based on 0.24 μm CMOS technologies", VLSI, 2003, or from S. Lai et al. "OUM - a 180 nm non-volatile memory cell element technology for standalone and embedded applications", IEDM 2001, or from YH Ha et al "An edge contact cell type cell for phase change RAM featuring very low power consumption", VLSI, 2003 ,

The featured memory cells usually use planar transistors or transistors whose source / drain contacts are in the same horizontal Plain are arranged, such as FinFETs. From geometric establish such a construction makes it difficult to reduce the cell size because the Size of the cell the size of the selection transistor to choose the cell includes.

Farther DRAN (Dynamic Random Access Memory) cells are known, which has an arrangement of vertical transistor cells in a substrate, the lower source / drain regions to a common terminal plate are connected. The upper source / drain regions have a Connection to a storage capacity. The arrangement of the transistor cells is represented by word line and perpendicular isolation trenches (STI = shallow trench isolation). The word lines form in the trenches the gate electrodes of the transistors.

Around competitive to be able to be a small cell size is needed a high density of memory cells in a memory cell array allows.

The invention described below is directed to an integrated circuit comprising an array of vertical transistors formed in a substrate for selecting one of a plurality of resistively switching memory cells by selecting a word line and a bit line, the surface of the substrate defining a horizontal reference plane comprising a plurality parallel isolation trenches filled with an insulating material and having a plurality of orthogonal gate electrode trenches, the gate electrode trenches being filled with a suitable gate electrode material, and the vertical gate electrode trenches being sandwiched between two following parallel isolation trenches so as to form separate gate electrodes disposed below the reference plane, and wherein the isolation trenches and the gate electrodes form distinct active regions of transistors of the array of vertical transistors in the substrate, two Gate electrodes on two opposite side walls of an active region form a double gate electrode of a transistor in the array of transistors, and wherein the plurality of gate electrodes is connected to a word line which is perpendicular to the gate electrode trenches and over the reference plane is arranged.

Farther the invention is an integrated circuit comprising a Arrangement of vertical, formed in a substrate transistors to choose one of a plurality of resistively switching memory cells by selecting directed to a word line and a bit line, wherein the surface of the Substrate forms a horizontal reference plane, comprising an in the ground plane electrode formed on the substrate by a layer of N + doped substrate material; a plurality of parallel, projecting into the ground plate and filled with insulating material isolation trenches; and a plurality of extending into the ground plate electrode and perpendicular to the isolation trenches arranged gate electrode trenches, wherein the gate electrode trenches with a suitable, interrupted by insulating gate electrode material filled are and thus separate, arranged below the reference gate electrodes form, with the isolation trenches and the gate electrode trenches form distinct active areas of transistors made of the substrate material emerge and connected to the ground plane electrode, wherein two, at opposite sidewalls an active region arranged gate electrodes a double-gate electrode of a transistor form, and wherein a plurality of gate electrodes with a word line connected perpendicular to the gate electrode trenches and over the Reference plane runs.

Furthermore, a method for producing the integrated circuit comprising an arrangement of transistors for selecting one of a plurality of resistively switching memory cells is disclosed, which comprises the following method steps:
Forming a ground plane electrode in the substrate; Forming a plurality of parallel isolation trenches in the substrate;
Forming a plurality of gate electrode trenches disposed perpendicular to the isolation trenches; Forming a layer of gate dielectric in the gate electrode trenches and filling the gate electrode trenches with a gate electrode conductive material; Depositing a three-layer stack of gate electrode material, word line material and insulating material, and then etching the three-layer stack to form word lines that are perpendicular to the gate electrode trenches, the word lines at least partially over vertical the active regions of the transistors are placed in the array of transistors.

In another aspect, the invention is directed to a method of fabricating an integrated circuit comprising an array of transistors for selecting one of a plurality of resistively switching memory cells, the surface of the substrate forming a horizontal reference plane, comprising the steps of:
Forming a ground plane electrode in the substrate by deeply implanting N + ions into a layer of the substrate material;
Forming a plurality of parallel isolation trenches in the substrate by etching and filling the strips in the substrate;
Forming a plurality of gate electrode trenches, wherein the gate electrode trenches are perpendicular to the isolation trenches, and wherein the etching is selective to the isolation material of the isolation trenches such that the isolation trenches and the gate electrode trenches form active regions of transistors ;
Producing a layer of gate dielectric in the gate electrode trenches and filling the gate electrode trenches with conductive gate electrode material;
Depositing a three-layer stack of gate electrode material, word line material, and insulating material, and then etching the three-layer stack to form word lines that are perpendicular to the gate electrode trenches, the gate electrodes by means of the gate Electrode materials are connected to the word lines, and wherein the word lines are placed at least partially vertically above the active regions and wherein the etching extends into the gate electrode trenches; Producing a galvanic insulating layer on a sidewall of the three-layer stack and in the gaps in the gate electrode trenches;
Depositing a layer of insulating material and filling the gaps between the word lines with an insulating material;
Forming contacts on the active regions to contact a volume of resistive switching material by etching holes which at least partially expose the surface of active regions and filling these holes with a suitable conductive material;
Forming volumes of resistively switching material connected to the contacts and forming bitlines connected to the volume of resistive switching material.

Further Features and embodiments of the invention will become apparent from the following, detailed description and from the drawings.

The Drawings show:

1 a schematic diagram of two memory cells, which represent an example of an arrangement of a plurality of memory cells

2 a schematic plan view of a portion of a layout of an array of memory cells;

3a a plan view of an array of transistors at an early stage in the production;

3b . 3c a sectional view through a transistor at a time as in 3a ;

4a - 4c Views like to the 3 described, however, after further process steps;

5 a supervision like in 4a after further process steps have been carried out;

6a a cross section through a transistor in the direction of a bit line;

6b a cross section in the direction of a bit line through a gate electrode;

6c a cross-section in the direction of a word line through two active regions of adjacent transistors;

6d a cross section in the direction of a word line through two gate electrodes.

1 shows an electrical circuit 100 , A first and a second memory cell, each delimited by the dashed lines 110 respectively 111 10 show, by way of example, a multiplicity of identical memory cells in one arrangement, which can be arranged on an integrated circuit, a so-called IC.

Every memory cell 100 . 111 has a memory element 120 . 121 and a selection transistor 130 . 131 on. In this drawing, as well as in the entire invention, the memory element may be a resistively switching memory element of any type, for example a volume phase change material of a PCRAM memory cell or a volume of a suitable material of a CBRAM (CBRAM) or an MRAM cell.

The memory elements 120 . 121 are at their one end with the bit line 140 and with its remaining end to the selection transistor 130 respectively. 131 the associated memory cell connected.

As shown in the drawing, the selection transistors 130 . 131 Double gate transistors, wherein the two gates of a transistor are arranged on opposite side walls of the active region of the transistor. As will be explained in more detail below, the transistors are vertical transistors, vertically describing that - with the original surface of the wafer as a horizontal reference plane throughout the following description - the current flows vertically, or in other words, that the drain is substantially vertical is disposed over the active region, which in turn is arranged substantially vertically above the source of the transistor. The gate electrodes of a transistor are connected to one and the same word line, so that the gate electrodes of the transistor 130 with a first wordline 150 and the gate electrodes of the transistor 131 with a second word line 151 are connected.

The transistors 130 . 131 are still using their source with a ground line 160 which, as will be explained later, is a ground plane electrode and which is typically a doped layer in the wafer serving as a ground line for all the selection transistors. In this way, the ground plane electrode is placed below the original surface of the wafer. Alternatively, the ground plane electrode may be of another type of conductive layer, for example, a metal silicide or a metal. The semiconductor material can then be deposited or epitaxially grown or similarly produced.

Farther It should be noted that the two memory cells are representative for one Are a plurality of memory cells of a memory element in an IC, wherein the cells are arranged in a plurality of bit lines and word line for operating the cells are arranged. A variety of memory cells is connected to a bit line and a plurality of cells is connected to a wordline, with a single word Memory cell with a particular pair of a bit line and a Word line is connected so that each cell by selecting the corresponding bit line and word line can be selected.

2 shows a schematic plan view of a section of a layout of an arrangement 200 of memory cells, each comprising a double gate transistor.

In this illustration, the insulating material, which separates elements and isolated from each other for reasons of clarity, not shown in part. It will be apparent to those skilled in the art, for example, that bit or word lines drawn separately are embedded in any suitable dielectric to galvanically isolate them from adjacent elements. Likewise, some are Elements that are important for resistive switching memory cells, such as volume of the resistive switching material, not shown, as these are covered by other, overlying in the drawing elements. Furthermore, the ground plate electrode on which the structure is formed, not shown in this illustration.

A first and a second bit line 210 . 211 are the topmost elements in this supervision and exemplify a plurality of identical, adjacent and parallel bitlines. Each bit line 210 . 211 is connected to a plurality of memory elements of memory cells, which may be, for example, volumes of phase change material. These memory elements - hidden in this illustration below the bit lines and thus not visible - are via the bit line contacts 220 . 221 . 222 with the bitlines 210 . 211 where the placement of a bitline contact is indicated by a framed quadrangle.

The wordlines 230 . 231 are exemplary of a plurality of parallel word lines perpendicular to and below the bit lines 210 . 211 are arranged. As previously mentioned, each wordline is having a plurality of gate electrodes 240 - 245 connected, that is word line 230 is with the gate electrodes 240 . 241 and 242 and word line 231 is with the gate electrodes 243 - 245 connected. The gate electrodes 240 and 241 serve as gate electrodes for an active region of a transistor whose active region is arranged between these gate electrodes. In this way, the gate electrodes are arranged on opposite sidewalls of the active region of a transistor. The gate electrodes are by means of the gate oxide 250 isolated galvanically against the active area, its approximate placement by the dashed line 260 is specified. As shown, the shape of the active area is an oblong square arranged in a direction between the gate electrodes and in the direction perpendicular thereto by shallow trench isolation 270 (STI = shallow trench isolation) is limited, wherein a comparatively thin layer of a gate oxide 250 is respectively placed between a gate electrode and the active region or between the STI and the active region. Although the gate oxide does not necessarily have to be located between the active region and the STI, this arrangement is typical.

A transistor with an active area 260 further includes the gate electrodes 240 and 241 that with the wordline 230 are connected. The upper end of the active area 260 is connected to a memory element - not shown - connected, which in turn via a Bitleitungskontakt with bit line 211 wherein the placement of the bit line contact is similar to that of the 220 is. The lower end of the active area 260 is the source of the transistor and connected to the ground plane electrode, which is the lowest element and therefore not visible in this representation. Although this representation is not true to scale, but arrow shows 280 indicate that the periodicity of the word line is 2.2 to 3 F arrow 281 indicates the periodicity of the bitlines, which is 2F, where F indicates the "minimum feature size" given by conventional manufacturing techniques. Accordingly, the size of a memory cell is 4.4 to 6 F ² .

As well will be the approximate Size of one active area by the periodicity of the bit and word lines specified. According to the current production possibilities becomes a width of 1F for a Bit or word line needed, so the area of an active area approximately 1,2-2 times 1 F, resulting in a size of 1.2 until 2 F2 leads. Further developments in metallurgy and lithography can do this change relative sizes.

The vertical structure of such an arrangement is in 3a which shows a top view of the arrangement 2 at an earlier time of production.

3a shows a plan view of an array of transistors at an early production time. 3b is a sectional view through an active region of a transistor as indicated by line A and 3c is a sectional view through a gate electrode of a transistor as indicated by line B.

In an early process step becomes a ground plate electrode 310 - in 3a not shown - formed. This can be achieved by deep implantation of N + charge carriers into the silicon 320 of the wafer or by implanting with a subsequent epitaxial growth of Si on top. A silicide, metal or other conductive material may then be the electrode 310 form. The silicon or other semiconductor material may be formed by deposition or epitaxial growth or other known methods. In this way, an N + doped layer within the silicon 320 generated as a ground plane electrode 310 serves.

Furthermore, a thick oxide protective layer 340 and depositing a layer of silicon nitride on the surface which protects the surface and serves to achieve a better etch result.

Isolation trenches are etched into the wafer, extending into the ground plane electrode 310 extend. The isolation trenches serve as shallow trench ice Alignment (STI = shallow trench insulation) and are suitably with a suitable insulating material 330 filled, for example, silica.

Subsequently, gate electrode trenches 360 etched, these being perpendicular to the isolation trenches 330 are arranged. The etching is selective to SiN and silicon oxide, so that the SiN and SiO in the isolation trenches 330 remains untouched. Since this etch is selective to SiO, the gate electrode trenches become 360 from the isolation trenches 330 interrupted, leaving holes and at the same time columns 370 made of silicon, that of the thick oxide protective layer 340 and the SiN layer 350 are covered. The columns 370 serve as active regions of the transistors and can optionally be narrowed down to form them in their base into elongated squares. Likewise, a sacrificial oxide layer can be deposited, which is not shown in the drawing.

Further, implantation of N + ions may be performed to implant N + ions into the bottom of the holes in the event that the holes do not extend into the ground plate electrode, with implantation limited to the bottom surface of the holes. numeral 380 denotes an area at the bottom of a hole which has been implanted N +.

Thereafter, if a sacrificial oxide layer has been previously deposited, it is to be removed before an oxide layer is formed on the sidewalls and bottom of such a hole around a gate oxide layer in a subsequent process step 390 train.

After the gate oxide layer 390 are formed, the holes are filled with a polysilicon to the gate electrodes 3100 to form, the holes are completely or only partially - not shown - filled. In the event that the holes are only partially filled, the remaining opening may be filled with a dielectric and then etched back. Likewise, the polysilicon of the gate electrodes may optionally be planarized to the plane of the SiN protective layer.

In this way are gate electrodes 3100 have been formed, which reach below the original surface level by arrow 3110 is specified.

In the 4a - 4c are the same views as in the 3a - 3c but at a later stage of the procedure. Like reference characters designate like matter throughout the drawings.

In In a first optional method step, the isolation of the flat trench isolation (STI).

The SiN layer 350 is removed, making it the thick protective oxide layer 340 in the active areas 370 is exposed. As shown in the drawing, the upper edge of the oxide layer lies 340 above the active areas at the level of the STI 330 ,

At this stage of the process, source implants may be performed to determine the semiconductor junctions in the transistors. That is, N + ions can be implanted into the upper regions of the active regions to give N + doping as indicated by reference numeral 3120 to reach specified.

Subsequently, a gate conductor stack of three layers is deposited, as in a conventional wordline stack, by depositing a first layer of a suitable conductive material 3130 , in this case, for example, polysilicon as for the gate electrodes 3100 second, a layer of comparatively good conducting material, such as a metal 3140 For example, tungsten (W) and third, a layer of insulating material 3150 , such as silicon nitrite 3150 ,

This gate ladder stack is then etched to a word line 3140 from the metal / tungsten layer. When etching, ensure that the overlap of the first layer 3140 good contact with the gate electrodes 3100 makes the gate electrodes to the metal 3140 to pair. That is, in this case, about two-thirds of the reference number 3160 indicated area with the surface of a gate electrode 3100 overlaps. However, a different overlap ratio is sufficient, as long as sufficient coupling between the word line 3140 and the gate electrode 3100 is reached.

The etching of the gate conductor stack is carried out so that as far as the gate electrode material 3100 is etched into it. As shown in the drawing, the material is the gate electrode 3100 partially removed so that the surface of the gate electrode lies below the plane of the original wafer, indicated by arrow 3110 is specified.

In this method step, the gate conductor stack is formed into lines having open side surfaces and thus the word line 3140 leave with an open side wall.

Optionally, to determine the source / drain junctions in the active region of a Transistors are used to perform an oblique ion implantation to N + ions in the sidewalls of the active area 370 to implant. This may be useful in the case if over-etching into the gate electrode material 3100 the doping of the active area was damaged.

Subsequently, gate ladder spacers - as indicated by arrows 3170 shown - of insulating material, preferably of the same material as the uppermost layer of the gate conductor stack, in this case silicon nitride, on the sidewalls of the gate conductor stack and the sidewalls of the active region 370 deposited to isolate them electrically. These spacers may be on top of the gate electrodes 3100 thick enough to fill the openings on the gate electrodes or, as shown in the drawing, the spacers leave openings on top of the gate electrodes. Optionally, the openings are filled (preferably divot fill) with, preferably, the material from which the spacers were formed, that is, in this case, with silicon nitrite and then removing the over-deposited material so as to completely cover the hidden gate electrodes.

The 4a - 4c show a structure that was generated according to the described process steps.

In an optional, subsequent process step, the thick Oxide layer from the surface The active areas can be removed and it can be silicon epitaxially grown up so as to increase the contact area of the active areas enlarge - not shown.

5 shows a plan view of the structure as in the previous 3a and 4a after further process steps have been performed, as explained below. Again, like reference numerals refer to like things in the preceding figures.

To illustrate in this schematic drawing, the reference numerals designate 360 the placement of the gate trenches, where the actual gate trenches are covered by other layers as described above.

As in 4a is shown in a further process step, a comparatively thin layer of silicon nitride deposited on the surface of the structure. Furthermore, a thicker layer of a suitable insulating material, such as SiO, is deposited on the chip to fill in residual gaps, for example, between the gate conductor stacks and the spacers, respectively.

Furthermore, by means of a conventional method, the insulating material on the top of the active regions is removed, for example by means of a conventional lithography and etching process. Strips etched perpendicular to the wordlines and above the active regions are then etched, with the etch selective to the gate conductors and gate conductor spacers 3150 . 3170 is so that the wordlines embedded in it are preserved. Accordingly, holes are etched over the active areas in the insulating material exposing the surface of the active areas. In this fabrication state, the contact area of the active regions may be increased by epitaxially growing silicon on the active regions, or an implantation may be performed to introduce N + ions into the upper region of an active region.

The generated holes are then coated with a suitable conductive material 520 , preferably a metal such as tungsten (W) filled to make a connection to an active area. The conductive material 520 is then planarized to match the surface of the gate conductor stack 3150 to form a planar surface.

With the method steps described here, a selection transistor can thus be produced which can be connected to the ground contact of a volume of a resistively switching material and onto which such a volume of resistively switching material can be deposited by means of conventional methods. In turn, this can be a bit line 210 be formed, the bit line 210 may be connected to a plurality of volume resistively switching material, and perpendicular to the word lines 3140 is arranged.

6a to 6d each show a cross section through the structure of a transistor, wherein 6a a sectional view in the direction of a bit line and through an active area, 6b a section in the direction of a bit line and through a gate electrode, 6c a sectional view in the direction of a word line through two active areas of two adjacent transistors and 6d is a sectional view in the word line direction through two gate electrodes in the direction of a word line.

6a shows the active area 370 a transistor whose lower region is connected to the ground plane electrode 310 connected is. The upper region of the active area 370 For example, N + may be implanted, with either the entire upper region or only a portion implanted as indicated by the quarter circle, and those with the contact 520 connected in this case, the ground contact of a volume of resistive switching material 610 is which again with a bit line 210 connected is.

In this view, the side walls of the active area border 370 to the isolation trenches forming the STI, which in this view run into the plane of the paper. The surface of the active area 370 is partly due to the contact 520 covered, to which this is connected, and partly from the remains of the thick oxide insulating layer 340 covered. The thick oxide layer 340 isolated the gate ladder. This has a layer of SiO 3130 and a layer of a good conductive material, such as metal, on the word line 230 forms. The surface of the gate conductor stack is through a layer of SiN 3150 The sidewalls are isolated by the gate conductor spacers.

The ground plate electrode 310 , the STI 330 and the gate ladder run into the paper plane in this view and are thus in 6b visible, like a parallel section view 6a shows, but which lies in front of or behind it, because the cut line here through the gate electrode 3100 runs. To prevent the gate electrode 3100 formed of a conductive material such as polysilicon, which contacts the active region - not shown here - or the ground plane electrode, it is of one layer 390 an insulating material 390 like SiO surrounded. The gate electrode 3100 is over the polysilicon 3130 the gate lead galvanically with the word line 230 connected.

It should be noted that the bottom surface of the polysilicon of the gate lead stack is indicated by reference numerals 3160 indicated - the gate electrode 3100 preferably overlaps two-thirds of the surface. The remaining surface of the gate electrode 3100 is covered with insulating material of the gate conductor spacer, which in turn is covered by a thick layer of insulating material 510 is covered.

6c shows a schematic sectional view in the direction of a word line through an active region of a transistor and a gate conductor stack. As mentioned above, the gate conductor stack overlapping the polysilicon line overlaps 3130 , the wordline 230 and the insulating layer 3150 partially, the surface of an active area 370 a transistor. In this view, the intersection line crosses the overlap area.

An active area 370 stands out of the ground plate electrode 310 out. A first and a second gate electrode 3100 are on the left and right sidewall of the active area 370 placed and through the gate dielectric or gate oxide 390 isolated from this, so that the two gate electrodes form a dual or double gate for the transistor. The gate electrodes are over the polysilicon line 3130 and the word line 230 connected with each other.

It should be noted that the two gate electrodes not only act as gate electrodes of the active region visible in this view 370 serve. Rather, each gate electrode also serves as a gate electrode for an adjacent active region and vice versa. That is, the gate electrode on the left side of the active area 370 as a gate electrode for the illustrated active area 370 and also serves as an active region gate electrode adjacent to the left side of the illustrated gate electrode. Likewise, the gate electrode serves on the right side of the active region 370 also as gate electrode for the next active area on the right side. In this way, a plurality of gate electrodes 3100 with a single wordline 230 each two gate electrodes form a double gate electrode for a transistor.

Although the drawings are not drawn to scale, the floor area of the active area is 370 - as drawn - not square. When comparing the forms of an active area 370 out 6a with the in 6c it becomes clear that the shape of the lower surface of an active area 370 is an oblong quadrilateral, wherein the side length in the direction of a word line is smaller than the side length in the direction of a bit line.

A parallel sectional view through a transistor is shown in FIG 6d shown, with the section line through the contact 520 runs, which is the active area 370 with a volume of switching active material 610 connects, which in turn is galvanically connected to a bit line 210 is coupled. The active area 370 arises from the ground plate electrode 310 and is galvanic to the contact 520 coupled, the ground contact of the volume switching active material 610 serves. At the left and right side wall of the active area 370 is each a gate electrode 3100 placed by means of a gate dielectric 390 isolated from the active area.

The surface of the original wafer is by arrow 3110 designated. As shown in the drawing, the upper surface of the gate electrode is below the surface plane 3110 of the original wafer, so that the gate electrodes are buried in this way.

Claims (38)

An integrated circuit comprising an array of vertical transistors formed in a substrate for selecting one of a plurality of resistively switching memory cells (US Pat. 200 ) by selecting a word line ( 230 ) and a bit line ( 210 ), Where wherein the original surface of the substrate defines a horizontal reference plane comprising a plurality of parallel isolation trenches (US Pat. 330 ) filled with an insulating material and a plurality of perpendicular thereto, filled with a gate electrode material gate electrode trenches ( 240 ), wherein each vertical gate electrode trench of the plurality of vertical gate electrode trenches for forming a plurality of gate electrodes ( 240 ) between two successive, parallel isolation trenches ( 330 ) for forming a plurality of gate electrodes ( 240 ) is arranged below the reference plane, wherein the isolation trenches ( 330 ) and the gate electrode trenches have unique active regions ( 370 ) of transistors of the array of vertical transistors in the substrate, wherein two, placed on opposite sides of an active region gate electrodes form a double gate electrode of a transistor of the array of transistors, and wherein the plurality of gate electrodes is connected to a word line which is placed perpendicular to the plurality of vertical gate electrode trenches and above the reference plane. An integrated circuit according to claim 1, wherein a resistive switching memory cell ( 110 ) a volume of resistive switching material ( 610 ), which via a contact ( 520 ) is connected to a transistor, and wherein the contact ( 520 ) and the word line ( 230 ) at least partially vertically above the active area ( 370 ) of the transistor is placed. Integrated circuit according to one of the preceding claims, wherein the volume of resistive switching material ( 610 ) with a bit line ( 210 ) connected perpendicular to the word lines ( 230 ) runs. Integrated circuit according to one of the preceding claims, wherein the active region ( 370 ) of a transistor with a ground plane electrode ( 310 ), wherein the ground plate electrode ( 310 ) is formed as an N + doped plate in the substrate. Integrated circuit according to one of the preceding claims, wherein the multiplicity of parallel isolation trenches ( 330 ) and the plurality of vertical gate electrode trenches each extend into the ground plate electrode ( 310 ). An integrated circuit according to any one of the preceding claims, wherein said plurality of gate electrodes ( 240 ) is formed of polysilicon. Integrated circuit according to one of the preceding claims, wherein the word lines ( 230 ) are formed of a layer of polysilicon and a layer of metal. An integrated circuit according to claim 7, wherein said Metal tungsten is. Integrated circuit according to one of the preceding claims, wherein the plurality of resistively switching memory cells ( 110 ) Phase change memory cells are. Memory element comprising an array of vertical Transistors according to claim 1. Electronic system comprising the memory element according to claim 10th An integrated circuit comprising an array of vertical transistors formed in a substrate for selecting one of a plurality of resistively switching memory cells ( 110 ) by selecting a word line ( 230 ) and a bit line ( 210 ), wherein the original surface of the substrate defines a horizontal reference plane comprising a ground plane electrode ( 310 ) in the substrate, a plurality of parallel, down to the ground plate electrode ( 310 ) extending and filled with an insulating material isolation trenches ( 330 ), and a plurality of up to the ground plate electrode ( 310 ) extending and perpendicular to the isolation trenches ( 330 ) arranged gate electrodes trenches, which are filled with a gate electrode material which is interrupted by the insulating material and thus separate gate electrodes ( 240 ), which are arranged below the reference plane, and wherein the isolation trenches ( 330 ) and the gate electrode trenches separate active regions ( 370 ) of transistors connected to the ground plane electrode ( 310 ) and two on opposite sides of an active area ( 370 ) arranged gate electrodes ( 240 ) form a double gate electrode of a transistor, and wherein a plurality of gate electrodes ( 240 ) with a word line ( 230 ) which is perpendicular to the gate electrode trenches and above the reference plane. An integrated circuit according to claim 12, wherein the resistive switching memory cell ( 110 ) a volume of resistive switching material ( 610 ), which via a contact ( 520 ) is connected to a transistor, wherein the contact ( 520 ) and the word line ( 230 ) at least partially vertically above the active area ( 370 ) of the transistor are arranged. Integrated circuit according to one of the preceding claims 12 to 13, wherein the volume of resistive switching material ( 610 ) with bitlines ( 210 ) which are perpendicular to the word lines ( 230 ). Integrated circuit according to one of the preceding claims 12 to 14, wherein the gate electrodes ( 240 ) are formed of polysilicon. Integrated circuit according to one of the preceding claims 12 to 15, wherein the word lines ( 230 ) are each formed of a layer of polysilicon and a layer of metal. An integrated circuit according to claim 16, wherein the metal is tungsten. Integrated circuit according to one of the preceding claims 12 to 17, wherein the resistively switching memory cells 110 Phase change memory cells are. Integrated circuit according to one of the preceding claims 12 to 18, wherein the ground plane electrode ( 310 ) in the substrate is a layer of N + doped substrate material. Memory element comprising the arrangement of vertical Transistors according to claim 12th Electronic system comprising the memory element according to claim 20. A method of manufacturing an integrated circuit comprising an array of transistors in a substrate for selecting one of a plurality of resistively switching memory cells ( 110 ), comprising the following method steps: forming a ground plate electrode ( 310 in the substrate; Forming a plurality of parallel isolation trenches ( 330 in the substrate; Forming a plurality of gate electrode trenches perpendicular to the isolation trenches (US Pat. 330 ) are arranged; Producing a layer of a gate dielectric ( 250 in the gate electrode trenches and filling the gate electrode trenches with a gate electrode conductive material; Depositing a three-layer stack of gate electrode material, word line material and insulating material, and then etching the three-layer stack to form word lines ( 240 ) extending perpendicular to the gate electrode trenches, the word lines ( 240 ) at least partially vertically above the active areas ( 370 ) of the transistors are placed in the array of transistors. The method of claim 22, wherein forming the Ground plate electrode in the substrate implanting N + ions in a layer of the substrate. A method according to any of the preceding claims 22 to 23, wherein said forming said plurality of parallel isolation trenches ( 330 ) in the substrate comprises etching and filling strips in the substrate. Method for producing an integrated circuit comprising an arrangement of transistors for selecting one of a multiplicity of resistively switching memory cells ( 110 ), wherein the original surface of the substrate forms a horizontal reference plane, comprising the following method steps: forming a ground plate electrode ( 310 in the substrate by deeply implanting N + ions into a layer of the substrate material; Forming a plurality of parallel isolation trenches ( 330 in the substrate by etching and filling the strips in the substrate; Forming a plurality of gate electrode trenches, wherein the gate electrode trenches are perpendicular to the isolation trenches (US Pat. 330 ) and wherein the etching is selective to the insulating material of the isolation trenches ( 330 ), so that the isolation trenches ( 330 ) and the gate electrode trenches active areas ( 370 ) of transistors; Produce a layer of gate dielectric ( 250 in the gate electrode trenches and filling the gate electrode trenches with conductive gate electrode material; Depositing a three-layer stack of gate electrode material, word line material and insulating material and then etching the three-layer stack around word lines ( 230 ) which are perpendicular to the gate electrode trenches, the gate electrodes ( 240 ) by means of the gate electrode material with the word lines ( 230 ) and the word lines ( 230 ) are placed at least partially vertically above the active regions and wherein the etching extends into the gate electrode trenches; Producing a galvanic insulating layer on a sidewall of the three-layer stack and in the gaps in the gate electrode trenches; Depositing a layer of insulating material and filling the gaps between the word lines ( 230 ) with an insulating material; Forming contacts ( 520 ) in the active areas ( 370 ) for creating a contact to a volume ( 610 ) resistive switching material by etching holes which define the surface of active regions ( 370 ) are at least partially exposed, and by filling these holes with a suitable conductive material; Forming volumes ( 610 ) resistively switching material, which is in contact with the contacts ( 520 ) are connected and forming bitlines ( 210 ), with the volume ( 610 ) Resistive switching material are connected. The method of claim 25, wherein a thick oxide layer ( 340 ) and a layer of silicon nitride are deposited on the surface prior to etching the trenches. Method according to one of the preceding claims 25 to 26, wherein the isolation trenches extend into the ground plate electrode ( 310 ). Method according to one of the preceding claims 25 to 27, wherein the active regions formed by the etching of the insulating and the gate electrode trenches ( 370 ) are narrowed so that the active areas ( 370 ) have a bottom surface of an elongated quadrilateral. The method of any one of the preceding claims 25 to 28, wherein after etching the gate electrode trenches, the bottom surface of the gate electrode trenches is N-implanted to be grounded with the ground plane electrode. 310 ) connect to. Method according to one of the preceding claims 25 to 29, wherein the gate electrode trenches partly with gate electrode material and the remaining opening is filled to the reference plane with a dielectric. Method according to one of the preceding claims 25 to 30, wherein before the deposition of the three-layer stack for configuration the semiconductor junctions in the upper range of transistors source implantations are performed. Method according to one of the preceding claims 25 to 31, wherein after the etching of the word lines ( 2309 for implanting ions into the sidewalls of an active area ( 370 ) an oblique drain implantation is performed. Method according to one of the preceding claims 25 to 32, wherein in order to increase the contact area after the etching of the holes for the at least partial exposure of the active areas ( 370 ) and before filling the holes, an epitaxial growth is performed in these holes. Method according to one of the preceding claims 25 to 33, wherein the gate electrode material comprises polysilicon. Method according to one of the preceding claims 25 to 34, wherein the word line material comprises a metal. The method of claim 35, wherein the metal is tungsten is. A method according to any one of the preceding claims 25 to 36, wherein the material for forming the contacts for coupling to a volume of resistively switching material ( 610 ) is a metal. The method of claim 37, wherein the metal is tungsten is.