DE102006041783B3 - Charge-trapping-memory device i.e. Nitride ROM, programming and deletion method, involves executing programming cycle as reference point that is shifted based on wear-level determination, and executing testing process based on threshold - Google Patents

Abstract

The method involves implementing a programming/deletion cycle of a charge trapping memory device as a reference point based on a preset threshold of the charge trapping memory device. A wear-level of the deletion process is determined. The reference point is shifted according to the determination result. Multiple programming-/deletion cycles are implemented based on the shifted threshold. Reading and testing processes are also implemented based of the shifted threshold. An independent claim is also included for a charge-trapping-memory device comprising an oxide layer.

Description

The Invention relates to non-volatile Memory devices, and more particularly to a method of programming nonvolatile Storage devices.

Non-volatile memory devices have been known for several decades. Your essential property is given by the charge stored therein when turning off the device is not lost. In principle, two can be different groups non-volatile Memory devices distinguish: so-called "charge-trapping" devices on the one hand and floating gate devices on the other hand. The invention particularly relates to the former Group.

In Charge trapping storage devices become the electrical charge stored within a nitride adhesive site. A special batch trapping storage device represents a so-called "NROM", whereby a Nitride Read-Only Memory, d. H. a nitride read only memory is characterized. An NROM cell essentially corresponds to an n-channel MOSFET, whose gate oxide is replaced by an oxide-nitride-oxide structure (ONO) is. Enable such cells a permanent storage of charges. Due to the localized Charge storage in NROMs and the symmetrical design of the transistor Is it possible, to store two charge bits per transistor.

Around To program an NROM device, charges must be placed in the nitride layer be injected. Currently exists one mainly used method for programming an NROM device, which is called Hot-Carrier Injection (HCI) or in particular Channel Hot electron (CHE) injection is called. The hot electrons be by applying a high lateral electric field between generates the source and the drain of the transistor. Through this field will be Electrons on their way through the channel from the source to the drain region accelerated. Due to collisions between these electrons can some of them gain enough energy to get that from the lower one Oxide layer of ONO structure formed barrier to pass, if applied a suitable positive voltage to the gate of the transistor is. This effect leads to the trapping, d. H. Capture these hot electrons in the nitride layer.

There the trapping layer is not conductive is and a low conductivity and because of the comparatively low lateral component of the electric field in the charge-trapping layer, become the electrons individually trapped and remain localized within this layer. This is in contrast to the above-mentioned floating gate devices where the charges are stored in a conductive layer, which leads to a lateral mobility of the charges. A negative impact of this mobility represents the potential Flow away the total charge of the storage layer due to only one Point defect in the floating gate insulator. In the case of charge trapping devices lead the mentioned Point defects in the lower insulation layer to no complete charge outflow, but only to a charge loss immediately above the Point defect.

One Clear of the NROM is preferably by injection of hot holes (HH) in the batch trapping layer instead. The hot holes are made after applying a electric field between the drain region and the gate of the transistor generates and tunnels through the bottom oxide layer into the charge trapping layer where these recombine with trapped electrons. In this way, the stored charge cleared.

It It has been proven that the erase and programming capabilities after repeated cycles (programming and erasing) of an NROM cell changes. in the Trap of deletion of the NROM, the extinguishing steplevel goes up while of the cycle on which usually is referred to by the term "ERS degradation". On the other hand, the cells become more sensitive to programming already pre-cycled areas, d. H. with increasing number of cycles. This decreases the stability the efficiency an NROM cell with increasing number of program erase cycles from.

One Another problem in connection with the life of the NROM provides the shift of the self-conduction threshold Vtsc in pre-cycled By programming all cells below the self-threshold let yourself prevent the cell from going into the normally-off state. Self-conduction induces leakage currents while scanning the cells of affected bitlines of an NROM array. this leads to to wrong sampling results and malfunction of all e-sectors, the one belong to a specific section. Self-conduction can be caused by the following effects: a) defects ("kux bits"); b) wrong delete positions; and c) very strong cell length variations, the to a broad erase distribution to lead.

The influence of the pre-cycle on the self-conduction threshold of an NROM is in 1 shown. This figure shows a diagram in which the hot hole current of a memory cell IcellHH of a tested Victim ES (Victim Erasable Sector) over the leakage-source voltage VtLL for different Zy klenan figures are shown. As can be seen from the figure, the self-conducting threshold, which corresponds to the value of the voltage at which the decrease of the hot hole current is completed, shifts by approximately 300 mV after 50,000 cycles (increase from 1.5 V to 1.8 V). This phenomenon can be explained by the model of a WROM cell which detects a shortened channel length after the load caused by repeated programming and erasure. The entry of holes in the charge-trapping layer (nitride layer) results in a shorter effective channel, which is responsible for the increase in the self-conduction threshold Vtsc.

however the increase in the self-threshold can have a negative impact on the sampling accuracy and on a bit line fault in the With respect to shared by a plurality of transistors Exercise bitlines.

In the US 6,937,521 There are various methods for programming and erasing a nonvolatile memory cell. One of the methods includes the steps of determining the voltage level of the programming pulses that are used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level near the programming level of the fast bit. However, this document is not to solve the above problems.

It It is therefore an object of the invention to provide a method of programming and delete of charge trapping storage devices indicate that the above problems are avoided. It is also An object of the invention is a charge trapping storage device to indicate the above disadvantages is not exposed.

The invention is defined in independent claims 1 and 11 Are defined. Further embodiments of the invention are the subject of the dependent claims.

• a) Durchführen wenigstens eines Programmier-/Löschzyklus einer Charge-Trapping Speichervorrichtung auf Ba sis einer gegebenen Schwelle Vth der Charge-Trapping-Speichervorrichtung als Referenzpunkt; b) Bestimmen eines Wear-Levels des Löschvorgangs; c) Verschieben des Referenzpunkts gemäß einem Ergebnis der Bestimmung in Schritt b); d) Durchführen eines oder mehrerer Programmier-Löschzyklen auf Basis der verschobenen Schwelle; und e) Durchführen von Lese- und Überprüfungsvorgängen auf Basis der verschobenen Schwelle. Die Schritte b) bis d) können während der gesamten Lebensdauer der Speichervorrichtung wiederholt ausgeführt werden.

In order to achieve the above objects, the invention provides a method for programming and erasing a batch trapping memory device, the method comprising the following steps:

• a) performing at least one program / erase cycle of a charge trapping storage device based on a given threshold Vth of the charge trapping storage device as a reference point; b) determining a wear level of the deletion process; c) shifting the reference point according to a result of the determination in step b); d) performing one or more program erase cycles based on the shifted threshold; and e) performing read and verify operations based on the shifted threshold. The steps b) to d) can be carried out repeatedly during the entire life of the storage device.

following For example, shifting the reference point is sometimes referred to as "adjusting the cycle window."

In an embodiment has the charge trapping storage device one or more NROM cells. In particular, the batch trapping memory device correspond to a field of NROM cells in a suitable cell architecture.

The Threshold Vth can be one during of deleting between a gate and a source of the charge trapping storage device correspond to applied voltage.

According to one In the aspect of the invention, the determining step comprises counting the already executed Program / erase cycles. This leaves in particular by incorporating a counter in the charge trapping memory device achieve. According to this Aspect becomes the shift step after a predetermined number of cycles carried out, which depends can be adjusted by the type of memory device used. The distance between the number of cycles can be constant or vary. For example, a shift step may be every 100 cycles or every 500 cycles or even every 1000 cycles. On the other hand, the first displacement step after the first 100 Cycles are initiated, with the next shift step after the next 500 cycles, another after 1000 cycles and another after 10,000 cycles.

According to one In another aspect of the invention, the determining step comprises Determine the shift of threshold Vth based on a steplevel of deleting in a previous cycle.

The Shift size in step c) is preferably derived from a look-up table, in which correlates different wear levels with assigned shift sizes are. The look-up table may be in a conventional manner in a particular manner Area of the batch trapping storage device.

• – ein Substrat, in dem ein Sourcegebiet und ein Draingebiet vorgesehen sind, die durch ein Kanalgebiet voneinander getrennt sind;
• – eine untere Oxidschicht, die oberhalb des Kanalgebiets angeordnet ist;
• – eine oberhalb der unteren Oxidschicht angeordnete Charge-Trapping-Schicht;
• – eine oberhalb der Charge-Trapping-Schicht angeordnete obere Oxidschicht; und
• – ein auf der oberen Oxidschicht angeordnetes Gate, wobei die Speichervorrichtung zusätzlich eine Einrichtung zum Bestimmen eines Wear-Levels des Löschvorgangs sowie eine Einrichtung zum Verschieben eines Referenzpunkts bezüglich eines Löschvorgangs in der Speicherzelle enthält. Die betreffende Speichervorrichtung dient insbesondere zum Ausführen des erfindungsgemäßen Verfahrens.

In another aspect, the invention also relates to a charge trapping memory direction with at least one memory cell, wherein the memory cell comprises:

• A substrate in which a source region and a drain region are provided which are separated from each other by a channel region;
• A lower oxide layer disposed above the channel region;
• A charge trapping layer disposed above the lower oxide layer;
• A top oxide layer disposed above the charge trapping layer; and
• A gate disposed on the upper oxide layer, the memory device additionally including means for determining a wear level of the erase operation and means for shifting a reference point with respect to an erase operation in the memory cell. The relevant storage device is used in particular for carrying out the method according to the invention.

Furthermore can the storage device according to the invention a memory section in which a look-up table is stored is where different wear levels correlate with assigned shift sizes are.

Especially For example, the memory cell of the batch trapping memory device may be an NROM.

The Batch-trapping memory device has an intrinsic threshold Vth on, for example, the threshold of above the Gate and the source during Deletion processes created Voltage corresponds. The threshold Vth determines one during the deletion between a gate and a source of the charge trapping memory cell voltage to be applied.

As has already been suggested in connection with the above method can the determining means a counting input for counting already executed program / erase cycles be.

According to one In another aspect of the invention, the determining means comprises a write-only storage section for storing a deleting step level and means for comparing the last erasing step level with one for the Erase step level predetermined Threshold level.

The above features can be suitably combined.

following the invention will be explained in more detail with reference to the figures, which exemplary embodiments and by no means limit the scope of the claims.

1 Fig. 12 is a graph showing the hot hole current of a memory cell IcellHH of a Victim ER (Victim Erasable Sector) being examined above the leakage-source voltage VtLL for various number of cycles;

2 shows a cross-sectional view of an exemplary charge trapping memory cell;

3 and 4 show diagrams on the effect of the cycle window adaptation on the VPPDmax properties during programming and deletion;

5 shows a diagram for bit line interference as a function of the threshold voltage;

6 Figure 11 shows another retention behavior diagram after cycles of adjusted window cycle NROM structures and for fixed cycle window NROM structures; and

7 shows the retention behavior of various NROM structures with a constant cycle window of 1000 mV and with a cycle window adapted according to the invention.

following becomes current preferred embodiments of the invention, examples of which are shown in the accompanying drawings are shown.

2 shows the basic structure of a charge trapping memory cell in the form of an NROM. The cell consists of a substrate 1 , in the given case a p-type substrate, with a source region embedded therein 2 and a laterally spaced drain region 3 , The area of the substrate 1 which is the source area 2 and the drainage area 3 connects, represents a channel to cause an electron drift current, if a voltage between the source region and the drain region is applied. Across the channel is an oxide-nitride oxide stack 4 positioned, which allows a permanent and localized storage of electrons in the nitride layer (adhesive layer). Above the upper of the two oxide layers (upper oxide layer) is a gate 5 , The NROM cell thus represents a transistor.

Due to the localized storage and the symmetrical design of the transistor, it is possible to store two bits per transistor. As is well known to those skilled in the art, when programming using the Channel Hot Electron (CHE) method, a first voltage is applied between the source and drain regions and a second voltage or gate voltage VCCR is applied between the source region and the gate. This accelerates electrons along the channel and hot electrons whose energy is sufficient to pass the lower oxide layer become within the nitride layer of the ONO 4 captured.

3 and 4 show measured values represented in a diagram, wherein the x-axis characterizes the number of program / erase cycles and the y-axis the maximum drain voltage, VPPD max, required for erasure in the case of programming and erasing. The experimental results that led to the above diagrams were obtained using a Qimonda EF11 NROM structure. Since there is a field of NROMs, either a change in a test register of all VCCR gate voltages or the VCCR reference voltages could be selected to adjust the cycle window. In the experiments described below, a change of VCCR was chosen. For cycles (program / erase cycles), an ordinary cycle flow was used with the changes made as follows:
Increasing the cycle window by 100 mV after 100, 500, 1000 and 10,000 cycles. Enlarging the cycle window equals a reduction of the VCCR reference voltage by the mentioned value.

Of the reason for the chosen one Magnification of the Distance of the number of cycles, after an adjustment of the cycle window (Moving the reference point) is located in that Applicants were aware that the decrease in extinguishing efficiency stronger at the beginning of commissioning is nearly saturated towards the end of the life of an NROM. Becomes in practice, a cycle counter for determining the wear level of the erase performance The appropriate number of cycles should be used for each particular device be characterized in advance and stored.

With the mentioned NROM structure, a lifetime experiment including 30,000 program / erase cycles was performed. In the diagrams of 3 and 4 The "Adapt CM" curve indicates the values of an NROM structure whose cycle window was incrementally increased from 600 mV to 1000 mV after the number of cycles mentioned above.As an example, an identical NROM structure with a constant cycle window of 600 mV was tested is characterized as "CM 600mV." Third NROM structures also serve the purpose of comparison and were subjected to the same test, but the cycle window was kept constant at a high value of 1000 mV. "The performance of the third test NROM structures is shown as a curve." CM 1000mV ".

One E-sector (erasable sector, ie erasable sector, which is the smallest to be deleted in one step Unit) was for each of the above cycle windows is cycled.

The behavior of the programming step level VPPDmax can be taken from the diagram of 3 are derived and that of the erase step level VPPDmax is off 4 seen.

In 3 It is shown that the short cycle window test NROM structure has the worst performance especially at the beginning. This is because programmability becomes weaker with an increased cycle window. The best end-of-life results (here: after 30,000 cycles) are achieved with the low constant cycle window, provided that only the programming performance is considered. As a compromise, stable programming performance can be achieved during cycling if the custom cycle window of the present invention is used.

4 shows the VPPDmax properties of the erase performance. Here, the worst performance is achieved using the low constant cycle window, especially at higher cycle counts. The best performance is achieved with the large cycle window, which in contrast showed the worst results in the programming tests. Once again, the adjusted cycle window of the present invention turns out to be stable with respect to the cycle.

to Examination of the bit line fault An NROM field used a so-called "killer pattern" and a victim-delete. The disorder became with 50,000 killers using either the fixed cycle window of 600 mV or the adjusted cycle window, as mentioned above of Changed 600 mV to 1000 mV, carried out. To the disorder On the programmed side, the extinguishing Vinhibit was reduced adapted in parallel to the cycle window scheme.

In the picture in 5 Version 1 represents a switch from 3.1V to 3.5V after 500 cycles, and Version 2 represents a switch from 3.1V to 3.5V after 500 cycles and to 4.3V after 10,000 cycles. The results show a clear difference between the two approaches, CM 600 mV versus the adjusted window of Inhibit ver1. This is because the erase steplevel increased at the 600 mV cycle window during cycling. With one at constant VCCR NEN shunt transistor of the field experiences a floating bit line of the structure a larger voltage difference to a bit line, which is controlled by the increased erase VPPD. This increased voltage difference results in more soft programming of the erased cells. The adjusted cycle window does not undergo this soft-programming because the erase VPPD remains constant and therefore no significant voltage drop is caused between the bit lines. As the figure shows, the inhibit version 2 is overcompensated. The voltage drop on the programmed side represents a superposition of disturbance and retention after the cycle.

In 6 The results of a retention experiment with NROM structures with the above-described adapted cycle window and an NROM structure with a fixed cycle window at 600 mV are shown. The structures were previously subjected to 10,000 cycles with the described killer pattern. The threshold voltage Vth measured at different times up to 60 minutes after the cycles at room temperature is plotted on the y-axis. In addition, the measured threshold voltage after heating for 1 hour at 140 ° C is also shown.

Again 6 can be seen, the NROM structures with adapted window show the same retention behavior as the NROM structures with fixed Zyk lusfenster. If the cycle window is matched to the cell parameters, obviously the same loading conditions can be achieved, even with large cycle windows that resemble larger programming windows (higher programming load).

The comparison between the retention behavior of the NROM with adjusted window and the NROMs with the window fixed at 1000 mV is in 7 shown. From this figure, it can be deduced that there is almost no difference between both approaches of the pre-cycling.

When Result of the preceding investigations is proposed according to the invention, the cycle window after certain stages within the erase / program cycle to increase what a shift of a reference point of an NROM memory device represents. Thus, the cycle windows during use of the adapted to intrinsic NROM properties.

The Adaptation leaves best by using a lookup table, in the move values for the reference points regarding different number of cycles or different previous erase step levels are stored.

A change of the cycle window represents a suitable measure to the upcoming leak threshold On the one hand to circumvent and on the other hand, the deletion and programming power over the To keep life stable.

During the Zyklens rises the extinguishing steplevel which is also called extinguishing degradation referred to as. When enlarging the Cycle windows can be the Cells cleared more easily become. In combination with extinguishing degradation let yourself a stable erase performance over the Achieve lifetime.

As well Can the programming capability stabilized, as already mentioned above. During the cycle can be programming the cells more easily, but weakens an enlarged cycle window the programming efficiency. Along with the adjusted cycle window, over the lifetime becomes a constant Programming capability achieved.

Consequently the steple levels do not increase dramatically, so the strain of the field and the likelihood of error being kept low.

According to one Aspect of the invention does this by storing a cycle count z. In each e-sector of the NROM structure. Based on this count a stored algorithm can be executed which is the appropriate one Adjustment of the cycle window using a stored Lookup table derives. The latter is during characterization or after a process technology change (POA change) define.

According to one second aspect, the cycle window is changed as soon as the erase steplevel is one has reached a certain threshold. The last cycle window is in a backup arrangement Write-only memory of one OTP for each deletion saved.

With The above invention avoids the danger of self-conduction. About that In addition, a reduced bitline disturbance can be achieved, as above is shown. Likewise show NROM memory devices with adapted Cycle window better life retention compared to corresponding NROM devices with fixed cycle window.

Claims (17)

Procedure for programming and deleting batch trapping memory device comprising the steps of: a) performing at least one program / erase cycle of a batch trapping memory device based on a given threshold Vth of the batch trapping memory device as a reference point; b) determining a wear level of the deletion process; c) shifting the reference point according to a result of the determination in step b); d) performing one or more program / erase cycles based on the shifted threshold; e) performing read and verify operations based on the shifted threshold. The method of claim 1, wherein the charge trapping storage device having one or more NROM cells. Method according to claim 1 or 2, wherein the threshold Vth of one during the deletion between a gate ( 5 ) and a source ( 2 ) corresponds to the voltage applied to the charge trapping memory cell. Method according to one of the preceding claims, wherein the steps b) to d) are carried out repeatedly. Method according to one of the preceding claims, wherein the determining step is counting the already executed Includes program / erase cycles. Method according to one of claims 1 to 4, wherein the determining step determining the shift of the threshold Vth based on a Steplevels of deleting in a previous cycle. Method according to claim 5, wherein steps c) to e) every 500 cycles become. Method according to claim 5, wherein steps c) to e) every 100 cycles become. Method according to claim 5, wherein steps c) to e) every 1000 cycles become. Method according to one of claims 1 to 9, wherein the size of the displacement in step c) is derived from a look-up table in which different wear levels correlated with corresponding displacement sizes are. A charge trapping memory device having at least one memory cell, wherein the memory cell comprises: a substrate ( 1 ), in which a source region ( 2 ) and a drainage area ( 3 ) are provided, which are separated from each other by a channel region; A lower oxide layer overlying the channel region; A charge trapping layer above the lower oxide layer; An upper oxide layer disposed over the charge trapping layer; and a gate provided on the upper oxide layer; wherein the memory device additionally includes means for determining a wear level of the erase operation and means for shifting a reference point with respect to an erase operation in the memory cell. A batch trapping storage device according to claim 11, in addition comprising a memory section having a look-up table stored therein; in which different wear levels correlate with assigned displacement sizes are. A batch trapping storage device according to claim 11 or 12, wherein the memory cell is an NROM. Charge trapping memory device according to one of claims 11-13, wherein the charge trapping storage device has an intrinsic threshold Vth has. A charge trapping memory device according to any one of claims 11 to 14, wherein the threshold Vth is one between a gate (15) during erasure. 5 ) and a source ( 2 ) determines the voltage to be applied to the charge trapping storage device. Charge trapping memory device according to one of claims 11 to 15, wherein the determining means comprises a counter to count already engineered Program / erase cycles is. Charge trapping memory device according to one of claims 11 to 15, wherein the determining means is a write-only storage section for Save a deletion step level and means for comparing the last erasing step level with a for the Extinguishing-Step Level has predetermined threshold level.