DE102006036823B4 - Data synchronization and buffer circuit for the synchronization of serially received data signals - Google Patents

Abstract

A data synchronizing and buffering circuit for buffering and synchronizing serially received data signals (Data_in) with an input clock signal (Clock_in), the data synchronizing and buffering circuit comprising:
A data sample and hold register (A / H) for sampling and holding the received data signals (Data_in) with the input clock signal (Clock_in),
A FIFO data register (FIFO-REG) for buffering the data signals sampled with the input clock signal (Clock_in) and held in the sample and hold register (A / H),
A register write control circuit (CTR_G, DEC, FF) is selected for generating a register write pointer (wr_ptr) with the one write unit (L0... L3) of the FIFO data register (FIFO-REG) being dependent on the input clock signal (Clock_in), and
A register read circuit (MUX), which reads out the data signals buffered in the FIFO data register (FIFO REG) depending on an output clock signal (rd_clk) and from a register read pointer (rd_ptr_i), respectively, from the register unit (L0-L3) determined by the register read pointer (rd_ptr_i) and into an output register (AREG),
characterized in that
The data sync and buffer circuit continues to provide a FIFO data register (FIFO-REG) ...

Description

at a currently developed and future on become the market semiconductor memory system to the high Data transfer rates to cope, the data is no longer parallel but from a parent Transferring unit (eg, a memory controller) serially to a semiconductor memory module, buffered there and arranged on the semiconductor memory module semiconductor memory chips distributed. In the reverse direction, the read data from the semiconductor chips also buffered and then serially from the semiconductor memory module to the parent Transfer unit.

The enclosed 1 shows a daisy-chain example of such a "fully buffered" semiconductor memory system with multiple memory modules MMOD1-MMOD4 on each of which a plurality of semiconductor memory chips M1-M8 and a memory buffer chip MB are arranged. The data, such as As write data, command and address signals are from a higher-level unit HOST via a "Southbound" called transmission path, which in 1 from top to bottom, first transferred to the first memory module MMOD1, buffered there and transmitted to the next memory module MMOD2 via the southbound called transmission link, etc. Conversely, the read data signals to be transmitted from the semiconductor memory chips on the individual memory modules MMOD1-MMOD4 to the HOST are sent via a in the 1 from bottom to top leading transmission line which is called "Northbound", transmitted and again buffered in the corresponding buffer chip MB on the respective semiconductor memory modules and continue to transmit. Such a semiconductor memory system is called a fully buffered semiconductor memory system because all write, address and command signals transmitted over the southbound link and then all read data from its own memory module and those arriving via the northbound link are buffered on the memory modules. The memory modules MMOD1-MMOD4 may be DIMM semiconductor modules coupled with DRAM semiconductor memory chips e.g. B. the next generation are equipped.

The bit transfer rate on the high-speed transmission lines "Southbound" and "Northbound" is a multiple the data transfer rate between the semiconductor memory chips M1-M8 and the buffer chip MB. Except the decoding of the specified by a transmission protocol Frame of the transferred to the buffer chips High-speed data, each buffer chip MB decodes read commands and direct the returning, Read data as protocol-specified frames back over the high-speed transmission link Northbound to the parent HOST, the z. B. is a memory controller. The buffer chip MB synchronized this read data with a clock signal and performs the synchronized and read data formatted in read data frames over the northbound transmission link back to the parent Unit HOST.

Everyone Buffer chip MB collects all read data from all memory chips Memory modules MMOD1 and adds combine them into a read data frame (for example, to a 72-bit data word). Here it should be noted that the read data from the nearest Semiconductor memory chip earlier and from a more distant semiconductor memory chip later at one certain buffer chip MB arrive. In the buffer chip MB are therefore advantageously previously measured runtime data especially for the farthest removed memory chip known and stored to one of the position the memory chip on the memory module ent speaking different Enable timing during buffering and synchronization.

to Synchronization and buffering of inbound and outbound Reading data needed the buffer chip MB at its interface to the northbound transmission channel a data sync and buffer circuit. This must be considered Tighter timescales caused by the possibly high number of Semiconductor memory chips on the memory modules and the high transfer rates be set as low as possible Have latency.

In the enclosed 2 schematically shows a block diagram of a conventional data synchronization and buffer circuit integrated in a buffer chip MB, in which the incoming read data Data is first sampled by a sample and hold register A / H with an input clock signal Clock_in and then into a FIFO data register FIFO-REG for buffering, which, according to the data bursts of the read data Data_in, is subdivided into several sections A1-A4 with the same number of bits (eg four bits). A register write control circuit consists of a counter CTR which counts the delayed input clock signal Clock_in and a decoder circuit DEC which decodes the count of the counter CTR and generates for each section A1-A4 an enable signal EN which is supplied by the decoding circuit DEC synchronous with that of the sampling circuit. and holding register A / H sampled read data signals Data in is generated. The output signal of the counter CTR serves as a write pointer wr_ptr for the FIFO data register FIGO-REG. The read data signals buffered in sections A1-A4 of the FIFO data register FIFO-REG become dependent on a register read pointer rd_ptr_i is read out via a register reading circuit designed as a multiplexer MUX and taken over as an output data signal data_o into an output register AREG depending on a read clock rd_clk and a read enable signal rd_en. It should be mentioned that the read clock rd_clk, the read enable signal rd_en and the register read pointer rd_ptr_i are generated internally in the buffer chip MB. It should also be noted that the in 2 can still simplify the data sync and buffer circuit shown by using the registers of the FIFO data register FIFO-REG itself as sample and hold registers. This can happen if the set-up and hold-time conditions at the input are not critical.

It should also be mentioned that the in 2 The conventional data synchronization and buffer circuit shown in FIG. 1 has an error detection device FD which compares the value of the register write pointer wr_ptr with that of the register read pointer rd_ptr_i and generates an error signal fifo_error in the event of an error.

If the requirements at the entrance regarding Set-up and hold times and for the lowest possible latency Critical, it is necessary to one in its set-up and holding time tolerances use optimized sample and hold register A / H, wherein the FIFO write pointer wr_ptr by means of a delay element from the clock edge of the sampling clock can be obtained. The disadvantage is the delay of Data through the in-line devices buffer circuit, Register A1-A4, Multiplexer MUX and also by the sample and hold register A / H including the delay the sampling clock for the FIFO write pointer in the case of a, as mentioned above, optimized Scanning and attitude.

Even when the optimized sample and hold register A / H passes through the FIFO registers and if the register read pointer and the register write pointer have a minimum time interval from each other, carries in each Case caused by the FIFO registers and the control of their release inputs delay as well as the delay from the data input of the FIFO registers to the output and the delay through the multiplexer circuit MUX to the total delay d. H. to the latency of synchronized and buffered read data.

Out WO 2005/066966 A1 (see in particular 2 with related description), a data synchronizing and buffering circuit according to the preamble of claim 1 is known. This known data synchronization and buffer circuit is part z. A memory chip and / or a memory controller chip in a memory system arranged as a "daisy chain" with a point-to-point transmission of the data, as shown in FIG 1 this document is shown.

It It is an object of the invention to provide one with the least possible Latency of the synchronized and buffered read data signals optimized data synchronization and buffer circuit for synchronization serially received data signals having an input clock signal to enable so the above described by too tight time conditions caused problems in the buffer chip do not occur.

These The object is solved by the appended claim 1.

The to the solution The principle proposed in this task is that of the set-up and hold time optimized sample and hold register and a latched transparent FIFO data register to combine with an automatically switched bypass path, over the at certain time-critical situations bypassed the FIFO data register becomes.

• – ein Datenabtast- und -halteregister zum Abtasten und Halten der empfangenen Datensignale mit dem Eingabetaktsignal,
• – ein FIFO-Datenregister zur Pufferung der mit dem Eingabe taktsignal abgetasteten und im Abtast- und Halteregister gehaltenen Datensignale,
• – eine Registerschreibsteuerschaltung zur Erzeugung eines Registerschreibzeigers, mit dem jeweils eine jeweils zum Schreiben bestimmte Registereinheit des FIFO-Datenregisters abhängig vom Eingabetaktsignal ausgewählt wird, und
• – eine Registerleseschaltung, die abhängig von einem Ausgabetaktsignal und von einem Registerlesezeiger die im FIFO-Datenregister gepufferten Datensignale jeweils aus der vom Registerlesezeiger bestimmten Registereinheit ausliest und in ein Ausgaberegister übernimmt, dadurch gekennzeichnet, dass
• – die Datensynchronisier- und -Pufferschaltung weiterhin einen das FIFO-Datenregister umgehenden Bypassweg mit einem vom Ausgangssignal einer Vergleicherschaltung gesteuerten Bypassmultiplexer aufweist, um die mit dem Eingabetaktsignal abgetasteten und im Abtast- und Halteregister abgetasteten und gehaltenen empfangenen Datensignale abhängig von einem durch die Vergleicherschaltung erzeugten Bypassfreigabesignal am FIFO-Datenregister vorbei direkt dem Ausgaberegister zuzuführen, wobei
• – die Vergleicherschaltung den Wert des Registerschreibzeigers mit dem des Registerlesezeigers vergleicht und das Bypassfreigabesignal erzeugt, um den Bypassweg durch den Bypassmultiplexer durchzuschalten, wenn der Wert des Registerschreibzeigers gleich dem des Registerlesezeigers ist,
• – das Datenabtast- und -halteregister ein auf eine minimale Set-Up- und Haltezeit optimiertes Register ist, und
• – das FIFO-Datenregister aus mehreren einen transparenten Zustand annehmenden Latchregistern aufgebaut ist, so dass für den Fall des zum Durchschalten des Bypasswegs akti vierten Bypassmultiplexers an seinen beiden Eingängen jeweils das über den Bypassweg ankommende abgetastete, empfangene Datensignal und gleichzeitig das entsprechende Datensignal von dem zu diesem Zeitpunkt im transparenten Zustand befindlichen FIFO-Datenregister anliegt.

In accordance with a first embodiment, a data synchronizing and buffering circuit according to the invention is for buffering and synchronizing serially received data signals with an input clock signal, the data synchronizing and buffering circuit comprising:

• A data sample and hold register for sampling and holding the received data signals with the input clock signal,
• A FIFO data register for buffering the data signals sampled with the input clock signal and held in the sample and hold register,
• A register write control circuit for generating a register write pointer for respectively selecting a respective write unit of the FIFO data register in response to the input clock signal, and
• A register read circuit, which, depending on an output clock signal and a register read pointer, reads out the data signals buffered in the FIFO data register from the register unit determined by the register read pointer and transfers them to an output register, characterized in that
• The data sync and buffer circuit further comprises a bypass path bypassing the FIFO data register with a bypass multiplexer controlled by the output of a comparator circuit for receiving the data signals sampled and held with the input clock signal and sampled and held in response to a bypass enable signal generated by the comparator circuit past the FIFO data register directly to the output register, wherein
• The comparator circuit compares the value of the register write pointer with that of the register read pointer and generates the bypass enable signal to switch the bypass path through the bypass multiplexer when the value of the register write pointer is equal to that of the register read pointer,
• The data sample and hold register is a register optimized for a minimum set-up and hold time, and
• - The FIFO data register is constructed of a plurality of transparent state accepting latch registers, so that in the case of activating the bypass path acti fourth bypass multiplexer at its two inputs respectively via the bypass path sampled, received data signal and at the same time the corresponding data signal from the this time in the transparent state FIFO data register is present.

Although the problems to be solved by the embodiment of the data synchronization and buffer circuit are initially described using the example of a fully buffered semiconductor memory system (US Pat. 1 ) and a conventional buffer-integrated data synchronizing and buffering circuit ( 2 ), it should be explicitly noted that the inventive data synchronization and buffer circuit is not limited to the application in a buffer chip MB of such a memory system, but is applicable wherever a serial data stream with an input clock signal while maintaining a minimum latency for the data signals to be synchronized, ie that the data synchronization and buffer circuit according to the embodiment can also be operated as clock signals with a continuous clock and not only with the read data bursts of a fully buffered semiconductor memory system accompanying DQS signals.

Advantage oats way The Bypassweg switching Bypassmultiplexer automatically controlled so that the date passing through the FIFO data register becomes transparent arrives at the input of the bypass multiplexer before the bypass path turns off again becomes. This is in the case of the switched bypass path thereby achieved that delay of the data signal passing through the transparent state Register unit of the FIFO data register and by the register read circuit is applied to the first input of the bypass multiplexer is shorter than the delay when disabling the bypass path, d. H. when switching off the bypass enable signal.

• – die empfangenen Datensignale aus jeweils n-Speicherlesedatenbits umfassenden Datenbursts bestehen,
• – das Eingabetaktsignal ein mit jedem Lesedatenbit des Bursts synchrones Datenstrobesignal ist,
• – das Datenabtast- und -halteregister aus n Einzelregistern aufgebaut ist,
• – der Bypassweg und der Bypassmultiplexer jeweils n Bits umfassen,
• – das FIFO-Datenregister zum Puffern der Bursts in eine Anzahl m gleich langer Registerabschnitte unterteilt ist, die jeweils einer Registereinheit entsprechen, deren Bitlänge jeweils der Anzahl n der Lesedatenbits entspricht,
• – sowohl der von der Registerschreibsteuerschaltung erzeugte Schreibzeiger als auch der Registerlesezeiger einen jeweiligen Abschnitt des FIFO-Datenregisters zum burstweisen Einschreiben und Auslesen der Bursts auswählen, und
• – die Registerlesevorrichtung eine m:n Multiplexerschaltung aufweist, die entsprechend dem Wert des Registerlesezeigers die Bursts aus den Abschnitten des FIFO-Datenregisters zu einem seriellen Strom von Ausgabebursts mit jeweils n Bits vereinigt.

Another embodiment of the data synchronization and buffer circuit is characterized in that

• The received data signals consist of data bursts each comprising n memory read data bits,
• The input clock signal is a data strobe signal synchronous with each read data bit of the burst,
• The data sample and hold register is made up of n individual registers,
• The bypass path and the bypass multiplexer each comprise n bits,
• - the FIFO data register for buffering the bursts is subdivided into a number of m equal length register sections, each corresponding to a register unit whose bit length corresponds in each case to the number n of the read data bits,
• Both the write pointer generated by the register write control circuit and the register read pointer select a respective section of the FIFO data register for burst-by-burst writing and reading, and
• The register reading device has an m: n multiplexer circuit which, in accordance with the value of the register read pointer, combines the bursts from the sections of the FIFO data register into a serial stream of output bursts of n bits each.

• – der Bypassweg und der Bypassmultiplexer vier Bit umfassen, und
• – das Datenabtast- und -halteregister vier Einzelregister aufweist.

According to a variant of this embodiment of the data synchronizing and buffering circuit, n is equal to 4, so that each data burst comprises four read data bits and each register section of the FIFO data register is made up of four latch registers,

• The bypass path and the bypass multiplexer comprise four bits, and
• - The data sample and hold register has four individual registers.

• – die Anzahl m der Registerabschnitte des FIFO-Datenregisters gleich vier ist,
• – die Registerschreibsteuerschaltung einen Drei-Bit-Grayzähler, dem das Eingabetaktsignal um eine Vierteltaktperiode verzögert zugeführt wird, und
• – einen mit dem den Registerschreibzeiger angebenden Drei-Bit-Ausgangssignal des Grayzählers beaufschlagten Dreiaus-Vier-Decodierer aufweist, der aus dem Wert des Registerschreibzeigers ein Freigabesignal für einen jeweils zum Schreiben freizugebenden Registerabschnitt decodiert.

Furthermore, this variant of the embodiment of the data synchronization and buffer circuit is characterized in that

• The number m of register sections of the FIFO data register is four,
• The register write control circuit supplies a three-bit Gray counter to which the input clock signal is delayed by one quarter-clock period, and
• - Has a three-of-four decoder applied to the register write pointer indicating three-bit output of the Gray counter, which decodes from the value of the register write pointer an enable signal for a respective write-to-write register section.

Further preferred in this variant of the register read pointer is also a three-bit signal and the comparator circuit has three XOR gates and an output signal applied to their AND gate whose output signal indicates that the value of the register write pointer matches that of the register read pointer, thereby enabling the bypass path through the bypass multiplexer.

at another variant of the embodiment is the number m of register sections of the FIFO data register is two, and the register write control has a toggle flip-flop whose State is switched by each clock pulse, wherein the register write pointer is a one-bit signal.

Farther preferred is in the latter variant of the embodiment the register read pointer is also a one-bit signal and the register write pointer with the register read pointer comparative comparator circuit an XOR member and an AND gate with two inputs, whose one input is the output of the XOR gate and its another input receives the input clock signal delayed by one quarter-clock period, and its output indicates that the value of the register write pointer matches the register read pointer and thus releases the bypass path through the bypass multiplexer.

As mentioned, the present data synchronizing and buffering circuit is provided in a memory buffer chip for a semiconductor memory system having fully buffered memory modules, for example according to FIG 1 used, the memory chips each read data signals buffered by each buffer chip to a higher-level memory control unit HOST and thereby serves to synchronize and buffer the read data signals with the input clock signal.

The above and other advantageous objects and features of this invention In the following detailed description of exemplary embodiments, which refers to the accompanying drawings, even more clarified.

The Drawing figures show in detail:

1 the fully-buffered semiconductor memory system already explained at the outset, in which a buffer chip is arranged on each memory module equipped with semiconductor memory chips, in which the data synchronization and buffer circuit described here can be implemented by the memory chips to synchronize the read data signals serially received by the buffer chip;

2 a schematic block diagram of a previously discussed conventional data synchronization and buffer circuit without bypass path;

3 a schematic block diagram of a first embodiment of a data synchronization and buffer circuit according to the invention;

4 a first signal timing diagram, the signals important in understanding the function of in 3 in the case of a relaxed situation in which the register write pointer and the register read pointer have a relatively large time interval;

5 a second signal timing diagram according to the embodiment of the data synchronizing and buffer circuit according to 3 important signals, wherein the register write pointer and the register read pointer have a very small time interval from each other;

6 a signal timing diagram for explaining the function of the internally shifted by a quarter-clock period DQS signal in the edge-triggered acquisition of the DQ data and

7 a schematic block diagram of a second embodiment of a data synchronizing and buffer circuit according to the invention with only two register sections of the FIFO data register, which corresponds to a register depth of two, in which the Registerschreibsteuerschaltung, the Registerle seschaltung and the comparator circuit over the in 3 shown first embodiment are simplified.

As mentioned, consist of essential parts of the data synchronizing and Buffer circuit in the combination of a lower Set-up and hold time optimized sample and hold register with a built-in latches FIFO register and the bypass path, at the bypass multiplexer asynchronously dependent on a comparison of the Register write pointer is driven with the register read pointer.

Accordingly, this is shown in the schematic block diagram in FIG 3 illustrated first embodiment on the left side of the optimized in terms of low set-up and hold times Datenabtast- and -halteregister A / H, which samples the received data signals Data_in with delayed by a delay element DEL by a quarter clock period input clock signal Clock_in and holds and the sampled data signals Data_in as sampled signal smpl_out outputs at the output.

To explain the function of the embodiment of 3 show the signal timing diagrams in the 4 and 5 the temporal conditions of important in 3 designated signals in two different temporal situations, namely in a first, temporally relaxed Situati on, in which the time interval between the register write pointer wr_ptr and the register read pointer rd_ptr_i is relatively large ( 4 ) and a second time-constrained situation in which the time interval between the register write pointer wr_ptr and the register read pointer rd_ptr_i is very small. The latter situation occurs when the present data sync and buffer circuit in a buffer chip MB according to

1 is integrated and when reading data signals from a distant memory chip, eg. B. the farthest memory chip receives, synchronizes and buffers. As mentioned, the FIFO data register FIFO-REG consists of latch registers, which are transparent in the enabled state EN. The FIFO data register FIFO-REG is for buffering DQ read data in the embodiment of FIG 3 divided into m sections L0-L3 (here m = 4) of the same bit length, that is, each section L0, L1, L2 and L3 consists of four latches by each one four-bit data burst of the received data read data is registered in or buffered ,

Furthermore, the embodiment of the 3 a register write control circuit consisting of a Gray counter CTR G and a three-to-four decoder 3: 4 DEC. The gray counter CTR G counts clock_in with the inverted input clock signal delayed by one quarter clock period and outputs the three-bit register write pointer wr_ptr according to the following scheme: Gray code wr_ptr 3: 4Dec 0 000 EN 0 1 001 EN1 2 011 EN2 3 010 EN3 4 (0) 110 EN1 5 (1) 111 EN2 6 (2) 101 EN3 7 (3) 100 EN4

Of the Three-to-four decoder decodes from this Gray code, i. H. out the register write pointer wr_ptr the register enable signals EN0, EN1, EN2, EN3 respectively for enabling the register sections L0, L1, L2 and L3.

The first twelve lines of the 4 and 5 show in each case the temporal relationship between the input clock signal Clock_in, the input read data signals a0, a2, a4, a6, b0, b2, b4, b6 (four bits each), the sampled data signals smpl_out occurring at the output of the sample and hold register A / H, the count state of the gray counter CTR G (fourth line), the output signals of the three-to-four decoder 3: 4 DEC and the register enable signals EN0-EN3, as indicated by an AND gate at the enable input of each register section L0-L3 from the link the output signals of the 3: 4 decoder 3: 4 DEC are generated with the input clock signal Clock_in delayed by the delay element DEL by a quarter-clock period. In the next four lines, the data signals a0, a2, a4, a6 and b0, b2, b4 and b6 latched by the register enable signals into the latches of the FIFO data register FIFO-REG, ie their register sections L0-L3, are shown.

At the The output of the FIFO data register FIFO-REG is one of a multiplexer MUX existing register read circuit arranged whose inputs the from the FIFO data register FIFO-REG latched, d. H. buffered data signals issue. The register read circuit MUX reads depending on the the circuit from the outside applied register read pointer rd_ptr_in, which is also a three-bit signal and which is decoded into a two-bit signal stored in the FIFO data register FIFO REG buffered data signals each from the through the register read pointer rd_ptr_i specific register section L0, L1, L2, L3 and stores these dependent from an input clock signal rd_clk and a read enable signal rd_en_in the output register AREG.

A comparator circuit VGL consists of three XOR gates, to whose inputs the three-bit register write pointer wr_ptr and the three-bit register read pointer rd_ptr_i are supplied. The outputs of the three XOR gates are connected to the inputs of an AND gate of the comparator circuit VGL whose output signal, if the value of the register write pointer wr_ptr is equal to that of the register read pointer rd_ptr_i, as bypass enable signal bypass_en a bypass multiplexer BYPASS-MUX releases and thus the bypass BYPASS past the FIFO data register to the output register AREG. As mentioned, the register write pointer wr_ptr and the register read pointer rd_ptr_i, which is supplied to the data sync and buffer circuit from outside, ie, from other circuits of the buffer chip, are generated asynchronously with each other. Whenever the three-bit value of the register write pointer wr_ptr at the output of the gray counter CRT_G agrees with the three-bit value of the register read pointer rd_ptr_i, the XOR gates in the comparator circuit VGL detect this, so that the BYPASS bypass path can be read by the BYPASS bypass multiplexer via its AND element. MUX is switched through by means of the bypass enable signal bypass_en. Since the register read pointer can be incremented immediately after registering the output data data_o in the output register AREG on the read side, the timing when switching the bypass path at the bypass multiplexer is not critical. This means that the bypass multiplexer BY PASS-MUX can already turn on the bypass path if the new data has not yet arrived at the output of the sample and hold register A / H.

When the next data burst of the input data signals Data_in arrives at the sample and hold register A / H and is clocked in by the one-quarter clock period delayed by the delay element DEL edge of the input clock signal Clock_in, and this appears as signal smpl_out at the output of the sample and hold register, it will directly through the opened by the bypass multiplexer BYPASS MUX bypass BYPASS to the read side, ie passed to the output register AREG. By means of an optimally positioned read clock rd_clk_in and read enable signal rd_en, the data on the read side can be output immediately with the lowest latency. At the same time, the data smpl_out at the output of the sample and hold register A / H are fed through the non-designated buffer member provided there to all latches of the corresponding section L ₀ , L ₁ , L ₂ or L _{3 of} the FIFO data register FIFO-REG. A portion of the FIFO data register z. B. L0 is enabled by the applied enable signal EN0, so that the data are applied to the multiplexer MUX of the register read circuit. In 3 this is the 4: 1 multiplexer MUX. Since the register write pointer wr_ptr and the register read pointer rd_ptr_i have the same value in this case, the data is switched by the 4: 1 multiplexer MUX of the register read circuit and arrives at the corresponding input of the bypass multiplexer BYPASS-MUX (cf. 5 The register write pointer wr_ptr is incremented with the delayed clock edge of the input clock Clock_in and also the selected section of the FIFO data register FIFO-REG is closed with this delayed clock edge. In 3 This delay is realized by the delay element DEL and by the inverter at the input of the gray counter CTR_G, and therefore the input data are sampled with the rising edge of the input clock and the register write pointer vor_ptr is incremented with the next falling edge of the input clock Clock_in. The incrementing of the register write pointer wr_ptr is detected by the XOR elements of the comparator VGL and thereby the bypass enable signal bypass_en is deactivated via the AND gate of the comparator VGL (cf. 5 ).

Care must be taken in the comparator circuit VGL that there is no race situation that would cause the BYPASS bypass path to be released during normal operation of the FIFO data register FIFO-REG and thereby interfere with the function of the latter. For this reason, the in 3 The data synchronizing and buffering circuit of this embodiment has a gray coded register write pointer wr_ptr and a gray coded register read pointer rd_ptr_i which ensure that no race condition occurs in the comparator circuit VGL.

Another requirement is that the by-pass multiplexer BYPASS-MUX should not generate glitches while switching between its two input signals, if they have the same value. In order to avoid this, that ensures in 3 shown embodiment that the delay of the data passing through the buffer member to the sample and hold register A / H and the shared FIFO data register FIFO-REG and the 4: 1 multiplexer MUX at the output of the FIFO data register data is shorter than the delay which experiences the clock edge of the input clock Clock_in plus the delay in incrementing the gray counter CRT_G plus the delay of the comparator circuit VGL. This ensures that the same data is present at the two inputs of the bypass multiplexer BYPASS-MUX at the time when the BYPASS bypass path is again blocked. Since no interference signals thus occur at the output of the bypass multiplexer, there is also no change in the output data data_o at the output of the bypass multiplexer BYPASS-MUX. For this reason, the position of the clock edge of the read-side clock signal rd_clk and the edge of the read enable signal rd_en can occur completely independently (asynchronously) from whether the BYPASS bypass path is enabled or not. This fact is in the signal timing diagram of 5 with respect to the temporal position of the output data data_o represented in the last line of the time diagram by the vertical dashed lines.

It should be noted once again that the signal timing diagram of 4 shows the relaxed situation, in which there is a large time interval between the register write pointer wr_ptr and the register read pointer rd_ptr_i and in which the bypass path BYPASS is not switched through and 5 shows the temporally strained situation with a minimum time interval between the register write pointer wr_ptr (illustrated by the edges of the output signals of the 3: 4 decoder 3: 4 DEC) and the register read pointer rd_ptr_i shown in the second last line where the bypass path is switched through (see signal bypass_en in the third to last line of the 5 ).

Of course, it must be checked whether the set-up time requirements of the latch registers L0-L3 of the FIFO data register FIFO-REG when using the delayed edge of the input clock Clock_in for closing the latches are met. Here in this example, the input data Data_in is sampled with the rising edge of the input clock Clock_in, and the latch registers L0-L3 of the FIFO data register FIFO-REG are sampled with the falling edge of the input clock closed. This is illustrated 6 in the case of implementing the present data synchronizing and buffering circuit in a memory buffer chip for a semiconductor memory system with fully buffered memory modules, as e.g. In 1 1, the delay of the input clock Clock_in, which in this embodiment is the data strobe signal DQS, is one quarter clock period, such that an internally delayed clock signal DQS occurs to ensure that the input read data DQ is sampled with the rising edge of the internally delayed data strobe signal DQS the latch registers of the FIFO data register FIFO-REG can be closed with its falling edge.

A second simplified embodiment of the data synchronization and buffer circuit according to the invention is shown as a block diagram in FIG 7 shown. In this second embodiment, the FIFO data register FIFO-REG has only two register sections L0 and L1 (corresponding to a register depth of two). This simplifies the register write control circuit which generates the register write pointer wr_ptr and consists only of a simple toggle flip-flop FF and an inverter, the multiplexer MUX which is a 2: 1 multiplexer and the comparator circuit VGL which only has one XOR Member and an AND member. In addition, the input clock signal Clock_in delayed in the comparator circuit by the delay element DEL by one quarter-clock period is supplied to the AND gate as a second input signal to generate the by-pass BYPASS-enabling bypass enable signal bypass_en. For comparison, in the embodiment, the data synchronizing and buffering circuit is different 3 the "empty" condition of the FIFO data register FIFO-REG and its "full" condition only by one bit in the increment of the FIFO write pointer wr_ptr. This means that at a register depth of four as in the FIFO data register FIFO-REG the 3 a three-bit register write pointer wr_ptr was used. Instead, in the embodiment of the 7 the register write pointer wr_ptr and also the register read pointer rd_ptr_i each only one bit position (0 or 1).

To mention is still that the error detector FD at the in 3 and 7 illustrated embodiments has the same function as in the in 2 shown conventional circuit.

• – ein Datenabtast- und -halteregister zum Abtasten und Hal ten der empfangenen Datensignale mit dem Eingabetaktsig nal,
• – ein FIFO-Datenregister zur Pufferung der mit dem Eingabetaktsignal abgetasteten und im Abtast- und Halteregister gehaltenen Datensignale eingerichtet ist,
• – eine Registerschreibsteuerschaltung zur Erzeugung eines Registerschreibzeigers mit dem jeweils eine jeweils zum Schreiben bestimmte Registereinheit des FIFO-Datenregisters abhängig vom Eingabetaktsignal ausgewählt wird, und
• – eine Registerleseschaltung, die abhängig von einem Ausgabetaktsignal und von einem Registerlesezeiger die im FIFO-Datenregister gepufferten Datensignale jeweils aus der vom Registerlesezeiger bestimmten Registereinheit ausliest und in ein Ausgaberegister übernimmt.

The previously described and in the 3 to 7 Illustrated embodiments describe a data sync and buffer circuit for buffering and synchronizing serially received data signals with an input clock signal, the data sync and buffer circuit comprising:

• A data sample and hold register for sampling and holding the received data signals with the input clock signal,
• A FIFO data register is set up for buffering the data signals sampled with the input clock signal and held in the sample and hold registers,
• A register write control circuit for generating a register write pointer, each of which is selected a respective write unit of the FIFO data register in response to the input clock signal, and
• - A register read circuit, which reads depending on an output clock signal and a register read pointer buffered in the FIFO data register data signals respectively from the particular register from the register pointer register unit and takes over in an output register.

• – die Vergleicherschaltung den Wert des Registerschreibzeigers mit dem des Registerlesezeigers vergleicht und das Bypassfreigabesignal erzeugt, um den Bypassweg durch den Bypassmultiplexer durchzuschalten, wenn der Wert des Re gisterschreibzeigers gleich dem des Registerlesezeigers ist,
• – das Datenabtast- und -halteregister ein auf eine minimale Set-Up- und Haltezeit optimiertes Register ist, und
• – das FIFO-Datenregister aus mehreren, einen transparenten Zustand annehmenden Latchregistern aufgebaut ist, so dass für den Fall des zum Durchschalten des Bypasswegs aktivierten Bypassmultiplexers dieser an seinen beiden Eingängen jeweils das über den Bypassweg ankommende Datensignal und gleichzeitig das entsprechende Datensignal von dem zu diesem Zeitpunkt im transparenten Zustand befindlichen FIFO-Datenregister anliegt.

This data sync and buffer circuit further includes a bypass path bypassing the FIFO data register with a bypass multiplexer controlled by the output of a comparator circuit for receiving the data signals sampled and held with the input clock signal and sampled and held in response to a bypass enable signal generated by the comparator circuit past the FIFO data register directly to the output register, wherein

• - the comparator circuit compares the value of the register write pointer with that of the register read pointer and generates the bypass enable signal to switch the bypass path through the bypass multiplexer when the value of the register write pointer is equal to that of the register read pointer,
• The data sample and hold register is a register optimized for a minimum set-up and hold time, and
• - The FIFO data register is made up of a plurality of latching registers assuming a transparent state, so that in the case of the bypass path activated by the Bypassmultiplexers this at its two inputs respectively via the bypass path incoming data signal and at the same time the corresponding data signal from the at this time is present in the transparent state FIFO data register.

Such a data synchronization and buffer circuit can be implemented in an application case in a memory buffer chip for a semiconductor memory system with fully buffered memory modules, the memory chips each read data signals DQ buffered by each buffer chip to a higher-level unit, such as. B. a memory control unit and in another one set case for the synchronization and buffering of a continuous data signal stream, wherein the input clock signal is a continuous clock signal and each register unit of the FIFO data register consists of a single, corresponding to a single bit of the signal stream latch register.

It should also be noted that in the case of implementing the data synchronization and buffer circuit described above and consistent with the embodiments in a memory buffer chip for a semiconductor memory system with fully buffered memory modules and the use of the present data synchronization and buffering circuit to synchronize and buffer the DQ Signals having the data strobe signal DQS, this data sync and buffer circuit is duplicated in the memory buffer chip, namely firstly for the synchronization and buffering of the even-numbered bits a0, a2, a4, a6; b0, b2, b4, b6, as in 4 and separately therefrom, a second identical circuit for synchronizing and buffering the odd bits a1, a3, a5, a7, etc. of the DQ read data.

MB

buffer chip

M1-M8

Semiconductor memory chip

MMOD1-MMOD4

memory module

HOST

parent Memory controller

FIFO REG

FIFO

A1-A4; L0-L3

Register unit; register section

Data_in

input data

CLOCK_IN

Input clock signal

DEL

delay

AH

sampling and holding registers

CTR

counter

CTR_G

Gray counters

DEC

decoder

MUX

multiplexer

AREG

output register

FD

Error decoder

BYPASS

bypass path

BYPASS MUX

bypass multiplexer

EN

Latchfreigabeeingang

EN0 EN3

latch enable

SEE

comparator

smpl_out

sampled Input data signal

wr_ptr

Register write pointer

bypass_en

Bypass enable signal

rd_ptr_i

Register read pointer

data_o

output data

data_reg_o

output of the output register AREG

rd_clka

Read clock signal

rd_en

Read enable signal

fifo_error_o

FIFO error output signal

a0, a2, a4, a6; b0, b2, b4, b6

 input data or input data bursts

FF

Flip-flop

DQ

Read data signal = Input data signal

DQS

data strobe = Input clock signal

Claims (12)

A data synchronizing and buffering circuit for buffering and synchronizing serially received data signals (Data_in) with an input clock signal (Clock_in), the data synchronizing and buffering circuit comprising: - a data sample and hold register (A / H) for sampling and holding the received one Data signals (Data_in) with the input clock signal (Clock_in), a FIFO data register (FIFO-REG) for buffering the data signals sampled with the input clock signal (Clock_in) and held in the sample and hold register (A / H), a register write control circuit (CTR_G , DEC, FF) for generating a register write pointer (wr_ptr) with the one writing unit (L0 ... L3) of the FIFO data register (FIFO-REG) depending on the input clock signal (Clock_in) is selected, and - a register read circuit ( MUX) dependent on an output clock signal (rd_clk) and a register read pointer (rd_ptr_i) puffed in the FIFO data register (FIFO-REG) erten data signals in each case from the register read pointer (rd_ptr_i) certain register unit (L0-L3) reads and takes in an output register (AREG), characterized in that - the data sync and buffer circuit further bypassing the FIFO data register (FIFO-REG) Bypass (BYPASS) with a by the output of a comparator circuit (VGL) controlled bypass multiplexer (BYPASS-MUX) to the sampled with the input clock signal (Clock_in) and in the sample and hold register (A / H) sampled and held received data signals depending on a by the comparator circuit (VGL) generated bypass enable signal (bypass_en) past the FIFO data register (FIFO-REG) directly to the output register (AREG), where - the comparator circuit (VGL) the value of the register write pointer (wr_ptr) with that of the register read pointer (rd_ptr_i) and the bypass enable signal (bypass_en) is generated to bypass the bypass path (BYPASS) by the Byp by-pass multiplexer (BYPASS-MUX) if the value of the register write pointer (wr_ptr) equals that of the Re gisterlesen pointer (rd_ptr_i) is. Data synchronization and buffer circuit according to claim 1, characterized in that The data sample and hold register (A / H) a register optimized for a minimum set-up and hold time is. Data synchronization and buffer circuit according to claim 1 or 2, characterized in that - the FIFO data register (FIFO-REG) of several, assuming a transparent state Latch registers (L0-L3) is constructed, so for the case of enabling the bypass path (BYPASS) Bypass multiplexer (BYPASS-MUX) at its two inputs each the above the bypass path (BYPASS) incoming received data signal and simultaneously the corresponding data signal from the at that time in transparent State FIFO data register (FIFO-REG) is present. Data synchronization and buffer circuit according to claim 3, characterized in that in the case of the through-connected bypass path the delay of the data signal passing through the transparent state Register unit (L0-L3) of the FIFO data register (FIFO-REG) and by the register read circuit (MUX) at the first input of the bypass multiplexer (BYPASS-MUX) is shorter than the delay in the Disabling Bypass Path (BYPASS). Data synchronization and buffer circuit according to claim 3 or 4, characterized in that the received data signals form a continuous signal stream and the input clock signal is a continuous clock signal, each register unit of the FIFO data register (FIFO-REG) from a single to a single Bit of the signal stream corresponding latch register exists. Data synchronization and buffer circuit according to claim 3 or 4, characterized in that - the received Data signals from each n memory read data bits (DQ) data bursts, The input clock signal (Clock_in) a data strobe signal synchronous with each read data bit (DQ) of the burst (DQS) is, - the Data sample and hold registers (A / H) built from n single registers is - of the Bypass path (BYPASS) and the bypass multiplexer (BYPASS-MUX) each n bits include, - the FIFO data register (FIFO-REG) for buffering the bursts into a number m equal length register sections (L0-L3) is divided, each correspond to a register unit, the bit length of each of the number n of Read data bits corresponds - either that generated by the register write control circuit (CTR, DEC; FF) Write pointer (wr_ptr) as well as the register read pointer (rd_ptr_i) a respective section (L0-L3) the FIFO data register (FIFO-REG) for bursty writing and reading out the bursts, and - the Register reading device has an m: n multiplexer circuit (MUX), which according to the value of the register read pointer (wr_ptr) the bursts from the sections of the FIFO data register (FIFO-REG) to one serial stream of output bursts of n bits each. Data synchronization and buffer circuit according to claim 6 characterized in that n is equal to four, such that: - everyone Data burst comprises four read data bits (DQ), - everyone Register section (L0-L3) of the FIFO data register is composed of four latch registers, - the bypass route (BYPASS) and the bypass multiplexer (BYPASS-MUX) comprise four bits, and - the data sampling and hold registers (A / H) has four individual registers. Data synchronization and buffer circuit according to claim 6 or 7, characterized in that - the number m of the register sections (L0-L3) of the FIFO data register (FIFO-REG) is four, The register write control circuit a three-bit Gray counter (CTRG), the input clock signal (Clock_in) by one quarter-clock period is supplied delayed, and one indicating the register write pointer (wr_ptr) Three-bit output of the gray counter (CTR_G) acted upon Three-out-of-four decoder (3: 4DEC), derived from the value of Register write pointer (wr_ptr) a enable signal (EN0-EN3) for a each to be released for writing register section (L0-L3) decoded. Data synchronization and buffer circuit according to claim 7 or 8, characterized in that the register read pointer (rd_ptr_i) also a three-bit signal and the comparator circuit (VGL) is three XOR gates and an AND gate applied with their output signals whose output signal indicates that the value of the register write pointer (wr_ptr) matches that of the register read pointer (rd_ptr_i) and thus the bypass path (BYPASS) through the bypass multiplexer (BYPASS-MUX) releases. Data synchronizing and buffering circuit according to claim 6 or 7, characterized in that - the number m of the register sections of the FIFO Da ten register (FIFO-REG) is two, and - the register write control circuit has a toggle flip-flop (FF) whose state is switched by each clock pulse, the register write pointer (wr_ptr) being a one-bit signal. Data synchronization and buffer circuit according to claim 10, characterized in that the register reading pointer (rd_ptr) is also a one-bit signal, the register write pointer (wr_ptr) with the register read pointer (rd_ptr_i) comparative comparator circuit (VGL) has an XOR gate and a two-input AND gate, one input of which is the output of the XOR gate, the other one Input the input clock signal delayed by a quarter of a clock cycle (Clock_in) receives and its output indicates that the value of the register write pointer (wr_ptr) matches that of the register read pointer (rd_ptr_i) and thus the bypass path (BYPASS) through the bypass multiplexer (BYPASS-MUX) releases. Memory buffer chip for a semiconductor memory system with fully buffered memory modules (MMOD1-MMOD4), their memory chips (M1-M8) respectively Read data signals (DQ) buffered by each buffer chip to a parent Memory controller (HOST) transmit, characterized in that the memory buffer chip is a data synchronizer and buffer circuit according to one of claims 1 to 11 for buffering and synchronizing the read data signals (DQ) with the input clock signal (Clock_in; DQS).