DE102006032131A1 - Serial to parallel and parallel to serial converter for digital data is based on coupled latching registers - Google Patents

Serial to parallel and parallel to serial converter for digital data is based on coupled latching registers

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Publication number
DE102006032131A1
DE102006032131A1 DE102006032131A DE102006032131A DE102006032131A1 DE 102006032131 A1 DE102006032131 A1 DE 102006032131A1 DE 102006032131 A DE102006032131 A DE 102006032131A DE 102006032131 A DE102006032131 A DE 102006032131A DE 102006032131 A1 DE102006032131 A1 DE 102006032131A1
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DE
Germany
Prior art keywords
bits
data
parallel
serial
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102006032131A
Other languages
German (de)
Inventor
Kyu-hyoun Suwon Kim
Moon-Sook Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR1020050060444A priority Critical patent/KR100615580B1/en
Priority to KR10-2005-0060444 priority
Priority to US11/430,281 priority
Priority to US11/430,281 priority patent/US7522440B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102006032131A1 publication Critical patent/DE102006032131A1/en
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa

Abstract

The serial to parallel converter circuit handles a data stream of m bits where the m bits contains 2n data bits and k data bits. The data is received by a first register [162] consisting of m-1 D type register latches [DF]. This is coupled to a second register having m register stages [164].

Description

  • The The present invention relates to a serial-to-parallel converter Method for converting a serial bit stream into a parallel one Bitstream, a parallel-to-serial converter, a method of conversion a parallel bit stream into a serial bit stream, a control signal generator circuit, a method for generating a control signal, a memory element, a method of writing data into a memory cell array and for reading data from a memory cell array and Storage system.
  • 1A shows an example of a conventional memory system. As shown, a conventional memory system may include a memory controller 100 and a memory module 200 include. The memory module 200 may further comprise a plurality of memory elements 200-1 . 200-2 . 200-x include, which may be implemented in the form of DRAMs, for example.
  • The storage control unit 100 For example, an external clock signal ECLK, one or more command signals COM, such as a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB and a chip select signal CSB, one or more address signals ADD, and / or one or more data signals DATA can be applied to the memory module 200 output.
  • The memory module 200 may further include one or more data signals DATA to the memory controller 100 output. In the in 1A As shown, the one or more data signals DATA may be formed of a serial stream of 2 n bits, which is represented by [1: 2 n ] DATA11 to [1: 2 n ] DATAxj. As in 1A can be a memory element 200-1 the external clock signal ECLK receiving one or more command signals COM, the one or more address signals ADD and the data signals DATA11 to DATA1j. In the same way, a memory element 200-2 the external clock signal ECLK receiving one or more command signals COM, the one or more external address signals ADD and the data signals DATA21 to DATA2j, and a memory element 200-x may be the external clock signal ECLK comprising the one or more command signals COM, receiving the one or more address signals ADD and the data signals DATAx1 to DATAxj.
  • As shown, in the conventional memory system according to FIG 1A each storage element 200-1 . 200-2 - 200-x during a clock cycle of the external clock signal ECLK, receive or output data composed of 2 n serial bits. In addition, data of j bits can be written or read at the same time.
  • 1B shows an example of a conventional memory element, such as the memory element 200-1 in 1A , and an associated control logic. As shown, the associated control logic may include an address buffer (ADD BUF). 10 , a command decoder (COM DEC) 12 , one or more serial-to-parallel converters 14-1 to 14-j (j corresponds to the j in 1A ), one or more parallel-to-serial converters 16-1 to 16-j , the memory cell array and the memory cell array, respectively 18 , a row decoder 20 , a column decoder 22 , a phase locked loop (PLL) 24 and / or a control signal generation circuit (CSG Ckt.) 26 include.
  • The address buffer (ADD BUF) 10 may receive external input addresses (ADD) to generate row addresses (RA) which are applied to the row decoder in response to an active command signal (ACT) 20 to be delivered. This means that the address buffer (ADD BUF) 10 may include a plurality of address buffer circuits each receiving an external address signal to generate a row address signal (RA). Accordingly, the address buffer 10 in the case that the memory element 200-1 twelve external addresses (ADD) from the memory controller 100 receives twelve address buffer circuits for receiving twelve external addresses and generating twelve row addresses (RA).
  • The row decoder 20 may activate a main word line enable signal (MWE) corresponding to a plurality of row addresses generated by a plurality of row address buffers such that a desired wordline (not shown) in the memory cell array or memory cell array 18 can be selected. The address buffer (ADD BUF) 10 which may include a plurality of address buffer circuits for a plurality of external address signals may further generate a plurality of column addresses (CA) which are dependent on a read command (RE) or write command decrypted from the one or more command signals COM (WE) to the column decoder 22 to be delivered.
  • The column decoder 22 may receive a plurality of column addresses to activate a corresponding column select line (CSL). A plurality of bit lines of the memory cell array 18 may be selected depending on the selected CSL so that a plurality of data is written to or read from the selected memory cells can.
  • As stated above, the instruction decoder 12 upon receiving a plurality of external command signals (COM), such as RASB, CASB, WEB, and so on, generate an active command (ACT), a read command (RE), and a write command (WE).
  • Each serial-to-parallel converter ( 14-1 to 14-j ) can receive serial data DATA formed from 2 n bits of data and 2 n bits of parallel data over 2 n data bus lines simultaneously to the memory cell array 18 in response to a write command signal (WE) and a plurality of control signals (P1 ~ P ( 2n )). When the number of data input and output pins (DQ) is j, the number of serial-to-parallel converters is also j. In addition, each of the serial-parallel converters ( 14-1 to 14-j ) with the memory cell array 18 be coupled via 2 n data bus lines.
  • Each parallel-to-serial converter ( 16-1 to 16-j ) can take 2 n bits of data in parallel from a memory cell array 18 and output 2 n bits of serial data in response to a read command signal (RE) and the plurality of control signals (P 1 -P (2 n )). When the number of data input / output pins (DQ) is j, the number of parallel-to-serial converters is also j.
  • The phase locked loop 24 may receive the external clock signal ECLK and perform a latch operation to output an internal clock signal CLK1 latched with ECLK. After the conclusion of the locking operation, the phase locked loop 24 a plurality of internal clock signals (CLK1~CLKI) to the control signal generation circuit (CSG Ckt.) 26 output. The control signal generating circuit (GSG Ckt.) 26 may generate the plurality of control signals (P1~P ( 2n )).
  • A disadvantage of a conventional data access technique, as described above, is that that can be accessed only on 2 n bits of data during one clock cycle of an external clock signal, for example ECLK, for example 2 bits, 4 bits, 8 bits and so on.
  • 2A shows the operation of a conventional PLL and a conventional control signal generating circuit, for example, PLL 24 and Control Signal Generation Circuit (CSG Ckt.) 26 in 1B , As shown, an internal clock signal CLK1 may be locked to an external clock signal ECLK. The PLL may generate two (or more) internal clocks CLK1 / CLK2 which is twice the frequency of the external clock signal ECLK. A phase difference between CLK1 and CLK2 can be 180 °. The control signal generating circuit (CSG Ckt.) 26 may generate four control signals P1 ~ P4 using different combinations of the two internal clocks CLK1 ~ CLK2 and the external clock signal ECLK. Accordingly, four data D1-D4 may be written or read in response to each of the control signals P1 ~ P4 during one clock cycle of the external clock signal ECLK by serial-parallel converters or parallel-serial converters. Such a storage element may be characterized as being operated at a quad data rate (QDR).
  • 2 B Fig. 15 shows another mode of operation of a conventional PLL and a conventional control signal generating circuit, for example PLL 24 and Control Signal Generation Circuit (CSG Ckt.) 26 in 1B , As shown, the internal clock signal CLK1 may be locked to the external clock signal ECLK. The PLL may generate four internal clock signals CLK1 ~ CLK4 having the same frequency as the external clock signal ECLK. A phase difference between adjacent clocks may be 90 °. The control signal generating circuit (CSG Ckt.) 26 may generate four control signals P1~P4 using different combinations of the four internal clocks CLK1~CLK4 and the external clock ECLK to access four data D1-D4 in one memory element during one clock cycle of the external clock signal ECLK. Such a memory element may also be characterized as being operated at a fourfold data rate.
  • 3 shows still another mode of operation of a conventional PLL and a conventional control signal generating circuit, for example PLL 24 and Control Signal Generation Circuit (CSG Ckt.) 26 in 1B , As shown, the internal clock signal CLK1 may be locked to the external clock signal ECLK. The PLL can generate four internal clocks CLK1 ~ CLK4 which are twice the frequency of the external clock signal ECLK. A phase difference between adjacent clocks may be 90 °. The control signal generating circuit (CSG Ckt.) 26 may generate eight control signals P1~P8 using different combinations of the four internal clocks CLK1~CLK4 and the external clock ECLK to access eight data D1-D8 in one memory element during one clock cycle of the external clock signal ECLK. Such a memory element may also be characterized as being operated at an octal data rate (ODR).
  • A disadvantage of conventional data access techniques, as described above, is that only 2 n bits of data, for example 2 bits, 4 bits, 8 bits and so on, while ei nes clock cycle of the external clock signal can be accessed.
  • Out For this reason, a conventional semiconductor element additional Pins or connections to Receiving and / or outputting data bits for error correction coding (Error Correction Coding - ECC), for Cyclic Redundancy Coding (CRC) or for have a data masking (DM). This can a larger chip area and thus increased Condition manufacturing costs.
  • Of the Invention is based on the object, methods and devices specify the type mentioned above, the access to quasi allow any number of data and that about it beyond usual Techniques reduced by a smaller chip area and accordingly Distinguish manufacturing costs.
  • The Task is achieved by a serial-to-parallel converter according to claim 1, by a Process according to claim 8, by a parallel-to-serial converter according to claim 9, by a Process according to claim 15, by a control signal generating circuit according to claim 16, by a memory element according to claim 21, by a Process according to claim 43 and solved by a storage system according to claim 44.
  • advantageous Further developments of the present invention are the subject of subclaims, whose Wording hereby incorporated by reference Description is brought to unnecessary text repetition too avoid.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for the data input and data output, which allow a higher data count per Clock cycle input and / or output.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for the data entry and data output, what additional data on the same Bus can enter and / or spend.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for the data input and data output, the additional data being from a memory controller to a memory and / or transferred from the memory to the memory controller can be.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for data entry and data output, with the additional ones Data is error correction data, such as CRC or Parity-check data.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for data entry and data output, with the additional ones Data is about masking data.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for data entry and data output, with the additional ones Data for information regarding a memory controller or a memory state, such as temperature information.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for data entry and data output, with the additional ones Data is dummy data.
  • Exemplary embodiments of the present invention are directed to control and control method for the data input and data output, wherein (a plurality of write or read data, which are formed from m (2 n + k) bits where m, n and k are each integers ), can be accessed within one clock of the external input clock.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for the data input and data output, which has less chip area and / or require lower production costs.
  • An exemplary embodiment of the present invention provides a serial-to-parallel converter for converting a serial bit stream of m bits (where m is an integer ≥ 3) in a parallel m-bit stream, the m bits being 2 n data bits (where n an integer ≥ 1) and k data bits (where k is an integer ≥ 1), comprising: a first register array of (m-1) registers, each for sequentially receiving bits 1 to (m-1) of the serial bit stream is formed of m bits and (m-1) control signals, each of the (m-1) registers of the first register arrangement bits 1 to (m-1) of the serial bit stream of m bits as (m -1) stores and outputs outputs of the first register arrangement, each of the (m-1) outputs of the ers th register arrangement is output during a clock cycle of an external clock signal which is applied to the serial-parallel converter; and a second register arrangement of m registers, each for sequentially receiving the (m-1) outputs of the first register arrangement and the m-th control signal, each of the m registers of the second register arrangement storing bits 1 to m and outputting m as outputs second register arrangement outputs at the same time, wherein all m outputs of the second register teranordnung during a clock cycle of the external clock signal are output.
  • Another exemplary embodiment of the present invention provides a method for converting a serial bit stream of m bits (where m is an integer ≥ 3) in a parallel the m-bit current, the m bits 2 n bits (where n is an integer ≥ 1) and k data bits (where k is an integer ≥ 1), comprising: sequentially receiving bits 1 to (m-1) of the serial bit stream of m bits and (m-1) control signals; Storing and outputting bits 1 to (m-1) of the serial bit stream of m bits as (m-1) first outputs, each of the (m-1) first outputs being output during one clock cycle of an external clock signal; sequentially receiving the (m-1) first outputs and the m-th control signal; and storing and simultaneously outputting bits 1 to m as m second outputs, all of the m second outputs being output during one clock cycle of the external clock signal.
  • Another exemplary embodiment of the present invention provides a parallel-serial converter for converting a parallel bit stream of m bits (where m is an integer ≥ 3) in a serial bit stream of m bits, the m bits 2 (n bits where n an integer ≥ 1) and k data bits (where k is an integer ≥ 1) comprising: a logic gate array of m logic gates, each for simultaneously receiving bits 1 to m of the parallel bit stream of m bits and m control signals, each of the m logic gates sequentially outputting bits 1 to m of the m bit serial bit stream in response to each of the m control signals as m outputs of the logic gate array, outputting every m outputs of the logic gate array during one clock cycle of an external clock signal which is applied to the parallel-to-serial converter; and a logic gate for sequentially receiving the m outputs of the logic gate array and outputting bits 1 to m as a serial bit stream of m bits, bits 1 to m being output during one clock cycle of the external clock signal.
  • Another exemplary embodiment of the present invention provides a method of converting a parallel bit stream of m bits (where m is an integer ≥ 3) into a serial bit stream of m bits, the m bits being 2 n data bits (where n is an integer ≥ 1) and k data bits (where k is an integer ≥ 1) comprising: receiving bits 1 to m of the parallel bit stream of m bits and m control signals simultaneously; sequentially output bits 1 to m of the serial bit stream of m bits in response to each of the m control signals as m first outputs, each of the m first outputs being output during one clock cycle of an external clock signal; and sequentially receiving the m first outputs and outputting bits 1 to m as a serial bit stream of m bits, each of bits 1 to m being output during a clock cycle of an external clock signal.
  • Another exemplary embodiment of the present invention provides a method of generating a control signal, including receiving at least two internal clock signals and generating p control signals (where p is an integer ≥ 3), where p = 2 n + k, where 2 n is a number of data bits (where n is an integer ≥ 1) and where k is a number of data bits (where k is an integer ≥ 1), each of the p control signals being generated sequentially during a clock cycle of an external clock signal.
  • Another exemplary embodiment of the present invention provides a method of writing data to a memory and reading data from a memory including a plurality of memory elements and a memory controller, comprising the steps of: providing an external clock signal to each of the plurality of memory elements Plurality of memory elements, generating at least two internal clock signals from the external clock signal, generating p control signals (where p is an integer ≥ 3), where p = 2 n + k, where 2 n is a number of data bits (where n is a integer ≥ 1) and where k is a number of data bits (where k is an integer ≥ 1), all of the p control signals being generated sequentially during a clock cycle of the external clock signal, sequentially receiving a serial bit stream of m bits (where m is an integer ≥ 3) from the memory controller and converting the serial bit stream of m bits into a parallel bit stream at least one parallel in response to each of the p control signals, wherein all bits of the parallel bit stream are output during one clock cycle of the external clock signal, providing a write command signal and an address signal for writing at least the 2 n data bits to at least one of the plurality of storage elements, receiving 2 n -bit stream which has been read from one of the plurality of storage elements, and Umwan denoting the parallel 2 n- bit stream into a serial bit stream in response to each of the 2 n control signals, all bits of the serial bit stream being output during a clock cycle of the external clock signal, and providing a read command signal and an address signal for reading at least 2 n Data bits from the at least one of the plurality of memory elements.
  • exemplary Embodiments of the present invention are directed to controls and control procedures for the data entry and data output, where there is a one-to-one correspondence between the number of generated internal clock signals, a number used inversion circuits and a number of generated control signals. At the others exemplary embodiments, there is no one-to-one correspondence between the number of generated internal clock signals, a number of used Inverting circuits or a number of generated control signals. In some example embodiments, the number of generated Control signals greater than the Number of generated internal clock signals.
  • Further Advantages and characteristics of the present invention will be apparent from the following description of exemplary embodiments with reference to FIG Drawing. It shows:
  • 1A an example of a conventional memory system;
  • 1B an example of a conventional memory element;
  • 2A the operation of a conventional PLL and a conventional control signal generating circuit;
  • 2 B another operation of a conventional PLL and a conventional control signal generating circuit;
  • 3 another operation of a conventional PLL and a conventional control signal generating circuit;
  • 4 a memory system according to an exemplary embodiment of the present invention;
  • 5 a memory element according to an exemplary embodiment of the present invention;
  • 6 a serial-parallel converter according to an exemplary embodiment of the present invention;
  • 7 a parallel-to-serial converter according to an exemplary embodiment of the present invention;
  • 8th a control signal generation circuit according to an exemplary embodiment of the present invention;
  • 9A a write operation of a memory element using a control signal generation circuit according to an exemplary embodiment of the present invention;
  • 9B a read operation of a memory element using a control signal generation circuit according to an exemplary embodiment of the present invention;
  • 10 a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 11A a write operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 11B a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 12 a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 13A a write operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 13B a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 14 a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 15A a write operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 15B a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention;
  • 16 a memory element according to another exemplary embodiment of the present invention;
  • 17 an error detector according to an exemplary embodiment of the present invention;
  • 18 an error detection code generation circuit according to an exemplary embodiment of the present invention;
  • 19 a memory element according to another exemplary embodiment of the present invention;
  • 20 a data masking circuit according to another exemplary embodiment of the present invention; and
  • 21 a memory element according to another exemplary embodiment of the present invention.
  • It It should be noted that an element, which as with a another element "connected" or "coupled" is described, can be connected or coupled directly to the other element or the intermediate elements may be present. In contrast to this are then, if an item as "direct connected "or" directly coupled "with a other element is indicated, no intermediate elements present. Other used to describe relationships between elements words should be interpreted accordingly, for example "between" versus "directly between," "adjacent" versus "directly neighboring "and so on.
  • 4 shows a storage system according to an exemplary embodiment of the present invention. As illustrated, a memory system according to an exemplary embodiment of the present invention may include a memory controller 100 ' and a memory module 200 ' contain, wherein in the latter a plurality of memory elements 200-1 ' . 200-2 ' . 200-x ' are arranged on a module board. As shown, the memory controller swap 100 ' and the memory module 200 ' one or more data signals DATA off. In the in 4 As illustrated, the one or more data signals DATA may be formed of a serial stream of m bits represented as [1: m] DATA11 to [1: m] DATAxj, where m is described in more detail below.
  • As shown, each memory element 200-1 ' . 200-2 ' . 200-x ' during a clock cycle of an external clock signal ECLK, receive or output data DATA formed of a serial stream of m bits, where m = (2 n + k) bits instead of 2 n bits. According to an exemplary embodiment, all of the 2 n + k data bits may be valid data that may be written to a memory cell array or read from a memory cell array.
  • 5 shows a memory element including associated control logic according to an exemplary embodiment of the present invention. As shown, the associated control logic may include one or more serial-to-parallel converters 14-1 ' to 14-j ' , one or more parallel-to-serial converters 16-1 ' to 16-j ' , a memory cell array 18 ' , a clock generator (CLK Gen.) 24 ' and / or a control signal generation circuit (CSG Ckt.) 26 ' exhibit. The associated control logic can still use the conventional address buffer (ADD BUF) 10 , Command Decoder (COM DEC) 12 , Row decoder 20 and / or column decoder 22 according to 1B exhibit.
  • Each serial-to-parallel converter ( 14-1 ' to 14-j ' ) can receive serial data DATA composed of m bits of data and m bits of parallel data through m data bus lines simultaneously to the memory cell array 18 ' in response to a write command signal (WE) and a plurality of control signals (P1 ~ P (m)). In addition, each of the serial-parallel converters ( 14-1 ' to 14-j ' ) over m data bus lines to the memory cell array 18 ' be coupled.
  • Each parallel-to-serial converter ( 16-1 ' to 16-j ' ) can m bits of data from the memory cell array 18 ' receive in parallel and output m bits of serial data in response to a read command signal (RE) and the plurality of control signals (P1~P (m)).
  • The clock generator (CLK Gen.) 24 ' may receive the external clock signal ECLK and perform a latch operation to output an internal clock signal CLK1 locked to the external clock signal ECLK. After completing the lock operation, the clock generator (CLK Gen.) 24 ' a plurality of internal clock signals (CLK1~CLKI) to the control signal generation circuit (CSG-Ckt.) 26 ' output. The control signal generating circuit (CSG Ckt.) 26 ' may generate the plurality of control signals (P1~P (m)).
  • As in 5 the control signal generating circuit (CSG Ckt.) generates 26 ' a plurality of control signals (P1 ~ P (m)). In an exemplary embodiment, m = 2 n + k. As a result, according to an exemplary embodiment of the present invention, one or more serial-parallel converters ( 14-1 ' to 14-j ' ) and / or one or more parallel-to-serial converters ( 16-1 ' to 16-j ' Moreover, m bits of data during a clock of the external clock signal ECLK in response to one or more control signals (P1 ~ P (m)) into a parallel or serial stream.
  • 6 shows a serial-to-parallel converter, for example a serial-parallel converter ( 14-j ' ) according to an exemplary embodiment of the present invention. The serial-parallel converter ( 14-j ' ) may be a first flip-flop part 162 comprising m-1 flip-flops (for example, D flip-flops DF11 ~ DF1 (m-1)) and a second flip-flop part 164 having m flip-flops (for example, D flip-flops DF21 ~ DF2m). Each of the m-1 flip-flops (DF11 ~ DF1 (m-1)) can store corresponding input data from a serial data stream DATA in response to a rising edge of one or more control signals (P1 ~ P (m-1)) and can be one Plurality of data output DI1, DI2 ~ DIm-1.
  • Each of m flip-flops (DF21~DF2m) can input m-1 output data of the first flip-flop part 162 and at the same time storing a last input data in response to the rising edge of the control signal Pm and all data (di1 ~ dim) to a memory cell array (eg memory cell array 18 ' ) in a parallel manner.
  • 7 shows a parallel-to-serial converter, for example a parallel-to-serial converter ( 16-j ' ) according to an exemplary embodiment of the present invention. The parallel-to-serial converter ( 16-j ' ), a plurality of AND circuits AND1 ~ ANDm and an OR circuit 40 include. M data bits (do1~dom) may be sequentially output through the plurality of AND circuits AND1~ANDm in response to the rising edge of one or more control signals (P1~P (m)). The OR circuit 40 can be used to output data DATA consecutively without gap.
  • 8th shows a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. The control signal generating circuit (CSG Ckt.) 26 ' I can be internal clock signals, where I is an integer; in 8th I = 5), a plurality of inverse circuits I1 ~ Ix (where x is an integer; 8th x = 5) and a plurality of AND circuits AND11 ~ ANDm (where m is an integer; 8th is m = 5). 9A and 9B show in exemplary writing and reading timing diagrams for a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. An Exemplary Operation of the Control Signal Generating Circuit (CSG Ckt.) 26 ' is below in connection with the 8th . 9A and 9B described.
  • 9A shows a write operation or a write method of a memory element using a control signal generation circuit according to an exemplary embodiment of the present invention. In the example of 9A m = I = 5 for one write cycle. 9B FIG. 12 shows a read operation or a read operation of a memory element using a control signal generation circuit according to an exemplary embodiment of the present invention. FIG. In the example of 9B m = I = 5 for a read cycle.
  • As shown, in 9A and 9B the control signal P1 is activated when CLK1, CLK2B (the inverse signal to CLK2), CLK3B (the inverse signal to CLK3) and CLK5 are at a high level. Control signal P2 is activated when CLK1, CLK2, CLK3B and CLK4B are at a high level. Control signal P3 is activated when CLK2, CLK3, CLK4B and CLK5B are at a high level. Control signal P4 is activated when CLK1B, CLK3, CLK4 and CLK5B are at a high level. Control signal P5 is activated when CLK1B, CLK2B, CLK4 and CLK5 are at a high level.
  • As in 9A shown, a clock generator, such as clock generator (CLK Gen.) 24 ' in 5B , generate five (I = 5) internal clock signals CLK1 ~ CLK5 having the same frequency as the external clock signal ECLK. The five internal clocks CLK1 ~ CLK5 can be activated sequentially within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 ~ CLK5 may be 72 °. The data writing operation from D11 ~ D14 to di1 ~ di5 was described above using 6 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , can generate five (m = 5) control signals P1 ~ P5 to write five data D1-D5 to a memory element during one clock cycle of the external clock signal ECLK. According to an exemplary embodiment, m = I = 2 n + k, where n = 2 and k = 1.
  • As in 9B shown, a clock generator, such as clock generator (CLK = Gen.) 24 ' in 5 , generate five (I = 5) internal clocks CLK1 CLK5 having the same frequency as the external clock signal ECLK. The five internal clocks CLK1 ~ CLK5 can be sequentially activated within one clock of the external clock signal ECLK. A phase difference between adjacent internal Clock CLK1 CLK5 can be 72 °. The data transfer process from do1 to do5 has already been described with reference to FIG 7 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , five (m = 5) can generate control signals P1 P5 to read five data D1 to D5 from a memory element during one clock cycle of the external clock signal ECLK. According to an exemplary embodiment, m = I = 2 n + k, where n = 2 and k = 1.
  • 10 shows a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. The control signal generating circuit (CDS Ckt.) 26 ' I can use internal clock signals (where I is an integer; 10 I = 6), a plurality of inversion circuits I1 ~ Ix (where x is an integer; 10 x = 6) and a plurality of AND circuits AND11 ~ AND1m (where m is an integer; 10 is m = 6). 11A and 11B show exemplary writing and reading timing charts for a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. An Exemplary Operation of the Control Signal Generating Circuit (CSG Ckt.) 26 ' is below in connection with the 10 . 11A and 11B described.
  • 11A shows a write operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention. In the example according to 11A m = I = 6 for one write cycle. 11B shows a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention. In the example according to 11B m = I = 6 for a read cycle.
  • As shown, according to 11A and 11B the control signal P1 is activated when CLK1, CLK2B (the inverse signal to CLK2), CLK3B (the inverse signal to CLK3), CLK4B (the inverse signal to CLK4), CLK5 and CLK6 have a high level. Control signal P2 is activated when CLK1, CLK2, CLK3B, CLK4B, CLK5B and CLK6 are high. Control signal P3 is activated when CLK1, CLK2, CLK3, CLK4B, CLK5B and CLK6B are high. Control signal P4 is activated when CLK1B, CLK2, CLK3, CLK4, CLK5B and CLK6B are high. Control signal P5 is activated when CLK1B, CLK2B, CLK3, CLK4, CLK5 and CLK6B are high. Control signal P6 is activated when CLK1B, CLK2B, CLK3B, CLK4, CLK5, and CLK6 are high.
  • As in 11A shown, a clock generator, such as clock generator (CLK Gen.) 24 ' according to 5 generate six (I = 6) internal clocks CLK1 ~ CLK6 having the same frequency as the external clock signal ECLK. The six internal clock signals CLK1 ~ CLK6 may be activated sequentially within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 ~ CLK6 may be 60 °. The data writing operation from DI1 ~ DI5 to di1 ~ di6 has already been described above in connection with 6 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , six (m = 6) can generate control signals P1 ~ P6 to write six data D1-D6 to a memory element during one clock cycle of the external clock signal ECLK. According to an exemplary embodiment, m = I = 2 n + k, where n = 2 and k = 2.
  • As in 11B shown, a clock generator, such as clock generator (CLK Gen.) 24 ' according to 5 generate six (I = 6) internal clocks CLK1 ~ CLK6 having the same frequency as the external clock signal ECLK. The six internal clock signals CLK1 CLK6 can be activated sequentially within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 ~ CLK6 may be 60 °. The data writing process from do1 to do6 has already been discussed above 7 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , six (m = 6) can generate control signals P1 ~ P6 to read six data D1 to D6 during one clock cycle of the external clock signal ECLK from a memory element. According to an exemplary embodiment, m = I = 2 n + k, where n = 2 and k = 2.
  • 12 shows a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. The control signal generating circuit (CDS Ckt.) 26 ' I can use internal clock signals (where I is an integer; 12 I = 9), a plurality of inverse circuits I1 ~ Ix (where x is an integer; 12 x = 9) and a plurality of AND circuits AND11 ~ AND1m, where m is an integer; and 12 is m = 9). 13A and 13B show exemplary writing and read timing charts for a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. An Exemplary Operation of the Control Signal Generating Circuit (CSG Ckt.) 26 ' is below in connection with the 12 . 13A and 13B described.
  • 13A shows a write operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention. In the example according to 13A m = I = 9 for a write cycle.
  • 13B shows a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention. In the example according to 13B m = I = 9 for a read cycle.
  • As shown, according to 13A and 13B the control signal P1 activates when CLK1, CLK2B (the inverse signal to CLK2), CLK3B (the inverse signal to CLK3), CLK4B (the inverse signal to CLK4), CLK5B (the inverse signal to CLK5), CLK6B (the inverse signal to CLK6), CLK7, CLK8 and CLK9 have a high level. Control signal P2 is activated when CLK1, CLK2, CLK3B, CLK4B, CLK5B, CLK6B, CLK7B, CLK8 and CLK9 have a high level. Control signal P3 is activated when CLK1, CLK2, CLK3, CLK4B, CLK5B, CLK6B, CLK7B, CLK8B and CLK9 have a high level. Control signal P4 is activated when CLK1, CLK2, CLK3, CLK4, CLK5B, CLK6B, CLK7B, CLK8B and CLK9B have a high level. Control signal P5 is activated when CLK1B, CLK2, CLK3, CLK4, CLK5, CLK6B, CLK7B, CLK8B and CLK9B have a high level. Control signal P6 is activated when CLK1B, CLK2B, CLK3, CLK4, CLK5, CLK6, CLK7B, CLK8B and CIK9B have a high level. Control signal P7 is activated when CLK1B, CLK2B, CLK3B, CLK4, CLK5, CLK6, CLK7, CLK8B and CLK9B have a high level. Control signal P8 is activated when CLK1B, CLK2B, CLK3B, CLK4B, CLK5, CLK6, CLK7, CLK8 and CLK9B have a high level. Control signal P9 is activated when CLK1B, CLK2B, CLK3B, CLK4B, CLK5B, CLK6, CLK7, CLK8 and CLK9 have a high level.
  • As in 13A shown, a clock generator, such as clock generator (CLK Gen.) 24 ' in 5 , generate nine (I = 9) internal clock signals CLK1 CLK9 having the same frequency as the external clock signal ECLK. The nine internal clock signals CLK1 ~ CLK9 can be activated sequentially within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 ~ CLK9 may be 40 °. The data writing operation from DI1 DI8 to di1 ~ di9 has already been described above with reference to FIG 6 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , nine (m = 9) can generate control signals P1 ~ P9 to write nine data D1-D9 into a memory element during one clock cycle of the external clock signal. According to an exemplary embodiment is m = I = 2 n k, where n = 3 and k =. 1
  • As in 13B shown, a clock generator, such as clock generator (CLK Gen.) 24 ' according to 5 generate six (I = 9) internal clocks CLK1 ~ CLK9 having the same frequency as the external clock signal ECLK. The nine internal clock signals CLK1 CLK9 can be activated sequentially within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1~CLK9 may be 40 °. The data write from do1 to do9 has already been discussed above 7 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , nine (m = 9) can generate control signals P1 ~ P9 to read six data D1-D9 from a memory element during one clock cycle of the external clock signal ECLK. According to an exemplary embodiment, m = I = 2 n + k, where n = 3 and k = 1.
  • 14 shows a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. The control signal generating circuit (CDS Ckt.) 26 ' I can use internal clock signals (where I is an integer; 14 I = 5), a plurality of inverse circuits I1 ~ Ix (where x is an integer; 14 x = 6) and a plurality of AND circuits AND11 ~ AND1m, where m is an integer; in 14 is m = 10). 15A and 15B show exemplary writing and reading timing charts for a control signal generating circuit, for example, a control signal generating circuit (CSG Ckt.) 26 ' according to an exemplary embodiment of the present invention. An Exemplary Operation of the Control Signal Generating Circuit (CSG Ckt.) 26 ' is below in connection with the 14 . 15A and 15B described.
  • 15A shows a write operation of a memory element including a control signal generation circuit according to another example th embodiment of the present invention. In the example according to 15A m = 2I = 10 for one write cycle. 15B shows a read operation of a memory element using a control signal generation circuit according to another exemplary embodiment of the present invention. In the example according to 15B m = 2I = 10 for a read cycle.
  • As in 15A and 15B 1, control signals P1 and P6 are activated when CLK1, CLK2B (the inverse signal to CLK2), CLK3B (the inverse signal to CLK3), CLK4B (the inverse signal to CLK4) and CLK5 are high level. Control signals P2 and P7 are activated when CLK1, CLK2, CLK3B, CLK4B and CLK5B are high. Control signals P3 and P8 are activated when CLK1B, CLK2, CLK3, CLK4B and CLK5B are high. Control signals P4 and P9 are activated when CLK1B, CLK2B, CLK3, CLK4 and CLK5B are high. Control signals P5 and P10 are activated when CLK1B, CLK2B, CLK3B, CLK4 and CLK5 are high.
  • As in 15A shown, a clock generator, such as clock generator (CLK Gen.) 24 ' in 5 , generate five (I = 5) internal clock signals CLK1 ~ CLK5 which are twice the frequency as the external clock signal ECLK. The five internal clock signals CLK1 ~ CLK5 may be sequentially activated more than once (for example twice) within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 ~ CLK5 may be 72 °. The data writing operation from DI ~ DI10 to di1 ~ di9 has already been described above with reference to FIG 6 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , can generate ten (m = 2I) control signals P1 ~ P10 to write ten data D1-D10 to a memory element during one clock cycle of the external clock signal ECLK. In an exemplary embodiment m = 2I 2 = n + k, wherein n = 3 and k =. 2
  • As in 15B shown, a clock generator, such as clock generator (CLK = Gen.) 24 ' in 5 , generate five (I = 5) internal clocks CLK1 CLK5 having the same frequency as the external clock signal ECLK. The five internal clocks CLK1 ~ CLK5 can be sequentially activated within one clock of the external clock signal ECLK. A phase difference between adjacent internal clocks CLK1 CLK5 may be 72 °. The data transfer process from do1 to do10 has already been described with reference to FIG 7 described.
  • A control signal generating circuit, for example, control signal generating circuit (CSG Ckt.) 26 ' , can generate ten (m = 2I) control signals P1 ~ P10 to read ten data D1 to D10 from a memory element. In an exemplary embodiment m = 2I 2 = n + k, wherein n = 3 and k =. 2
  • 16 shows a memory element according to another exemplary embodiment of the present invention, which includes an associated control logic. As described above with reference to 5 As shown and discussed, the associated control logic may include one or more serial-to-parallel converters 14-1 ' to 14-j ' , one or more parallel-to-serial converters 16-1 ' to 16-j ' , a memory cell array 18 , a clock generator (CLK Gen.) 24 ' and / or a control signal generating circuit (CSG Ckt.) 26 ' include. The associated control logic may further include the conventional address buffer (ADD BUF). 10 , the command decoder (COM DEC) 12 , a memory cell array 18 ' , the row decoder 20 and / or the column decoder 22 according to 1B exhibit.
  • Each serial-to-parallel converter ( 14-1 ' to 14-j ' ) may receive serial data DATA composed of m bits of data and output m bits of parallel data over m data bus lines in response to a write command signal (WE) and a plurality of control signals (P1~P (m)). In addition, each of the serial-parallel converters ( 14-1 ' ~ 14-j ' ) over 2 n data bus lines to the memory cell array 18 be coupled.
  • Each parallel-to-serial converter ( 16-1 ' to 16-j ' ) can take 2 n bits of data in parallel from the memory cell array 18 receive and output m bits of serial data in response to a read command signal (RE) and the plurality of control signals (P1~P (m)).
  • The clock generator (CLK Gen.) 24 ' may receive the external clock signal ECLK and perform a latch operation to output an internal clock signal CLK1 locked to the external clock signal ECLK. After completing the lock operation, the clock generator (CLK Gen.) 24 ' a plurality of internal clock signals (CLK1~CLKI) to the control signal generation circuit (CSG Ckt.) 26 ' output. The control signal generating circuit (CSG Ckt.) 26 ' may generate the plurality of control signals (P1~P (m)).
  • As in 16 shown, the control signal generating circuit (CSG Ckt.) generates 26 ' a plurality of control signals (P1 ~ P (m)). According to an exemplary embodiment, m = 2 n + k. As a result, according to an exemplary embodiment of the present invention, this means that one or more serial-parallel converters ( 14-1 ' to 14-j ' ) and / or one or more parallel-to-serial converters ( 16-1 ' to 16-j ' Moreover, m bits of data can be converted to parallel or serial current during one clock of the external clock signal ECLK in response to one or more control signals (P1~P (m)). According to an exemplary embodiment, the 2 n data bits are valid data bits that can be written to a memory cell array and read from a memory cell array, and the k data bits are test data, as described below.
  • As in 16 In addition, a memory element having associated control logic according to another exemplary embodiment of the present invention may further comprise an error detection circuit 35 and / or one or more generating circuits ( 34-1 to 34-j ) for error detection code. The error detection circuit 35 may further include one or more error detectors ( 30-1 to 30-j ) and / or a generating circuit 32 for an error detection signal.
  • As in 16 shown, each of the error detectors ( 30-1 to 30-j ) the m bits of data from the one or more serial-to-parallel converters ( 14-1 ' to 14-j ' ) through the m data bus lines. Each of the fault detectors ( 30-1 to 30-j ) generates an error detection signal ed1 to edj, and the generation circuit 32 for the error detection signal, the error detection signals ed1 to edj of the error detectors ( 30-1 to 30-j ) and generates a composite error detection signal ED.
  • As continues in 16 1, the one or each of the plurality of generating circuits ( 34-1 to 34-j ) for error detection code, the 2 n bits of data from the memory cell array 18 over 2 n data bus lines. Each of the generating circuits ( 34-1 to 34-j ) for error detection code generates k bits, such as error detection bits, to each of the parallel-to-serial converters ( 16-1 ' to 16-j ' ) where the k error detection bits from the one or more generation circuits ( 34-1 to 34-j ) for error detection code with the 2 n bits of data from the memory cell array 18 combined and output as a serial data stream DATA1 ~ DATAj.
  • As described above, the one or each of the error detectors ( 30-1 to 30-j ) M bits ((with m = 2 n + k) to parallel data from the one or each of the plurality of serial-to-parallel converters 14-1 ' to 14-j ' ), can detect whether or not there is an error, and can generate an error signal (ed1~edj). The generating circuit 32 for the error detection signal, all the error detection signals (ed1~edj) can be received, can determine whether an error is present or not, and can output a composite error detection signal ED to a memory control unit, for example, the memory control unit 100 according to 1A ,
  • 17 shows an error detector, for example one of the error detectors ( 30-1 to 30-j ) according to an exemplary embodiment of the present invention. An error detector ( 30-j ) may implement a parity check method or a CRC method. In the case of implementing a CRC method, an error detector ( 30-j ) a divider 50 and an error decision circuit 52 include. As shown, the divider can 50 subdivide the m bits of parallel data into k + 1 bits of data and output k bits. If the k bits are all zeros, the error decision circuit may 52 determine that there is no error. If the k bits are not all zeros, the error decision circuit may 52 determine that there is an error.
  • 18 shows an error detection code generation circuit, for example one or more generation circuits for error detection code ( 34-1 to 34-j ) according to an exemplary embodiment of the present invention. A generation circuit for error detection code ( 34-j ) may generate a k-bit code corresponding to 2 n bits of parallel data provided by the memory cell array 18 to each of the parallel-to-serial converters ( 16-1 ' to 16-j ' ). Each of the parallel-to-serial converters ( 16-1 ' to 16-j ' ) may be the 2 n bits of parallel data from the memory cell array 18 and the k data bits from the one or more generation circuits ( 34-1 to 34-j ) for error detection code in m bits (with m = 2 n + k) on serial data in response to the one or more control signals (P1 ~ P (m)).
  • A generating circuit ( 34-j ) for error detection code can be a shift register 60 and a divider 62 exhibit. The shift register 60 2, the shift n bits of data to k bits (for example, to the left) so that the LSB (least significant bit) assumes the value zero of k bits to form 2 n + k bits for the divider 62 to create. The divider 62 can subdivide the m data bits into k + 1 data bits and output a remainder of k bits. If all k bits of the remainder are zero, there is no error. If not all k bits of the remainder are zero, there is an error.
  • 19 shows a memory element with associated control logic according to another exemplary embodiment of the present invention. As shown above and with reference to 5 1, the associated control logic may include one or more serial-to-parallel converters 14-1 ' to 14-j ' , one or more parallel-to-serial converters 16-1 ' to 16-j ' , a memory cell array 18 , a clock generator (CLK Gen.) 24 ' and / or a control signal generation circuit (CSG Ckt.) 26 ' exhibit. The associated control logic can also use the address buffer (ADD BUF). 10 , the command decoder (COM DEC) 12 , a memory cell array 18 ' , the row decoder 20 and / or the column decoder 22 according to 1B exhibit.
  • Each serial-to-parallel converter ( 14-1 ' to 14-j ' ) can receive serial data DATA composed of m data bits, and can output m bits of parallel data through m data bus lines in response to a write command signal (WE) and a plurality of control signals (P1 ~ P (m)). In addition, each of the serial-parallel converters ( 14 to 1 ' to 14-j ' ) with the memory cell array 18 be coupled via m data bus lines.
  • Each parallel-to-serial converter ( 16-1 ' to 16-j ' ) can take 2 n bits of data in parallel from the memory cell array 18 receive and output m bits of serial data in response to a read command signal (RE) and the plurality of control signals (P1~P (m)).
  • The clock generator (CLK Gen.) 24 ' may receive the external clock signal and perform a latching operation to output an internal clock signal CLK1 locked to the external clock signal ECLK. After completing the lock operation, the clock generator (CLK Gen.) 24 ' a plurality of internal clock signals (CLK1~CLKI) to the control signal generation circuit (CSG Ckt.) 26 ' output. The control signal generating circuit (CSG Ckt.) 26 ' may generate the plurality of control signals (P1~P (m)).
  • As in 19 shown, the control signal generating circuit (CSG Ckt.) generates 26 ' a plurality of control signals (P1 ~ P (m)). According to an exemplary embodiment, m = 2 n + k. As a result, this means that according to an exemplary embodiment of the present invention, one or more serial-parallel converters ( 14-1 ' to 14-j ' ) and / or one or more parallel-to-serial converters ( 16-j ' ) can further convert m bits of data into a parallel or serial stream during a clock of the external clock signal ECLK in response to one or more control signals (P1~P (m)).
  • As in 19 1, a memory element with associated control logic according to another exemplary embodiment of the present invention may further comprise one or more temperature detector generators ( 38-1 ' to 38-j ' ) and / or one or more data masking circuits ( 40-1 ' to 40-j ' ) exhibit. Each data masking circuit ( 40-1 ' to 40-j ' ) may further include one or more error switches (SW1 ~ SW ( 2n )). According to an exemplary embodiment is at the 2 n bits of data to valid data, which can be written in a memory cell array and read from a memory cell array, and the k data bits are mask data. According to another exemplary embodiment, the 2 n data bits are valid data that can be written to a memory cell array and read from a memory cell array, and the k data bits are data indicating the state of the memory cell array, for example in the form of temperature data. as described below.
  • As in 19 1, the one or each of the plurality of data masking circuits (FIG. 40-1 ' to 40-j ' ) the m bits of data from the one or more serial-to-parallel converters ( 14-1 ' to 14-j ' ) through the m data bus lines.
  • The one or each of the plurality of data masking circuits ( 40-1 ' to 40-j ' ) may include a range of the m-bit data from the one or more serial-to-parallel converters ( 14-1 ' to 14-j ' ) through the m data bus lines. For example, depending on k bits, odd data (di1, di3, ...) can be prevented from being introduced into the memory cell array 18 (for example, for 2 bits, k1 = 1 and k2 = 0), while depending on k bits, even data (di2, di4, ...) is prevented from being written into the memory cell array 18 (for example, for 2 bits, k1 = 0 and k2 = 1).
  • Further, when the k bits are "11", all of the m input data can be input to the memory cell array 18 (essentially no masking operation is performed). As a result, a memory element, such as any of the memory elements described above, does not require data masking pins or terminals. 20 shows a data masking circuit ( 40-j ' ), where k = 2 bits.
  • It It should be noted that the number of k bits can vary and that in principle a higher number of bits causes a better data masking resolution. If, for example the k data bits include 3 or 4 bits is the masking masking of input data better than for 2 bits.
  • Like also in 19 shown, the generated one or each of the plurality of temperature detector generators ( 38-1 ' to 38-j ' ), for example, k bits of temperature information associated with the one or each of the plurality of parallel-to-serial converters ( 16-1 ' to 16-j ' ), where the k bits of temperature information from the one or more temperature detector generators ( 38-1 ' to 38-j ' ) with the 2 n bits of data from the memory cell array 18 combined and output as a serial data stream DATA1 ~ DATAj.
  • The one or each of the plurality of temperature detector generators ( 38-1 ' to 38-j ' ), k data bits corresponding to a temperature measured by a temperature sensor (not shown) at the one or each of the plurality of parallel-to-serial converters ( 16-1 ' to 16-j ' ) output. The one or each of the plurality of temperature detector generators ( 38-1 ' to 38-j ' ) may include an analog-to-digital converter configured to convert an analog signal output by a temperature sensor into a digital signal.
  • As described above, the one or each of the data masking circuits ( 40-1 ' to 40-j ' ) none, some or all of the 2 n parallel data for the memory cell array 18 mask. Likewise, the one or each of the plurality of temperature detector generators ( 38-1 ' to 38-j ' Generate) k bits at temperature information with the 2 n bits of data from the memory cell array 18 combined and output as a serial data stream DATA1 ~ DATAj. It should be appreciated that temperature detector generators and temperature information are only an example, and that any type of data from any type of device may be combined and output with the 2n bits of data from a memory cell array and forwarded to a memory controller, such as the FIG memory controller 100 according to 1A ,
  • 21 shows a memory element with associated control logic according to another exemplary embodiment of the present invention. As already with reference to 1 As shown and discussed, the associated control logic may include one or more serial-to-parallel converters 14-1 ' to 14-j ' , one or more parallel-to-serial converters 16-1 ' to 16-j ' , a memory cell array 18 , a clock generator (CLK Gen.) 24 ' and / or a control signal generation circuit (CSG Ckt.) 26 ' exhibit. The associated control logic may further include the conventional address buffer (ADD BUF). 10 , the command decoder (COM DEC) 12 , a memory cell array 18 , the row decoder 20 and / or the column decoder 22 according to 1B exhibit.
  • Each serial-to-parallel converter ( 14-1 ' to 14-j ' ) can receive serial data DATA composed of m bits of data, and can output m bits of parallel data through m data bus lines in response to a write command signal (WE) and a plurality of control signals (P1~P (m)). Furthermore, each of the serial-parallel converters ( 14-1 ' to 14-j ' ) with the memory cell array 18 be coupled via m data bus lines.
  • Each parallel-to-serial converter ( 16-1 ' to 16-j ' ) can take 2 n bits of data in parallel from the memory cell array 18 receive and output m bits of serial data in response to a read command signal (RE) and the plurality of control signals (P1~P (m)).
  • The clock generator (CLK Gen.) 24 ' may receive the external control signal ECLK and perform a latch operation to output an internal clock signal CLK1 locked to the external clock signal ECLK. After completing the lock operation, the clock generator (CLK Gen.) 24 ' a plurality of internal clock signals (CLK1~CLKI) to the control signal generation circuit (CSG Ckt.) 26 ' output. The control signal generating circuit (CSG Ckt.) 26 ' may output the plurality of control signals (P1~P (m)).
  • As in 21 the control signal generating circuit (CSG Ckt.) generates 26 ' a plurality of control signals (P1 ~ P (m)). According to an exemplary embodiment, m = 2 n + k. As a result, this means that according to an exemplary embodiment of the present invention, one or more serial-parallel converters ( 14-1 ' to 14-j ' ) and / or one or more parallel-to-serial converters ( 16-1 ' to 16-j ' ) is further capable of converting m data bits into a parallel or serial current during a clock of the external clock signal ECLK in response to one or more control signals (P1 ~ P (m)). According to a further exemplary embodiment han delt it is in the 2 n bits of data to valid data, which can be written in a memory cell array to or read from a memory cell array, and the k data bits are dummy data, as described below.
  • As in 21 In addition, a memory element with associated control logic according to another exemplary embodiment of the present invention may further comprise one or more dummy bit generation circuits (FIG. 42-1 ' to 42-j ' ) and / or one or more data masking circuits ( 40-1 ' to 40-j ' ) exhibit. Each data masking circuit ( 40-1 ' to 40-j ' ) may also include one or more error switches SW1 ~ SW ( 2n ).
  • As in 21 shown, the one or each of the plurality of Datenmaskierungsschalter circles ( 40-1 ' to 40-j ' ) the m bits of data from the one or more serial-to-parallel converters ( 14-1 to 14-j ' ) over the m data bus lines. An exemplary structure and operation of the one or more data masking circuits (FIG. 40-1 ' to 40-j ' ) was discussed above with reference to 20 described.
  • The one or each of the plurality of generating circuits ( 42-1 ' to 42-j ' ) for dummy bits, k bits of dummy data (for example data with a value zero or a value vcc) can be sent to one or more parallel-to-serial converters ( 16-1 ' to 16-j ' ) in a read operation.

Claims (44)

  1. Serial-parallel converter ( 14-1 ' - 14-j ' ) for converting a serial bit stream of m bits into a parallel m-bit stream, wherein the m bits include 2 n data bits and k data bits, m is an integer ≥ 3, n is an integer ≥ 1, and k is an integer ≥ 1, comprising: a first register arrangement ( 162 of m-1 registers (DF11-DF1 (m-1)), each for sequentially receiving bits 1 to m-1 of the serial bit stream of m bits in response to each of m-1 control signals (P1-P (FIG. m-1)), each of the m-1 registers of the first register arrangement storing bits 1 to m-1 of the serial bit stream of m bits as m-1 outputs (DI1-DI (m-1)) of the first register array and outputting each of the m-1 outputs of the first register arrangement during a clock cycle of an external clock signal (ECLK) applied to the serial-to-parallel converter; and a second register arrangement ( 164 each of the m registers of the second register arrangement stores bits 1 to m and outputs m as outputs (m) of m registers (DF21-DF2m), each for sequentially receiving the m-1 outputs of the first register array and the mth bit. di1-dim) of the second register arrangement at the same time in response to an m-th control signal (Pm) outputs, wherein all m outputs of the second register arrangement during a clock cycle of the external clock signal (ECLK) are output.
  2. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to claim 1, characterized in that each of the m-1 registers (DF11-DF1 (m-1)) of the first register arrangement ( 162 ) and each of the m registers (DF21-DF2m) of the second register arrangement ( 164 ) are designed as flip-flops.
  3. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to claim 2, characterized in that the flip-flops (DF11-DF1 (m-1), DF21-DF2m) are D flip-flops.
  4. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to one of claims 1 to 3, characterized in that the 2 n data bits and the k data bits valid data for writing in a memory cell array ( 18 . 18 ' ) and for reading from a memory cell array.
  5. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to one of Claims 1 to 4, characterized in that the 2 n data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are test data.
  6. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to one of Claims 1 to 5, characterized in that the 2 n data bits comprise valid data bits for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array, and that the k data bits are masking data.
  7. Serial-parallel converter ( 14-1 ' - 14-j ' ) according to one of claims 1 to 6, characterized in that the 2 n data bits valid data for writing in a memory cell array ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are dummy data.
  8. A method of converting a serial bit stream of m bits into a parallel m-bit stream, wherein the m bits include 2 n data bits and k data bits, m is an integer ≥ 3, n is an integer ≥ 1, and k is an integer ≥ 1, comprising the steps of: sequentially receiving bits 1 to m-1 of the serial bit stream of m bits in response to each of m-1 control signals (P1-P (m)); Storing and outputting bits 1 to m-1 of the serial bit stream of m bits as m-1 first outputs (DI1-DI (m-1)), each of the m-1 first outputs during one clock cycle of an external clock signal (ECLK) is issued; sequentially receiving the m-1 first outputs and the mth bit; and storing and simultaneously outputting bits 1 to m as m second outputs (di1-dim) in response to an m-th control signal (Pm), with all m second outputs output during one clock cycle of the external clock signal (ECLK).
  9. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) for converting a parallel bit stream of m bits (do1-dom) into a serial bit stream (DATA) of m bits, the m bits including 2 n data bits and k data bits, m is an integer ≥ 3, n is an integer ≥ 1 and k is an integer ≥ 1, comprising: a logic gate array of m logic gates (AND1-ANDm), each of the m logic gates connected to concurrently receiving bits 1 to m of the parallel bit stream of m bits, each of the m logic gates sequentially output bits 1 to m of the serial bit stream in response to each of m control signals (P1-Pm) as m outputs of the logic gate array and all m outputs of the logic gate array during a clock cycle of an external clock signal (ECLK) are applied, which is applied to the parallel-to-serial converter; and a logic gate ( 40 ) for sequentially receiving the m outputs of the logic gate array and outputting bits 1 to m as a serial bit stream (DATA) of m bits, bits 1 to m being output during one clock cycle of the external clock signal (ECLK).
  10. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) according to claim 9, characterized in that the m logic gates as AND gates (AND1-ANDm) and the logic gate as an OR gate ( 40 ) are formed.
  11. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) according to claim 9 or 10, characterized in that the 2 n data bits and the k data bits valid data for writing in a memory cell array ( 18 . 18 ' ) and for reading from a memory cell array.
  12. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) according to one of Claims 9 to 11, characterized in that the 2 n data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are test data.
  13. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) according to one of Claims 9 to 12, characterized in that the 2 n data bits comprise valid data bits for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array, and that the k data bits are masking data.
  14. Parallel-to-serial converter ( 14-1 ' - 14-j ' ) according to one of Claims 9 to 13, characterized in that the 2 n data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are dummy data.
  15. A method of converting a parallel bit stream of m bits (do1-dom) into a serial bit stream (DATA) of m bits, the m bits including 2 n data bits and k data bits, m is an integer ≥ 3, n is an integer ≥ 1 and k is an integer ≥ 1, comprising the steps of: simultaneously receiving bits 1 to m of the parallel bit stream of m bits; sequentially output bits 1 to m of the serial bit stream of m bits in response to each of m control signals (P1-Pm) as m first outputs, each of the m first outputs being output during one clock cycle of an external clock signal; and sequentially receiving the m first outputs and outputting bits 1 to m as a serial bit stream (DATA) of m bits, each of bits 1 to m being output during one clock cycle of an external clock signal (ECLK).
  16. Control signal generating circuit ( 26 ' ), comprising: a logic circuit for receiving at least two internal clock signals (CLK1, CLK2) and for generating p control signals (P1, P2, ...), where p is an integer ≥ 3, p = 2 n + k , 2 n is a number of data bits, n is an integer 1, k is a number of data bits, k is an integer ≥ 1, and each of the p control signals is generated sequentially during one clock cycle of an external clock signal (ECLK).
  17. Control signal generating circuit ( 26 ' ) according to claim 16, characterized in that the 2 n data bits and the k data bits are valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array.
  18. Control signal generating circuit ( 26 ' ) according to claim 16 or 17, characterized in that the 2 n data bits valid data for writing in a memory cell array ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are test data.
  19. Control signal generating circuit ( 26 ' ) according to one of claims 16 to 18, characterized in that the 2 n data bits are valid data bits for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array, and that the k data bits are masking data.
  20. Control signal generating circuit ( 26 ' ) according to one of Claims 16 to 19, characterized in that the 2 n data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are dummy data.
  21. A memory element comprising: a memory cell array ( 18 . 18 ' ); a control signal generation circuit ( 26 ' ) for receiving at least two internal clock signals (CLK1, CLK2) and for generating p control signals (P1, P2, ...), where p is an integer ≥ 3, p = 2 n + k, 2 n is a number of Data bits is, n is an integer ≥ 1, k is a number of data bits, k is one integer ≥ 1 and each of the p control signals is generated sequentially during one clock cycle of an external clock signal (ECLK); at least one serial-parallel converter ( 14-1 ' - 14-j ' ) for sequentially receiving a serial bit stream of m bits, where m is an integer ≥ 3, and converting the serial bit stream of m bits into a parallel bit stream in response to each of the p control signals, all bits of the parallel bit stream during one clock cycle the external clock signal are output and at least the 2 n data bits are writable into the memory cell array; and at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) For receiving at least a parallel 2 n -bit stream which has been read from the memory cell array, and converting the parallel 2 n -bit stream into a serial bit stream in response to each of 2 n control signals, all bits of the serial bit stream are output during one clock cycle of the external clock signal and at least the 2 n data bits are readable from the memory cell array.
  22. Memory element according to Claim 21, characterized in that the 2 n data bits and the k data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array.
  23. Memory element according to claim 21 or 22, characterized in that the 2 n data bits valid data for writing in a memory cell array ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are test data.
  24. Memory element according to one of Claims 21 to 23, characterized in that the 2 n data bits comprise valid data bits for writing to a memory cell arrangement ( 18 . 18 ' ) and to Le sen of a memory cell array and that the k data bits are masking data.
  25. Memory element according to one of Claims 21 to 24, characterized in that the 2 n data bits comprise valid data for writing to a memory cell arrangement ( 18 . 18 ' ) and for reading from a memory cell array and that the k data bits are dummy data.
  26. Memory element according to one of Claims 21 to 25, characterized in that the at least one serial-to-parallel converter ( 14-1 ' - 14-j ' ) further receives a write enable signal (WE) to transfer at least the 2 n data bits into the memory cell array (WE). 18 . 18 ' ) to write.
  27. Memory element according to one of Claims 21 to 26, characterized in that the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) further receives a read enable signal (RE) to extract at least the 2 n data bits from the memory cell array (RE). 18 . 18 ' ) to read.
  28. Memory element according to one of Claims 21 to 27, characterized in that the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) converts the m bit serial bit stream into a parallel m-bit stream containing the 2 n data bits and the k data bits, and the m-bit parallel stream into the memory cell array ( 18 . 18 ' ) is writable.
  29. Memory element according to Claim 28, characterized in that the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) converts the parallel m-bit stream into a m-bit serial bit stream consisting of the memory cell array ( 18 . 18 ' ) is readable, wherein the serial bit stream of m bits contains the 2 n data bits and the k data bits.
  30. Memory element according to one of Claims 21 to 29, characterized in that the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) converts the m bit serial bit stream into a parallel m-bit stream containing the 2 n data bits and the 2 n data bits into the memory cell array (FIG. 18 . 18 ' ) are writable.
  31. Memory element according to claim 30, characterized in that the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) converts the parallel m-bit stream into a serial bit stream of m bits, the 2 n data bits from the memory cell array ( 18 . 18 ' ) are readable.
  32. Memory element according to Claim 30 or 31, characterized by an error detection circuit ( 35 ) for receiving the parallel m-bit stream from the at least one serial-parallel converter ( 16-1 ' - 16-j ' ) and generating a composite error detection signal (ED).
  33. Memory element according to Claim 32, characterized in that the error detection circuit ( 35 ): at least one fault detector ( 30-1 - 30-j ) with a divider ( 50 ) for receiving the parallel m-bit stream from the at least one serial-parallel converter and generating a k-bit signal and an error decision circuit ( 52 ) for receiving the k-bit signal and generating an error detection signal (ed1-edj), and a generation circuit ( 32 ) for the error detection signal which combines the error detection signals (ed1-edj) from the at least one error decision circuit and generates the composite error detection signal (ED).
  34. Memory element according to claim 33, characterized in that the at least one fault detector ( 30-1 - 30-j ) implemented a parity check.
  35. Memory element according to claim 33 or 34, characterized in that the at least one fault detector ( 30-1 - 30-j ) implemented a cyclic redundancy check.
  36. Memory element according to one of Claims 32 to 35, characterized by a generating circuit ( 34-1 - 34-j ) for an error detection code which is for receiving the 2 n data bits from the memory cell array ( 18 . 18 ' ) and for generating at least one k-bit code is formed.
  37. Memory element according to Claim 36, characterized in that the generating circuit ( 34-1 - 34-j ) for the error detection code at least one error detection code generator with a shift register ( 60 ) for receiving the 2 n data bits from the memory cell array and for generating m bits and a divider ( 62 ) for dividing the m bits to generate the k-bit code.
  38. Memory element according to one of Claims 30 to 37, characterized by a data masking circuit ( 40-1 ' - 40-j ' ) for receiving the parallel m-bit stream and at least one serial-parallel converter ( 14-1 ' - 14-j ' ) for generating the 2 n data bits that are inserted into the memory cell array ( 18 . 18 ' ) are writable.
  39. Memory element according to Claim 38, characterized in that the data masking circuit ( 40-1 ' - 40-j ' ) comprises a plurality of switches (SW1-SW ( 2n )), each of which receives the 2 n data bits and the k data bits from the at least one serial-parallel converter ( 14-1 ' - 14-j ' ) to mask at least one of the 2 n data bits.
  40. Memory element according to Claim 39, characterized that a masking resolution with growing k increases.
  41. Storage element according to one of Claims 38 to 40, characterized by at least one temperature detector generator ( 38-1 ' - 38-j ' ) for receiving temperature information about the memory cell array ( 18 . 18 ' ) and for outputting k bits of temperature information to the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) is trained.
  42. Memory element according to one of Claims 39 to 41, characterized by at least one dummy bit generator ( 42-1 ' - 42-j ' ) for generating k dummy bits and for outputting the k dummy bits to the at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) is trained.
  43. Method for writing data in a memory cell arrangement ( 18 . 18 ' and reading data from a memory cell array, comprising: receiving at least two internal clock signals (CLK1, CLK2) and generating p control signals (P1, P2, ...), where p is an integer ≥ 3, p = 2 n + k, 2 n is a number of data bits, n is an integer ≥ 1, k is a number of data bits, k is an integer ≥ 1, and all p control signals are generated sequentially during one clock cycle of an external clock signal (ECLK) , sequentially receiving a serial bit stream of m bits, where m is an integer ≥ 3, and converting the m bit serial bit stream to a parallel bit stream in response to each of the p control signals, all bits of the parallel bit stream being clocked during an external cycle clock cycle Clock signal are output and at least the 2 n data bits in the memory cell array are writable; and receiving at least one parallel 2 n- bit stream read from the memory cell array and converting the parallel 2 n- bit stream into a serial bit stream in response to each of the 2 n control signals, all bits of the serial bit stream during one clock cycle of the external clock signal are output and at least the 2 n data bits from the memory cell array are readable.
  44. Memory system, comprising: a memory module ( 200 ' ) having a plurality of memory elements, each memory element comprising: a memory cell arrangement ( 18 . 18 ' ); a control signal generation circuit ( 26 ' ) for receiving at least two internal clock signals (CLK1, CLK2) and for generating p control signals (P1, P2, ...), where p is an integer ≥ 3, p = 2 n + k, 2 n is a number of Data bits is, n is an integer ≥ 1, k is a number of data bits, k is an integer ≥ 1, and each of the p control signals is generated sequentially during one clock cycle of an external clock signal (ECLK); at least one serial-parallel converter ( 14-1 ' - 14-j ' ) for sequentially receiving a serial bit stream of m bits, where m is an integer ≥ 3, and converting the serial bit stream of m bits into a parallel bit stream in response to each of the p control signals, all bits of the parallel bit stream during one clock cycle the external clock signal are output and the 2 n data bits are writable into the memory cell array; and at least one parallel-to-serial converter ( 16-1 ' - 16-j ' ) for receiving at least one parallel 2 n- bit stream coming from the memory cells order to convert the parallel 2 n- bit stream into a serial bit stream in response to each of the 2 n control signals, with all bits of the serial bit stream being output during one clock cycle of the external clock signal and at least the 2 n data bits off the memory cell array are readable; and a memory controller ( 100 ' ), which sends the external clock signal to a phase-locked loop ( 24 ' ) supplies each of the plurality of memory elements such that the at least two internal clock signals are producible by each of the phase locked loops supplied to the control signal generating circuit and the command signal (COM) and an address signal (ADD) for reading the at least 2 n data bits from any of the plurality of memory elements and for writing the at least 2 n data bits to any of the plurality of memory elements.
DE102006032131A 2005-07-05 2006-07-05 Serial to parallel and parallel to serial converter for digital data is based on coupled latching registers Ceased DE102006032131A1 (en)

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KR1020050060444A KR100615580B1 (en) 2005-07-05 2005-07-05 Semiconductor memory device and data input and output method of the same, and memory system comprising the same
KR10-2005-0060444 2005-07-05
US11/430,281 2006-05-09
US11/430,281 US7522440B2 (en) 2005-07-05 2006-05-09 Data input and data output control device and method

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