DE102006026718A1 - Memory device e.g. programmable ROM, forming method, involves forming contact holes in layers of insulating material and layer of active material, and filling contact holes with conducting material to form electrode contacts - Google Patents

Abstract

The method involves depositing a layer of insulating material on a substrate (1), and depositing a layer of switching active material on the layer of the insulating material. The active material layer is structured to form volumes of the active material, and another layer of insulating material is deposited. Contact holes are formed in the layers of the insulating material and switching active material layer. The contact holes are formed with a conducting material to form electrode contacts for connection of volumes of the active material. An independent claim is also included for a memory device with a number of memory cells on a substrate.

Description

method for generating a memory device with at least one memory cell, in particular a phase change memory cell and memory device The invention relates to a method for generating a memory device with at least one memory cell, in particular a phase change memory cell, and storage device.

conventional Memory devices, in particular semiconductor memory devices, can be divided are placed in a first group of so-called functional storage devices, For example, PLAs, PALs, etc. and in a second group of so-called Table storage devices, for example ROM devices, such as PROMs, EPROMs, EEPROMs, flash memories, etc. Further There is a third group of so-called RAM memory, such as DRAMs and SRAMs.

Farther can Memory devices are divided into volatile and nonvolatile memory.

in the In the case of SRAMs (Static Random Access Memory), there is one single memory cell of a few, for example six, transistors, and in the case of so-called DRAMs (DRAM = Dynamic Random Access Memory) consists of a single memory cell of a correspondingly controlled capacitive element, for example a selection transistor, the one with a capacity is connected, in which a bit can be stored as a charge.

There the cargo in capacity the DRAM memory cell only for is maintained for a short time, the charge must be refreshed regularly For example, a corresponding "refresh" is performed approximately every 64 milliseconds.

in the In contrast, a date remains stored in an SRAM cell for as long as as a corresponding supply voltage is supplied, so that the transistors do not lose their sound condition.

Either However, DRAMs as well as SRAMs are volatile memories that hold their data no later than lose as soon as the supply voltage is switched off.

in the Trap of non-volatile Memory devices, so-called non-volatile memory devices (NVMs), for example, EPROMs, EEPROMs, or flash memory, remain the stored data in the memory cell, even if the supply voltage is turned off.

In younger Time is "resistive" or "resistive switching" memory devices become known, for example, so-called phase change memory (Phase Change Memories = PCMs).

In a "resistive" or "resistively switching" memory device can be an "active" or "active" material for example, between two suitable electrodes, for example one Anode and a cathode, is arranged by a suitable Switching process in a conductive and a less conductive state be offset. The conductive state, for example, a logical one and the less conductive state can be a logical one Zero be assigned, or vice versa, which for example one logical arrangement of one bit.

at Phase change memories (PCRAMs), a suitable chalcogenide compound, For example, Ge-Sb-Te (GST) or an Ag-In-Sb-Te compound as switching active material can be used, which is between the two corresponding electrodes is arranged. This switching active material, so the chalcogenide compound, can be between an amorphous and a crystalline state, wherein the amorphous Condition of the relatively weak conductive state is, accordingly a logical zero can be assigned, and the crystalline State, which is the comparatively strongly conducting state, can be assigned according to a logical one. The following will be this material referred to as switching active material.

Around a change from the amorphous, ie the relatively weakly conductive State of the switching active material, to the crystalline, ie the relatively strong conductive state, cause the material must be heated become. For this purpose, a Heizstromimpuls is passed through the material, which heats the switching active material above its crystallization temperature and so reduces the resistance. That way the value can be a memory cell are set to a first logical value.

Vice versa can be a change of state of switching material of a crystalline, i.e., the relative strongly conductive state, to an amorphous, so the relatively weak conductive state, for example, be achieved by that in turn by means of a suitable Heizstrompulses the switching active material on the Melting temperature also heated and subsequently in an amorphous Condition "quenched" by rapid cooling, so that the first logical state reset becomes.

For phase change memory cells Various concepts have been proposed (PCRAM). For example is known as a so-called "Mushroom" cell S.J.Ahn, "Highly Manufacturable High Density Phase Change Memory of 64MB and Beyond ", IEDM 2004, and H. HORII et al. "A novel cell technology using N-doped Films for phase change RAM ", VLSI, 2003, and Y. N. HWANG et al." Full integration RAM based on 0.24 μm CMOS technologies ", VLSI, 2003 and S. Lai et al. "OUM-180 nm non-volatile memory cell element technology for stand alone and embedded applications ", IEDM 2001. Furthermore, a so-called "edge contact" cell is known from Y. H. Ha et al. "An edge contact cell type Cell for phase change RAM featuring very low power consumption ", VLSI, 2003 and the so-called "micro-trench" cell of F. Pellizer et al. is known from "Novel utrench phase change memory cell for embedded and stand alone non-volatile memory applications ", VLSI 2004.

Next In these designs, a so-called "bridge" design is known, which essentially - in one Cross section through a corresponding semiconductor memory cell - a vertical flat, but horizontally oblong Has volume of the switching active material. The ends of this elongated Volume of the switching active material are each on an electrode placed so that the volume forms a bridge between the electrodes formed.

A disadvantage of this currently known "bridge cell" design is that it can not be downsized to a size of 6 or 8 F ² (F ² = minimum feature size) since overlay tolerances could otherwise compromise cell functionality. Furthermore, there are parasitic resistances in the current path through the switching active material, that is, the phase change material caused by the curvy path of the current flow caused by the geometry of the contact surfaces between the phase change material and the electrodes. Furthermore, the tungsten (W) electrode, which is usually chosen for its good processability, has an undesirable effect on the thermal insulation of the cell.

1 shows a cross section through two conventional "bridge" type memory cells in a phase change memory element. The cells are on a substrate 1 formed, which has a selection transistor 2A . 2 B for each memory cell and transistor contacts 3A . 3B , each having a memory cell with a transistor 2A . 2 B connect. Furthermore, the transistors 2A . 2 B with a ground line 4 connected. The spaces between these functional elements are with an insulator 5 filled, for example SiO ₂ . The function and interaction of these and other components in the substrate are known to those skilled in the art.

The memory cells are on the surface of the transistor contacts 3A or 3B and the insulating material 5 showing the spaces between the transistor contacts 3A . 3B fills out, educated. For each memory cell, a first electrode contact 6A . 6B on a transistor contact 3A . 3B educated. In the same layer becomes a second electrode contact 7 formed between the first electrode contact 6A . 6B is placed and the second electrode contact for the switching active material 8A . 8B serves two adjacent memory cells, and so forms a common electrode contact for two adjacent memory cells. The spaces between the first electrode contacts 6A . 6B , ie the "bottom" electrodes, and the common electrode contact 7 , so the top electrode contact for both cells, is filled with an insulator. Both the first electrode contacts 6A and 6B as well as the second common electrode contact 7 may be formed of tungsten, for example.

The switching active material, ie the phase change material 8A . 8B , for a cell is thus deposited on this surface, making it the first electrode contacts 6A . 6B contacted at one end and the second electrode contact 7 contacted at the other end. The second electrode contact 7 is via a V0 contact 9 with a so-called bitline 10 connected, which is usually formed of a metal.

The switching active material, ie the phase change material 8A . 8B , is thus contacted on one side, in this example at the bottom, so-called "bottom" side. A stream passing through the material 8A . 8B flows when read or write access to the cell, so enters on one side in the switching active material and leaves it on the same page. This causes the current flow path to be bent, resulting in parasitic resistances.

Also, the tolerances that result from the stacking and etching of the switching active material and later the material of the V0 connector prevent the area of a memory cell from being reduced to 6 F ² or 8 F ² because the tolerances could cause the V0, for example Head is not placed over the center of the common electrode and not contacted and thus the functionality of a memory cell would be affected.

Furthermore, the tungsten used for the electrode contacts deteriorates the thermal behavior of the memory cell. Since the thermal Leit Tungsten is comparatively good, the heat, which was caused by the heating current pulse, dissipated by the switching active material. Accordingly, this must be taken into account in dimensioning the magnitude of the current for writing, that is, for heating the switching active material to change its conductivity.

One The aim of this invention is therefore a new storage device with a plurality of memory cells, in particular phase change memory cells, propose. Furthermore, a corresponding method for forming Such a device are proposed, with the aforementioned Disadvantages are avoided.

For this purpose, a method is proposed for forming a memory device having a plurality of memory cells on a substrate, wherein the substrate has transistor contacts for connecting a memory cell to a selection transistor, each memory cell has a volume of a switching active material, with the following steps:
Depositing a first layer of insulating material on the substrate;
Depositing a layer of switching active material on the first layer of the insulating material;
Patterning the layer of switching active material to form volumes of the switching active material;
Depositing a second layer of insulating material;
Forming contact holes in the first layer of the insulating material, the switching active material layer and the second layer of insulating material in a single process step, and filling the contact holes with a conductive material to form first and second electrode contacts for connecting the volumes of the switching active material.

Farther is a memory device formed by this method with proposed a plurality of memory cells on a substrate, which defines a reference plane, and wherein each memory cell is a volume switching active material having contact surfaces, and with electrodes for Connecting the volume at the contact surfaces, wherein the surface normal the contact surfaces in parallel to the reference plane, and wherein the extension of the electrodes perpendicular to the reference plane the extent of the contact surfaces the volume of the switching active material ranges.

in the The following are the invention and advantageous embodiments closer by means of drawings explained. Show it:

1 a schematic view of a section through a conventional PCRAM memory cell of the "bridge"type;

2 a cross section of a substrate on which memory cells are formed;

3 a view like in 2 after depositing first layers;

4 a view like in 3 after lithographic processing and etching;

5 a view like in 4 after forming the electrode contacts;

6 a schematic cross section through memory cells.

2 shows a schematic sectional view of a substrate 1 on which two memory cells are formed. Up to this state became the substrate 1 generated by conventional process steps. In the substrate 1 are two selection transistors 2A and 2 B embedded, which are used to select the associated memory cells. The transistors 2A . 2 B can be conventional transistors or transistors that allow the formation of borderless contacts 2A . 2 B are connected to the transistor contacts 3A . 3B each connecting to an electrode contact of a memory cell. The transistor contacts 3A . 3B may be formed of any conductive material such as tungsten or polysilicon.

Likewise, a ground connection 4 made of any conductive material, such as tungsten, in the substrate 1 embedded, with which the selection transistors 2A . 2 B are connected.

The spaces between the described and other functional elements, which are known in the art and not shown in this illustration, are filled with an insulating material, such as silicon dioxide SiO ₂ , to electrically and thermally isolate the elements from each other.

The surface of the substrate 1 , on which the subsequent layers are deposited and further processed, is thus formed by the surface of the transistor contacts 3A . 3B and the surface of the insulating material 5 ,

3 shows a cross section at a later processing time. A first insulating layer 11 is deposited on the surface of the substrate. This layer may be deposited by a conventional method, such as chemical vapor deposition CVD (CVD = chemical vapor deposition), wherein the layer thickness in the range of 5 to 200 nm, preferably between 20 to 50 nm.

This layer 11 is used to form insulating sockets for the volumes of switching active material. The insulating layer may be made of any insulating or semi-insulating material having a significantly higher ohmic resistance than the switching active material and preferably a lower thermal conductivity. A suitable material may for example be an oxide, such as silicon oxide SiO ₂ or aluminum trioxide Al ₂ O ₃ or silicon nitride SiN _2, or any other material which may for example also be derived from a switching active material with a higher ohmic resistance and a higher melting temperature as the switching active material itself.

On the insulating layer 11 By means of a known method, for example CVD, a layer of the switching active material 12 deposited.

In dependence from the so-called "minimum feature size " the thickness of the layer of the switching active material is 5 to 100 nm. The switching active material may be a conventional chalcogenide, such as For example, a compound of Ge-Sb-Te (GST) or a compound be from Ag-In-Sb-Te.

The Volume of the switching active material in the memory cells to be produced become from this layer of switching active material by means of conventional formed lithographic processes with subsequent etching. To the results the lithographic and etching steps may be an optional layer of a hard mask material be deposited on the layer of switching active material.

In the embodiment of the described here The invention is not this optional layer of hardmask material shown. The layer may be formed by a conventional method such as CVD are deposited. Any suitable material can be used in a suitable layer thickness. In the here described embodiment of the invention could Silica can be used as a suitable hard mask material, which is deposited with a thickness of about 40 nm.

In the subsequent process steps of the lithographic processing and the subsequent etching of the layers of the hard mask material, the switching active material and the insulating layer, the volumes of the switching active material of the memory cells become of the layer of the switching active material 12 structured. The etching process must be at the latest when reaching the surface of the transistor contacts 3A . 3B being stopped. In this way, either volume or lines of switching active material are formed, which are structured in a later process step in volume. The bulk switching active material may be elongate in a direction parallel to the surface of the substrate and preferably have a length of "minimum feature size", whereas in the paper plane of the drawing the geometric extension of a volume of switching active material is preferably 1 / 2 to a "minimum feature size" is.

After the layer of switching active material 12 is structured, becomes a second layer of insulating material 13 deposited to fill in the spaces between the volumes or lines of switching active material.

4 shows a state in the production process after the via holes have been etched. By means of the etching process, which may be a conventional etching process using an optional hardmask layer, the contact holes in the second layer become insulating material 13 , the layer of switching active material 12 and the first layer of the insulating material 11 etched in a single process step.

In this embodiment, two volumes 12A . 12B switching active material from a line or layer of switching active material 12 have been formed, each on a pedestal 11A respectively. 11B placed from insulating material and from remaining pieces of insulating material 13A . 13B and if the optional hard mask material has been deposited, are covered by the remnants of that hard mask material.

Each contact hole, which is above a transistor contact 3A . 3B placed, exposes the contact. The horizontal extension of a contact hole, ie parallel to the surface of the substrate 1 , is greater than the horizontal extent of the underlying transistor contact 3A . 3B , Although this is an advantageous embodiment, variants are also possible in which the horizontal extent of a contact hole is equal to or smaller than the horizontal extent of a transistor contact 3A or 3B is.

The vertical extent of the contact hole, that is perpendicular to the surface of the substrate 1 , not only surpasses the vertical extent of the switching active material, ie the thickness of the layer of switching active material 12 , Rather overshadowed the upper end of the contact hole the upper end of the switching active material 12 in that the upper end of the contact formed in the contact hole projects beyond the upper end of the switching active material.

As shown in this embodiment, the expansion of the volumes of the switching active material 12A . 12B in the horizontal direction - ie parallel to the surface of the substrate 1 - Significantly greater than the thickness of the layer of switching active material 12 , The expansion of the volume 12A . 12B in the remaining horizontal direction, which runs into the paper plane in the schematic representation, can be selected accordingly, so that elongate volumes of the switching active material are formed. According to the view shown in the figure, this expansion is not shown.

5 shows the same view as in the previous figures, but after the layers have been deposited, from which the electrode contacts of the memory cells are formed.

An optional, relatively thin layer was deposited, which is the intermediate layer 14 forms. The liner 14 contacts the contact surfaces of the volumes of the switching active material 12A . 12B , The purpose of this intermediate layer is to improve the thermal insulation to the volume of the switching active material and to contact them electrically. A suitable material for this liner 14 For example, titanium (Ti) or titanium nitride (TiN) has a comparatively low thermal but electrically acceptable conductivity.

Since the processing of titanium or titanium nitride compared to the tungsten commonly used is significantly more expensive and therefore more expensive, the layer thickness of the intermediate layer 14 kept relatively low. Accordingly, the thickness of the layer becomes 14 chosen so that the desired properties of the material of the liner 14 At the same time, however, the expenses for the complex and expensive processing are kept low.

In a variant, not shown, the intermediate layer 14 only on the contact surfaces of the volumes of the switching active material 12a . 12b be applied, so without covering the bottom of the contact holes. In this way, the properties of the material of the liner 14 only at the contact surfaces to the volume 12a . 12b of the switching active material.

After the optional layer of the liner 14 is deposited, becomes a layer 15 of an electrically conductive material, which may be, for example, tungsten or another suitable material for forming an electrode contact. This layer 15 fills in the interstices that still exist between the volumes of the switching active material 12A . 12B exist and can be deposited with a conventional CVD or PVD (Physical Vapor Deposition) method.

As mentioned above, the liner is 14 optional and can be omitted. In this case, the layer becomes 15 of tungsten or other suitable material for forming an electrode contact directly on the surface of the wafer, so that the contact holes are filled. As a result of the omission of the thermally insulating intermediate layer 14 the thermal behavior of a memory cell deteriorates, so that a higher current pulse is necessary for heating the switching active material.

As shown in the drawing and mentioned above with respect to the via holes, the top of a contact overhangs the top edge of the volume of switching active material associated with that contact 12A . 12B ,

After the shift 15 The surface of the chip is planarized in preparation for the next process steps, for example using a conventional chemical mechanical polishing (CMP) polishing process. The planarization process is stopped as soon as the state shown in the illustration is reached, that is, when the electrode contact material from the surface of the insulating material, which is the volume of the switching active material 12A . 12B covered, away.

In the described steps so that the volume of the switching active material are formed. The contact surfaces for connecting a volume of switching active material 12A . 12B At electrodes are perpendicular to the surface of the substrate 1 such that the surface normal is parallel to the surface of the substrate and were formed in a single process step after the switching active material was deposited.

Subsequently, both electrode contacts 16 formed, wherein the electrode contacts 16 with the volume of switching active material 12A . 12B the memory cells are electrically connected.

In the illustrated embodiment, the electrode contacts connect 16A . 16C one volume each of the switching active material 12A . 12B with a transistor contact 3A . 3B , In difference To do this, the electrode contact connects 16B two opposite contact surfaces of the volume switching active material with a connection 17 which establishes the connection to another line, for example a bit line.

In 6 the results of the last process steps are shown. That is, in a further step, an insulating layer 18 deposited, which covers the underlying elements and electrically insulated from each other and which is used to achieve a planar surface. Subsequently, by means of a known lithographic etching process, a contact hole for a connection 17 educated. The corresponding etching process is carried out until the contacts 16 are exposed, but stopped at the latest before the switching active material 12 is reached. Thereafter, a layer of suitable electrically conductive material, for example tungsten, is deposited on the insulating layer by means of a conventional method, for example CVD 18 deposited and planarized by means of a suitable planarization process, for example by means of CMP. The connection 17 closes at the electrode contact 16B and forms an electrical connection between the electrode contact 16B and a continuation line as mentioned above, for example, a bit line.

In a subsequent process step, another line 19 , For example, a bit line, on the insulating layer 18 or the surface of the connection 17 be formed. The administration 19 can be deposited from a suitable material and using a known method such as CVD or PVD and then patterned by a known lithographic etching process.

In The described method steps is thus a method for Forming volumes or lines of switching active material disclosed which are embedded horizontally and vertically in insulating material. The surfaces for both Electrode contacts of a memory cell are in a subsequent step by means of a single etching step formed, with contact holes be formed, which are filled with contact material, so that the contacts project in the vertical direction the volume of the switching active material. Thus, a method is described in which the contact surfaces and the contacts are formed after the switching active material was separated.

The single etch process for forming the contact holes for the contacts enables the minimization of overlay tolerances so that the memory cell area can be reduced to a minimum of 8 F ² to 6 F ² .

Farther are the contact surfaces to the electrode contacts on the opposite end faces of Volume of switching active material placed so that the current flow path is linear due to a volume of switching active material and thus reduces parasitic resistances become.

Additional process steps are not needed as compared to a conventional manufacturing process for known "bridge" type memory cells. The method can be applied to the surface of a substrate as described in 2 set up, wherein the substrate has been formed by conventional methods.

Finally is to mention that so far formed and that according to the described method produced chip memory chip further processed and processed is, for example, the memory cells formed so far on the electrodes For example, continue to connect according to known methods.

1

substratum

2a, 2 B

selection transistor

3a, 3b

transistor Contact

4

ground line

5

insulator in substrate

6a, 6b

first electrode contact

7

second Electrodenkontakt

8a, 8b

switching active / phase change material

9

V0 Contact

10

bit

11

layer insulating material

12

layer switching active material

12a, 12b

volume switching active material

13

layer insulating material

14

Ti / TiN liner

15

tungsten

16

electrodes

16a, 16b, 16c

electrode

17

connection

18

insulating

19

bitline

Claims (14)

Method for forming a memory device having a multiplicity of memory cells on a substrate ( 1 ), the substrate ( 1 ) Transistor contacts ( 3A . 3B ) for connecting a memory cell to a selection transistor ( 2A . 2 B ) and each memory cell has a volume ( 12A . 12B ) of a switching active material ( 12 ) comprising the steps of: depositing a first layer of insulating material ( 11 ) on the substrate ( 1 ); Depositing a layer of switching active material ( 12 ) on the first layer of the insulating material ( 11 ); Structuring the layer of the switching active material ( 12 ) to volume ( 12A . 12B ) of the switching active material ( 12 ) to train; Depositing a second layer of insulating material ( 13 ); Forming contact holes in the first layer of the insulating material ( 11 ), the switching active material layer ( 12 ) and the second layer of insulating material ( 13 ) in a single process step, and filling the contact holes with a conductive material to first and second electrode contacts ( 16 ) for connecting the volumes ( 12A . 12B ) of the switching active material ( 12 ) to build. The method of claim 1, wherein after forming the contact holes, a layer of electrically conductive, thermally insulating material ( 14 ) is deposited. Method according to one of the preceding claims, wherein a first electrode contact ( 16A . 16C ) is formed on the surface of a first contact to a volume ( 12A . 12B ) of the switching active material ( 12 ) with a transistor contact ( 3a . 3B ) in the substrate ( 1 ) connect to. Method according to one of the preceding claims, wherein each electrode contact ( 16B ) between two adjacent volumes ( 12A . 12B ) switching-active material ( 12 ) to form a common second electrode contact of the two adjacent volumes ( 12A . 12B ) of the switching active material. Method according to one of the preceding claims, further comprising the step that an electrode contact ( 17 ) on the second electrode contact ( 16B ) is formed to the second electrode contact ( 16B ) with a bitline ( 19 ) connect to. Method according to one of the preceding claims, wherein a hard mask layer on the layer of the switching active material ( 12 ), and wherein the hard mask layer in the same process steps for forming the volume ( 12A . 12B ) of the switching active material is etched. Method according to one of the preceding claims, wherein a hard mask layer on the second layer of insulating material ( 13 ), and wherein this hard mask layer is etched in the same process steps when the via holes are etched. Method according to one of the preceding claims, wherein the electrically conductive, thermally insulating material ( 14 ) Titanium or titanium nitride and wherein the electrically conductive material ( 15 ) to fill the gaps is tungsten. Method according to one of the preceding claims, wherein the contact surface of the switching active material 12 for connecting to the electrodes ( 16A . 16B . 16C ) after the deposition of the switching active material ( 12 ) are formed. Method according to one of the preceding claims, wherein the substrate ( 1 ) forms a reference plane, and wherein the surface normal of the contact surfaces of the volume ( 12A . 12B ) of the switching active material is parallel to the reference plane. Method according to claim 10, wherein the contact surfaces for connecting the volumes of switching-active material ( 12A . 12B ) with the electrodes ( 16A . 16B . 16C ) are formed in a single etching step. Memory device with a plurality of memory cells on a substrate ( 1 ), which defines a reference plane, and wherein each memory cell contains a volume of switching active material ( 12A . 12B ) with contact surfaces, and with electrodes for connecting the volume ( 12A . 12B ) at the contact surfaces, wherein the surface normal of the contact surfaces is parallel to the reference plane and wherein the extension of the electrodes ( 16A . 16B . 16C ) perpendicular to the reference plane, the extent of the contact surfaces of the volume of the switching active material surmounted. A memory device according to claim 12, wherein a layer of thermally insulating, electrically conductive material ( 14 ) between the contact surfaces of an electrode ( 16A . 16B . 16C ) and the volume of the switching active material ( 12A . 12B ) is placed. Storage device according to one of the preceding claims 12 to 13, wherein the layer of the thermally insulating, electrically conductive material ( 14 ) Is titanium or titanium nitride.