DE102006006300A1 - Integrated circuit e.g. electrically erasable programmable ROM, arrangement for automobile industry, has electronic units covered by passivation layer, where identification data is provided in substrate and clearly indicates circuit - Google Patents

Abstract

The arrangement has a semiconductor substrate (105) and electronic units formed on the substrate. The electronic units are covered by a passivation layer. Identification data (104) is provided over or in the substrate. The data clearly indicates the integrated circuit. The integrated circuit of different assembly groups is combined to a test group, where the electronic units are examined individually for their operability. An independent claim is also included for a method for personalizing an integrated circuit arrangement.

Description

The The invention relates to an integrated circuit arrangement and a Method for personalizing an integrated circuit arrangement.

Manufacturer of products with semiconductor devices and users of these products often put in the quality inspection or while the operation of these products errors. These errors can be from caused by defective semiconductor devices. In such cases, the defective semiconductor devices, e.g. in the automotive supply industry, returned by the users to the respective manufacturer become.

The Manufacturers of semiconductor products, e.g. of semiconductor chips for the automotive industry, It is important to understand the history and the origin of each semiconductor device to be able to understand for the reasons for the Failure to detect these semiconductor devices to initiate corrective action to be able to and recall other affected semiconductor devices as soon as possible to be able to. An important information for this are the manufacturing conditions of this defective semiconductor device. In this case, in particular, the position of a corresponding semiconductor device on a semiconductor wafer and the position of the semiconductor wafer in the lot, with which the semiconductor device was manufactured, interesting. Knowledge of the relevant information allows conclusions to be drawn which semiconductor devices as well could be affected by this error, so that more semiconductor devices, possibly are faulty, can be identified. It is also for engineers important to know the circumstances of the manufacturer Semiconductor device was made to work in the event of a or a reliability problem to be able to react quickly.

To solve this problem, there are the following approaches:
The fabrication of the semiconductor devices is documented by means of a "tracking" system, which records how a wafer lot is split into assembly lots and how a plurality of assembly lots are merged and possibly redistributed and finally distributed on tape rolls that delivered to customers. By means of the tracking system, it is possible to trace the origin of a single semiconductor device back to its original lot and its original semiconductor wafer. However, this system is time consuming and errors can easily occur. Furthermore, there is no way to determine the x and y coordinates of the semiconductor device on the original semiconductor wafer. Because manufacturing facilities do not have a connection to a tracking system available to all machines, documentation is usually done manually, for example, on paper, making traceability even more time-consuming and prone to errors.

A different possibility is, the relevant information in a non-volatile To write memory, such as an EEPROM or flash memory on the semiconductor device. However, this is only possible if such a memory element Part of the technology is and in the corresponding semiconductor device is implemented. Otherwise, it is very expensive to have such a memory element only for the purpose of traceability of the semiconductor device in addition to to implement.

Of the Invention is based on the problem, in a simple way the origin to be able to determine a semiconductor element.

The Problem is solved by a method and a device with the features solved according to the independent claims.

According to one Aspect of the invention comprises an integrated circuit arrangement a semiconductor substrate and a plurality of electronic elements, which are formed on and / or in the semiconductor substrate, wherein over or in the semiconductor substrate identification data are provided, which uniquely identify the integrated circuit.

An integrated circuit arrangement may be configured as any electronic component integrated on a substrate and thus illustratively forms a microchip, for example. In particular, these may be ICs (integrated circuits), microprocessors, microcontrollers or memory elements having a multiplicity of transistors. The electronic elements forming part of this integrated circuit arrangement are, for example, transistors, resistive elements or other types of devices. The semiconductor substrate is made of silicon dioxide (SiO ₂ ), for example, and it is not limited to this material. By means of a known technique, data are provided above or in the semiconductor substrate, ie permanently "written" into / onto the semiconductor substrate by means of this technique, which represent a clear identification of the integrated circuit arrangement and thus permit unambiguous identification of this integrated circuit arrangement. For example, a laser serial number may be etched into a layer of the integrated circuit device within a particular range, with the serial number identifying when and where this integrated circuit has been fabricated. The identification data are arranged so that the function of inte grated circuit arrangement is not disturbed. Furthermore, the identification data can be coded in order, for example, to save space and / or to prevent reading of the information and conclusions from the information on manufacturing processes by unauthorized persons. That is, the identification data may be expressed by a code which is generally a rule for converting the identification data to be encoded and / or characters in which the identification data is expressed into other data or characters. Exemplary codes are the ASCII code, which assigns a bit sequence to each character, and the bar code, which assigns a sequence of wide and narrow bars to each character.

Consequently may be the origin of a corresponding integrated circuit be found by exposing the layer that the Serial number of the integrated circuit arrangement has, and the serial number is read out with a microscope, for example. Because the serial number already in the production of the integrated Circuit arrangement is attached, the integrated circuit arrangement remains identifiable even if the production lots and / or wafers, on which this integrated circuit arrangement is arranged, later and with integrated circuit arrangements of others Production lots and / or wafers are combined without an additional Effort arises. Unlike conventional methods, the Identification data according to a Aspect of the invention thus already during a front-end processing on the integrated circuit arrangement are applied.

According to one Another aspect of the invention features a method of personalization an integrated circuit arrangement forming the steps electronic elements on a semiconductor substrate and registered of identification data, which uniquely identifies the integrated circuit mark, over or in the semiconductor substrate.

further developments The invention will become apparent from the dependent claims.

For example In the integrated circuit arrangement, the majority is electronic Elements covered by a passivation layer, and the identification data are applied to the passivation layer.

There conventionally the plurality of electronic elements covered with a passivation layer and this passivation layer except any vias or vias has no electronic elements or other structures, it is particularly advantageous the identification data on the passivation layer applied. Here is also the positioning of the identification data particularly easy on the passivation layer, and for application The identification data can be a large "font size" can be used, so that the identification data even with a low magnification can be read out by a microscope.

In another embodiment the identification data are on a portion of the semiconductor substrate arranged next to the electronic elements.

It One advantage of this arrangement is that identification data is not in a simple manner, e.g. by grinding the passivation layer can be removed because in this case also the electronic elements are destroyed, those in the same level or higher are arranged as the identification data.

According to one In another embodiment of the invention, the semiconductor substrate is a Semiconductor wafer.

Especially Preferably, the semiconductor substrate is a semiconductor wafer, as it used in the production of integrated circuit assemblies. In particular, you can Monocrystalline silicon semiconductor wafers, silicon carbide, gallium arsenide or indium phosphide.

In another embodiment The identifying identification data have the coordinates the integrated circuit arrangement on a semiconductor wafer, on which this is formed, the number of the semiconductor wafer in one Lot, which has the semiconductor wafer, and / or the number of the lot on.

through The identification data mentioned can be the origin of the corresponding integrated circuit arrangement, i. of the IC, clearly stated become. Furthermore, these identification data are very easy during the Production of the integrated circuit arrangement to produce.

According to one Another embodiment of the invention, the integrated circuit arrangement casing on.

Further the integrated circuit arrangement has a housing, preferably made of a resin at least partially around the integrated circuit arrangement is poured so that the electronic elements before mechanical, electrostatic and chemical influences are protected. Thus, a simpler Processing in electronic systems guaranteed.

In another embodiment a lithographic step is performed on the integrated circuit array and the identification data is patterned onto or into the circuit array during the lithographic step. For example, a portion of the photoresist material is exposed a second time after exposure of the photoresist material by means of a mask so that the identification data is transferred into the photoresist material before the photoresist material is developed.

The Identification data can while a lithographic step used to form the electronic Elements used is structured on or in the circuit arrangement become. Since the identification data e.g. through a second exposure step transferred into the photoresist material can be the identification of the electronic circuit arrangement done in a simple way and in particular easily in the usual Production process to be inserted.

According to one Another embodiment of the invention is a plurality of integrated circuit arrangements formed on a semiconductor wafer.

Especially Preferably, the semiconductor substrate is a semiconductor wafer, as it used in the production of integrated circuit assemblies. In particular, you can Monocrystalline silicon semiconductor wafers, silicon carbide, gallium arsenide and indium phosphide.

For example the semiconductor wafer is cut to singulate the integrated circuit devices, allowing the integrated circuit arrangements until final completion can be further processed. The cutting of the semiconductor wafer can also by means of various Other methods known per se take place.

According to one Another embodiment of the invention, the identification data inscribed with a laser.

The Laser method has the advantage that, in contrast to an etching method, no mask needed and thus the step of writing the identification data is simplified on the electronic circuit arrangement, without the Significantly extend the production process.

In another embodiment the identification data is a bar code or a dot matrix code encoded via or inscribed in the semiconductor material.

The Use of bar code and dot matrix code in registered mail The identification data has the advantage that coded so Identification data are easily read by machine can, when the layer having the identification data is exposed is. Furthermore, can Competitors of bar code and dot matrix code, or in general from coded identification data hardly read information and evaluate.

Further embodiments the method of personalizing an integrated circuit device correspond to the respective embodiments the integrated circuit arrangement.

embodiments The invention is illustrated in the figures and will be discussed below explained in more detail.

1 FIG. 12 is a diagram illustrating the propagation of contamination of semiconductor ICs with defective semiconductor ICs. FIG.

2 shows a cross section through a semiconductor IC and portions of the semiconductor IC for applying identification data.

3 shows a plan view of a semiconductor wafer and on a metal carrier with a plurality of semiconductor ICs.

4 shows a cross section through a semiconductor IC and a metal carrier.

The Figures described only serve to explain embodiments of the invention and in particular do not represent true to scale illustrations the subject of the invention.

In show all the figures where possible same or similar Elements have the same reference numerals.

1 FIG. 12 is a diagram illustrating the propagation of contamination of semiconductor ICs with defective semiconductor ICs. FIG.

1 serves to explain the problem that occurs in quality assurance in semiconductor production, and results in that in a conventional production process with a relatively small number of actually defective semiconductor ICs often a multiple of this number of semiconductor ICs must be recalled and destroyed, although the majority of the recalled semiconductor integrated circuits or ICs are error free.

According to the prior art, it is not possible to pinpoint which semiconductor ICs may be faulty because the methods for post-processing often are incomplete and prone to error. This leads, for example, to the fact that in a case when a faulty semiconductor IC has been sent back to the manufacturer, only the wafer lot and / or the wafer in which the faulty semiconductor IC has been manufactured can be determined. Usually, all semiconductor ICs are then recalled from this wafer lot to avoid further malfunctioning of electronic devices in which these semiconductor ICs are used. However, when this wafer lot in which a faulty semiconductor IC is fabricated has been mixed with other wafer lots, the number of semiconductor ICs to be recalled multiplies because often it is not easy to assign.

In 1 are a plurality of wafer lots 50 shown, each having a plurality of wafers 40 having. On every wafer 40 For example, a plurality of semiconductor ICs (not shown) are formed. In the 1 illustrated wafer lots 50 are shown in a manufacturing state where those in the wafer lots 50 contained wafers 40 be fed to a wafer testing process. In other words, the wafers 40 are already functional, but the semiconductor ICs are not isolated yet.

The wafers 40 a wafer lot 50 be in different groups 60 divided by wafers, which are each tested in a wafer test step to those on the wafers 40 formed electronic components to check for errors. These wafer groups 60 can also use wafers 40 different wafer lots 50 exhibit. The wafer groups 60 are fed to a device for performing a wafer test. From these wafer groups 60 be after testing the wafers 40 Groups, also called assembly lots 70 be formed formed. The assembly lots 70 are separated into a plurality of semiconductor ICs. Subsequently, the semiconductor ICs 100 a step of packaging the singulated unpackaged semiconductor ICs 100 fed.

After the housing of the isolated semiconductor ICs 100 (also referred to as "packaging"), the semiconductor ICs 100 different assembly lots 70 in test lots 80 united, and fed to a process for testing the electronic components. Every test lot 80 may be semiconductor ICs 100 different assembly lots 70 exhibit. In this test, the electronic components are individually tested for their functionality. The tested semiconductor ICs 100 are then in turn into a plurality of so-called "reels" 90 divided, and delivered to end users. Consequently, every reel points 90 a plurality of tested semiconductor ICs 100 on.

Join now at a semiconductor IC 100 an error on and becomes this semiconductor IC 100 returned to the manufacturer for examination, for example, it can only be established in a conventional manner by the manufacturer that the defect in the structuring of the semiconductor wafer has occurred, and that this semiconductor IC 100 in a particular wafer lot 50 was structured.

Because the "origin" of this defective semiconductor IC 100 can not be narrowed down, it must therefore be assumed that the remaining semiconductor ICs 100 this wafer lot 50 could be flawed. Because the semiconductor ICs 100 this wafer lot 50 but several times separated, processed in different lots and partly with semiconductor ICs of other wafer lots 50 All reels must be brought together 90 with all semiconductor ICs 100 be recalled, the at least one semiconductor IC 100 the faulty wafer lot 50 according to the prior art does not exist between semiconductor ICs 100 that with different wafer lots 50 can be distinguished.

Consequently, a plethora of semiconductor ICs 100 recalled and destroyed, although only a fraction of these semiconductor ICs 100 actually has an error.

According to an aspect of the invention, identification data such as the x and y coordinates of the semiconductor IC becomes 100 on the corresponding semiconductor wafer, a number of the semiconductor wafer in a wafer lot having the semiconductor wafer, and a number of the wafer lot 50 on an already existing layer, such as the last, ie top, metal layer of the semiconductor IC 100 enrolled. Alternatively, the identification data may be written in underlying layers. In particular, each semiconductor IC 100 be personalized with his own coordinates. If the source of a particular semiconductor IC 100 in the manufacture, after assembly, or after the submission to the manufacturer, to be determined, therefore, for example, only the top metal layer needs to be removed, so that the data of the semiconductor IC 100 can be read out. For example, only the housing of the semiconductor IC needs 100 which is an easy task for an error analysis department.

2 shows a cross section through a semiconductor IC and portions of the semiconductor IC for applying identification data.

How out 2 is apparent, is the semiconductor IC 100 on a semiconductor substrate 105 formed, for example, a conductive silicon substrate, on the alternately different layers have been applied and structured by means of conventional technologies. In particular, on the semiconductor substrate 105 a poly-silicon layer 110 be formed. Furthermore, in the later course of the manufacturing process, a plurality of metallization levels 108 and 109 are formed, the mutually or the poly-layer 110 completely or partially overlap laterally, with the metallization levels 108 . 109 are insulated from each other by a plurality of interconnects, by means not shown Intermetalldielektrikum layers and are electrically coupled together only by means of the intermetallic dielectric layers passed through contact vias. The entire layer arrangement may be provided with an oxide layer 107 be covered. In 2 For the sake of simplicity, the presentation of further layers has been omitted.

A section 104a the in 2 shown poly-layer 110 is not overlapped by a metallization level. This overlap-free section 104a the poly layer 110 is therefore suitable for that at the end of the manufacturing process, ie after the formation and structuring of the plurality of layers on the semiconductor substrate, thereon, the identification data of the respective semiconductor IC 100 be enrolled.

A section 104b of the semiconductor substrate 105 is neither of the poly layer 110 still covered or overlapped by another layer, so that too this overlap-free section 104b suitable for recording the identification data.

Generally is advantageously any layer for receiving the identification data suitable, in a simple way after complete processing again can be exposed.

With regard to the manufacturing process, during the wafer manufacturing process, the various layers of a wafer become 40 structured by photolithographic steps. A photoresist is added to the wafer 40 applied and irradiated with light that passes through a mask having the required structures. For example, the photoresist is irradiated with ultraviolet radiation. Thereafter, the photoresist is developed and the structure is made into the portion of the wafer by means of an isotropic or anisotropic etching process 40 etched below the photoresist. In accordance with the invention, a laser can be used to expose portions of the photoresist a second time after exposure through a mask but prior to developing the photoresist. In this step, the desired structure is directly written by the laser and includes the wafer lot number, the wafer number and the x and y coordinates of the semiconductor IC, and other data including the semiconductor IC 100 identify, on.

In In the following development step, the structure of this appears Data in the photoresist so that during the last etching step the data is etched into the material of the layer.

In in other words when exposed by means of a mask to e.g. an ECG aligner device the semiconductor IC identification data set on the mask and by the following development step into the photoresist material imprinted. This is a place to imprint needed on the photo material. This method does not work with semiconductor ICs using of a stepper. Furthermore, this method requires An additional Masks lithography step.

For example, the last metallization plane, ie, the topmost metallization plane, is used, so that the structure can be easily read by means of an optical microscope. The coordinates of the semiconductor IC 100 are provided by a software program to the laser device, wherein the software program receives the data from the wafer handler so that each semiconductor IC 100 finally his unique identification data 104 having.

According to a further embodiment of the invention, the patterning of the layer by means of the photomask may be carried out by a method using laser light exposure. In this case, both the exposure through the mask (to realize the required circuit structure in the layer) and the writing of the chip identification data 104 performed by the same device and in the same process step of the laser. Consequently, only one instead of two exposure devices is needed, and the mask can be saved.

Alternatively, the laser device can be used not only as an exposure means but also for directly writing the identification data 104 in the last, ie top, metal layer by etching or melting the metal. Alternatively, the identification data 104 similarly inscribed in a layer of another material. In this way, the identification data 104 already in the frontend, ie before separation, every semiconductor chip 100 be registered accordingly.

A corresponding method may also be used in a later manufacturing step, eg during the assembling step after the wafers 40 were etched and the semiconductor ICs 100 on a metal carrier, ie a lead frame 120 , be were strengthened. For example, in this case, an assembly lot number can be added to a wafer lot number.

A Another option is to replace the letters and numbers with a barcode or a dot matrix code to the required space to reduce.

3 shows a plan view of a semiconductor wafer and on a metal carrier with a plurality of semiconductor ICs.

A metal carrier, ie a lead frame 120 , points the supply lines 140b a plastic-encapsulated housing 150 on and keeps these leads 140b before the enclosure. After packaging, the supernatant metal carrier material is cut away. In other words, the lead frame 120 a thin metal layer that electrically couples wiring of small electrical terminals on the semiconductor surface to the extensive wiring on electrical devices and circuit boards.

In 3 is a plurality of semiconductor ICs 100 shown completed to the extent that repeatedly layers were deposited and patterned on the semiconductor substrate. Subsequently, the semiconductor chips 100 on the semiconductor wafer 40 sporadically. Further, a lead frame 120 shown. On every lead frame 120 become a plurality of semiconductor ICs 100 arranged. Using dashed lines are on the lead frame 120 Areas are shown, each one a semiconductor IC 100 take up. In each of these areas identification data are subsequently written in a further step, which the corresponding semiconductor IC 100 mark.

4 shows a cross section through a semiconductor IC and a metal carrier.

4 shows a semiconductor IC 100 with a housing 150 , the actual semiconductor crystal 130 on a lead frame 120 and wires 140a for coupling the semiconductor crystal 130 with the lead frame 120 , At the lead frame 120 are conductive pins 140b (ie feet), which is an electrically conductive connection of the semiconductor crystal 130 over the coupling wires 140a and the lead frame 120 with electrical tracks (not shown) on a circuit board (not shown). On a section of the lead frame 120 that is not from the semiconductor crystal 130 is covered, are the identification data 104 of the corresponding semiconductor crystal 130 enrolled. Consequently, each semiconductor IC 100 identification data 104 exhibit. The identification data 104 can be read in a simple manner, for example by means of an optical microscope, when the housing 150 of the semiconductor IC 100 is removed. Removing the housing 150 a semiconductor IC 100 is easy to implement with conventional methods.

40

wafer

50

wafer lot

60

wafer group

70

Assemblylos

80

Test lot

90

reel

100

Semiconductor IC

104

identification data

104a

non-overlapping section

104b

non-overlapping section

105

Semiconductor substrate

107

oxide

108

metallization

109

metallization

110

Poly layer

120

lead frame

130

Semiconductor crystal

140a

coupling wire

140b

supply

150

casing

Claims (17)

Integrated circuit arrangement with one Semiconductor substrate, a plurality of electronic elements, which are formed on and / or in the semiconductor substrate, wherein over or in the semiconductor substrate identification data are provided, which uniquely identify the integrated circuit. Integrated circuit arrangement according to claim 1, wherein the plurality of electronic elements of a passivation layer are covered and the identification data applied to the passivation layer are. Integrated circuit arrangement according to claim 1, wherein the identification data on a portion of the semiconductor substrate are arranged next to the electronic elements. Integrated circuit arrangement according to a the claims 1 to 3, wherein the semiconductor substrate is a semiconductor wafer. The integrated circuit device according to claim 4, wherein the characteristic identification data comprises: the coordinates of the integrated circuit device on a semiconductor wafer on which it is formed, • the number of the semiconductor wafer in a lot containing the semiconductor wafer, and • the number of the lot. Integrated circuit arrangement according to a the claims 1 to 5, which is a case having. Method of personalizing an integrated Circuit arrangement with the steps: • forming electronic elements on a semiconductor substrate; • writing of identification data, which uniquely identify the integrated circuit, via or in the semiconductor substrate. Method according to claim 7, wherein on the integrated circuit arrangement a lithographic Step performed and the identification data during the lithographic Step is structured on or in the circuit arrangement. Method according to claim 8, wherein after the exposure of a photoresist material means one mask a portion of the photoresist material a second Is exposed so that the identification data is transferred into the photoresist material before the photoresist material is developed. Method according to claim 7, wherein on the integrated circuit arrangement, a passivation layer is formed and the identification data on the passivation layer be enrolled. Method according to claim 7, wherein the identification data on the semiconductor substrate next the integrated circuit arrangement are written. Method according to one the claims 7 to 11, wherein a plurality of integrated circuit arrangements be formed on a semiconductor wafer. Method according to claim 12, wherein the semiconductor wafer for dicing the integrated circuit devices is cut. Method according to one the claims 7 to 13, wherein coordinates of the integrated circuit arrangement on the semiconductor wafer, a number of the semiconductor wafer in one Lot having the semiconductor wafer, and inscribed a lot number become. Method according to one the claims 7 to 14, wherein the identification data is written by a laser become. Method according to one the claims 7 to 15, wherein the identification data as a bar code or as Dot matrix code encodes via or inscribed in the semiconductor material. Method according to one the claims 7 to 16, wherein formed around the integrated circuit assembly, a housing becomes.