DE102006003390B3 - Method for forming clock signals e.g. for communication installations, involves comparing clock frequency information of clock signal with given clock frequency information - Google Patents

Abstract

A method for forming a clock signal, involves forming a generator signal (clk1...clk2) having different phase positions from an oscillator clock signal and in which clock frequency information of the clock signal (ts) is compared with a specified clock frequency information, and depending on the comparison result, at least one control signal (ctr) is formed, and in which with the aid of at least one control signal (ctr) and the generator clock signals having the different phase positions the clock periods of the clock signals being formed are shortened, lengthen, or not changed. An independent claim is included for a clock device for forming a digital clock signal.

Description

In Communication facilities are due to constantly increasing volumes of information and an associated constantly increasing processing and transmission speed usually several digital clock signals with high and different To provide clock frequencies. Therefor Several clock generators are required, with the help of several formed with respect to their phase position or clock frequency controlled clock signals become. This control of the phase position and the clock frequency for clock signals is only with considerable circuit and program technical. Effort to realize.

Out WO 2005/109643 A1 discloses a clock signal generator in which each of a reference clock signal different phase angles having basic clock signals are formed, from which the clock signal is generated.

In the US 4,870,665 a digital pulse generator is described which generates a pulse signal with adjustable pulse width or pulse frequency from an oscillator clock signal.

The The object underlying the invention is to form of clock signals to improve. The task is characterized by the features the claims 1 and 8 solved.

One An essential advantage of the invention is the fact that for the forming of clock signals only an unregulated oscillator or quartz oscillator is required. Another advantage is that the formation of a Clock signal or of several clock devices completely in integrated circuits can be realized, whereby the switching and programming effort is minimized.

advantageous Further developments of the method according to the invention and an embodiment of the invention a clock device are the other claims too remove.

in the The invention is based on four drawings explained in more detail. Show

1 in a block diagram an inventively designed clock device,

2 an inventively designed control device for extending the period of the clock signals to be formed,

3 a timing diagram for the in 2 shown control unit for turning on the respective control logic and

4 a timing diagram for the in 2 shown control unit for switching off the respective control logic.

In 1 a clock device designed according to the invention is shown with a quartz oscillator PXO which generates a digital oscillator clock signal with a frequency of 100 MHz, for example for an application in a local network. This oscillator clock signal is transmitted to a clock unit TE, in which four generator clock signals clk1..clk4 assumed from the oscillator clock signal for the exemplary embodiment are formed and transmitted to the control unit STE. The clock unit TE can advantageously be realized in an FPGA, in which a control unit STE, a comparison unit VE and the quartz oscillator PXO are implemented in terms of circuitry and program technology. The four respectively a phase shift of 90 ° having generator clock signals clk1..cl4 are advantageously realized in the clock unit TE each by a PLL (Phase Locked Loop) function, the clock frequency of the oscillator clock signal be lower or higher than the clock frequency of the generator clock signals clk1..clk4 can.

The function of the control unit STE consists in shortening and lengthening the period of the clock signal ts to be formed as a function of a control signal ctr fed to the control unit STE, where is achieved in the extension or shortening of the period of the clock signal to be formed in that, starting from a currently connected as a clock signal ts generator clock signal clk1..clk4 a generator signal clk1..clk4 is switched, the one compared to the currently switched generator clock signal clk1..clk4 a 90 ° lagging or 90 ° leading phase.

The function of the control unit STE is after the explanation of the basic arrangement according to 1 in the 2 to 4 explained in more detail.

The at the output A of the control unit STE present clock signal ts is transmitted to a arranged in a comparison unit VE counter Z. In the counter the clock pulses of the clock signal ts are periodically counted and at the end of the respective counting period becomes the counter reading ZSZ of the meter Z passed to a comparator V. Furthermore, a predetermined, stored in a register R is meter reading ZSR connected to the comparator V. The counter reading ZSR in register R represents the predetermined clock frequency information one in terms of his Clock frequency ideally formed clock signal ts. At each comparison of the both counter readings ZSR, ZSZ in comparator V thus becomes the difference of the clock frequencies representing Counter readings ZSR, ZSZ determined and formed therefrom a control signal ctr.

In 2 By way of example, a possible realization of a control unit STE for extending periods of the clock signal ts to be formed is shown, the configuration of the control unit STE being tuned to the four phase-shifted generator clock signals clk1..clk4. This variant is used when the generator clock signals clk1..clk4 generally have a higher clock frequency than the clock signals to be formed, since in this case the clock period of the generator clock signal clk1..clk4 is extended more or less, ie more or less period sections are inserted. The control unit STE is essentially formed by four control logics SL1..SL4, in each of which a chain of five delay elements V1..V5 is arranged, wherein in 2 For example, only the third control logic SL3 is shown in detail. To a data input D of the first of the five delay elements V1..V5 is in each case the control signal ctr out. The delay elements V1..V5 are advantageously implemented by flip-flops present in the FPGA.

• – der ersten Steuerlogik LS1 ist das erste Generatortaktsignal clk1,
• – der zweiten Steuerlogik LS2 ist das zweite Generatortaktsignal clk2,
• – der dritten Steuerlogik LS2 ist das dritte Generatortaktsignal clk3, und
• – der vierten Steuerlogik LS4 ist das vierte Generatortaktsignal clk4

geschaltet.To the clock inputs of the delay elements V1..V5

• The first control logic LS1 is the first generator clock signal clk1,
• The second control logic LS2 is the second generator clock signal clk2,
• The third control logic LS2 is the third generator clock signal clk3, and
• The fourth control logic LS4 is the fourth generator clock signal clk4

connected.

One Output of the first delay element V1 is connected to a data input of the second delay element V2 whose output is connected to a data input D of the third delay element V3 and its output and the output of the second delay element V2 is connected to an input of a first AND logic & 1 respectively. Of the Output of the first AND logic & 1 is on an input of a logic table LT and its output a data input D of the fourth delay element V4 connected.

Of the Output of the fourth delay element V4 is both with another input of the logic table LT as also connected to the data input D of the fifth delay element V5. The output of the fifth delay element V5 is on an input of a second AND logic & 2 and the respective one Generator clock signal clk1..clk4 is on an inverting input the second AND logic & 2 guided. Another input of the logic table LT of the third control logic SL3 is with the output of the fifth Delay element - not presented - the second control logic SL2 connected. Analogous to this is in each case the Output of the fifth delay element V5 of the other control logics SL1, SL3, SL4 additionally with the logic table LT of the respective following control logics SL2, SL4, SL1, being over these connections each a logic control signal cen1..cen4 transmitted becomes. The exits A of the four control logics SL1..SL4 are routed to an OR logic 1, i. that at an exit A of the control logic SL1..SL4 applied generator signal clk1..clk4 is switched to the output of the OR logic 1 and provides the currently formed clock signal ts.

Then you can with a subunit, not shown, the clock frequency of the formed Clock signal ts be reduced. The reduction or an integer division ratio the clock frequency is advantageously close to the desired Clock frequency of a clock signal to be formed ts with reduced clock frequency selected. It can even with several dividers several clock signals with different Clock frequency are formed, wherein one of the clock signals to the Comparative unit VE is controlled.

As already stated, in 2 an embodiment of a control unit STE for extending the period of a clock signal to be formed ts, it being assumed that the four generator clock signals clk1..clk4 each have a phase shifted by 90 ° and the first generator clock signal clk1 a 0-phase, the second generator clock signal clk2 has a 90 ° phase, the third generator clock signal clk3 is assigned a 180 ° phase, and the fourth generator clock signal clk4 has a 270 ° phase. In 3 and 4 In each case the third generator clock signal clk3 of the third control logic SL3 is shown with a 180.degree. phase, wherein the same but different phase generator clock signals clk1..clk4 are used in the further control logics SL1, SL2, SL3. In each of the four control logics SL1..Sl4, the aid of the first three delay elements V1..V3 causes not every clock period of a generator clock signal clk1 .. clk4 an extension of the clock period takes place or therefore the control signal ctr delayed to the logic table LT is passed , where in the 2 and 3 the delayed control signal is indicated in the third control logic SL3 with ctr3. Furthermore, the three delay elements V1..V3 together with the first AND logic & 1 reduces the width of the pulses of the control signal ctr to one clock period and adapts it to the phase position of the respective generator clock signal clk1..clk4 and thus also the control signal ctr suppressed. The control signal ctr is also a clock signal, wherein, for example, indicated by the logic zero level, that in this period, no extension of the period of the clock signal to be formed ts to be performed and is indicated by a logical 1 level, that in this period, an extension of the Period of the clock signal to be formed ts to be performed - see 3 and 4 , In 3 is denoted by the designations t _n-1 , t _n , t _{n + 1} and t _{n + 1,} the timing by clock pulses with respect to the third Generatortaktakting clk3, wherein the level changes take place in each case with rising edge of a clock pulse.

For the exemplary embodiment, for explanation of the function of FIG 2 The control unit STE assumed that the second control logic SL2 a logic control signal cen2 is transmitted, which indicates by a logic 1 level that the current clock signal ts by clock pulses of the second generator clock signal clk2 is formed, however, forming the clock signal ts after two further clock pulses to be performed with the third generator signal clk3.

On the basis of the further information, which is controlled by the output of the fourth delay element V4 to an input of the logic table LT, the following table T results, which is realized in the logic table LT, wherein the control signal ctr is the control signal present at the logic table LT of the third control logic SL3 ctr3 and the output V4 indicates the output of the fourth delay element V4 and output V5 indicates the output of the fifth delay element V5. The designations t _n and t _{n + 1} indicate that the signals ctr3, cen2 and V4 are applied to the logic gate LT in an n-th clock period and the signal at the output of the fifth delay element occurs one clock period later.

Table T

The with <* determined Rows of the table are not possible according to the invention, since the logic control signals cen2, V4 must not occur simultaneously.

A logical 1 at the output of the fourth delay element V5 is delayed by the fifth delay Delayed V5 by one clock period, connected to the inverted input of the second AND logic & 2 to the OR logic 1. As a result, the third generator clock signal clk3 is passed to the output of the OR logic 1 and temporarily represents the clock signal ts.

Out From the table it can be seen that the third control logic SL3 only in two states its third generator clock signal clk3 turns on as a clock signal ts. In the first state, the second logic control signal cen2 and the third control signal ctr3 the logical 1, where by the third delayed Control signal ctr3 is displayed that an insertion or turning on the third generator clock signal clk3 by the third control logic SL3 should take place and indicated by the second logic control signal cen2 is that currently the second generator clock signal clk2 as the current Clock signal ts is switched and that with the next control signal ctr the third generator clock signal clk3 of the third control logic SL3 as is to switch the current clock signal. In the second case this shows third delayed Control signal ctr3 a logic 0 and the second logic control signal cen2 a logical 1, wherein by the third control signal ctr3 is displayed, which does not extend the clock period is to take place, but by the third logic control signal cen3 indicates that the third control logic SL3 is currently the third generator clock signal clk3 as clock signal ts supplies and also up to a logical 1 of the delayed, third control signal ctr3 delivers. This means that the third delayed control signal ctr3 is displayed, that the clock signal ts continues from the third Control logic SL3 is delivered.

These relationships apply equally to the first, second and fourth control logic SL1, SL2, SL4 and mean that provided an extension the period of the clock signal ts to be formed by that in the comparison unit VE formed control signal ctr is displayed, which is currently the Clock signal ts supplying control logic SL1..SL4 in order following control logic SL1..SL4 supplies the clock signal ts. The extension the period of the clock signal ts is caused by the generator clock signal clk1..clk4 one each at 90 ° to the current clock signal ts lagging phase and when turned on of the generator clock signal clk1..clk4 a period of the current clock signal ts extended by 90 °.

In 4 For example, it is assumed that the third control logic SL3 currently supplies its generator clock signal clk3 as a clock signal ts, but in the next control interval the delayed third control signal ctr3 passes through a logic 1 and the logic control signal cen2 of the second control logic SL2 a logical 0 indicates that the clock signal ts of the third control logic SL3 should be extended by one period and therefore the subsequent fourth control logic LS4 should deliver the clock signal ts. In this constellation, the output of the third generator clock signal clk3 is suppressed as a clock signal ts by controlling the second control logic signal cen2 to a logical 0, and thus the third generator clock signal clk3 is no longer connected as a clock signal ts. It should be noted that before the logic information changes, the third logic control signal cen3 of the following fourth control logic SL4 indicates that its generator clock signal clk4 is to be switched as a clock signal ts, causing a period of the clock signal ts to be extended by a 90 ° phase and thus the average frequency of the clock signal is reduced.

The previously described procedure can also for shortening the Periods of a clock signal to be formed ts be used, wherein for this, the logical table LT is to be extended by an input, wherein at this input and the control logic signal cen in the Order subsequent control logic SL is controlled. In addition is a delayed, entstörtes and with respect to its pulse width adapted control signal ctr to lead to another input of the logical table. By this delayed Control signal ctr is the clock control of the respective control logic SL indicated that a period of the clock signal are shortened should. In this case, the generator clock signal clk is not the following control logic SL but the previous control logic SL controlled as a clock signal ts, since this phase of the previous Generator clock signal clk lags and thus a period of the clocking signal shortened and hence the average clock frequency of the clock signal elevated becomes.

The Invention is not on the embodiment limited, but can be used in all situations where the Clock devices completely with minimal effort in integrated circuits such as ASIC or FPGA are to implement and several clock signals simultaneously must be formed, where the oscillator clock signal and the clock signals to be formed on the desired Clock frequencies are tuned. Also, with digital in the integrated Circuits also realizable PLL circuits more Clock signals are derived.

Claims (15)

Method for forming a clock signal (ts), In which a clock frequency information of the clock signal (ts) is compared with a predetermined clock frequency information and at least one control signal (ctr) is formed as a function of the comparison result, in which different generator phase clock signals (clk1..clk4) are formed from an oscillator clock signal, and - in which with the aid of the at least one control signal (ctr) and the at least each different phase positions having generator clock signals (clk1..clk4) the clock periods of the clock signal to be formed shortened, extended or not affected. Method according to claim 1, characterized in that that a formed clock signal, compared to the clock signal to be formed (ts) a higher one Clock frequency, before comparison with the clock frequency information is divided so integer that the clock frequency information of the divided clock signal the next lies to the predetermined clock frequency information. Method according to claim 1 or 2, characterized that shortening or extend a period of the clock signal (ts) to be formed thereby is that a generator clock signal (clk1..clk4) with a relation to the currently formed clock signal (ts) lagging or leading Phase position for the further formation of the clock signal (ts) is switched. Method according to one of the preceding claims, characterized in that with the help of in a control unit (STE) arranged control logic (SL1..SL4), in which by the respective Generator clock signals (clk1..clk4) clocked, serially geschal tete delay elements (V1..V3) are arranged, the control signal (ctr) is delayed, that with the help of inserted Controls (LT, & 1) and other delay elements (V4, V5) a logic control signal (cen1..cen4) formed and to a the neighboring control logic (SL1..SL4) is transmitted, and - that at a shortened by the control signal (ctr) a Period of the current clock signal (ts) by the logic control signal (cen1..cen4) of those neighboring control logic (SL1..SL4) the Outputting the generator clock signal (clk1..clk4) as the current clock signal (ts) is displayed, whose phase deviation is a shortening of a Period of the currently formed clock signal (ts) causes - that at an extension indicated by the control signal (ctr) a period of the current clock signal (ts) by the logic control signal (cen1..cen4) of those neighboring control logic (SL1..SL4) the Outputting the generator clock signal (clk1..clk4) as the current clock signal is displayed, whose phase deviation is an extension a period of the currently outputting clock signal causes - and that at a change indicated by the control signal (ctr) the period of the currently outputting clock signal (ts) by the Logic control signal (cen1..cen4) of the current control logic (SL1..SL4) is displayed is that by the generator clock signal (clk1..clk4) formed Clock signal is output as the current clock signal (ts). Method according to claim 4, characterized in that that the controls (LT, & 1) a logical table (LT), with a logical link at least a control logic individual control signal (ctr1..ctr4), at least a logic control signal (cen1..cen4) at least one of the other Control Logic (SL1..SL4) and at least one of the signals at the output the other delay elements (V4, V5). Method according to one of claims 1 to 5, characterized that at a clock frequency of the generator clock signals (clk1..clk4), the higher is the clock frequency of the clock signal to be formed (ts), extending one Period of the clock signal to be formed (ts) indicating control signal (ctr) is formed and the logic control signal formed (cen1..cen4) is controlled to the adjacent control logic (SL1..SL4), with the Generator clock signal (clk1..clk4) an extension of a period of the current Clock signal (ts) is effected. Method according to one of claims 1 to 5, characterized that at a clock frequency of the generator clock signals (clk1..clk4), which is lower than the clock frequency of the clock signal to be formed (ts) is a shortening a control signal indicative of a period to be formed clock signal (ts) (ctr) is formed and the logic control signal formed (cen1..cen4) is controlled to the adjacent control logic (SL1..SL4), with the Generator clock signal (clk1..clk4) a shortening of a period of the current Clock signal (ts) is effected. Method according to one of claims 1 to 5, characterized in that at a clock frequency of the generator clock signals (clk1..clk4), which is in the range of the clock frequency of the clock signal to be formed (ts), extending a period of the clock signal to be formed (ts) indicating control signal, (ctr) or a control signal (ctr) indicating the shortening of a period of the clock signal (ts) to be formed or no influence sen indicating control signal (CTR) is formed and the logic control signal formed (cen1..cen4) to the adjacent control logic (SL1..SL4) is controlled with the Gene ratortaktsignal (clk1..clk4) an extension or shortening of a period of the current Clock signal (ts) is effected. Method according to one of the preceding claims, characterized in that for the comparison of the clock frequency information of the clock signal (ts) with he predetermined clock frequency information, the clock pulses of the formed Clock signal (ts) counted periodically and the count result each with a stored, the predetermined clock frequency information representing meter reading is compared, and that depending on the comparison result at least control signal (ctr) is formed in such a way that the control unit in accordance with the information about shortening or extend or not affecting the formed clock signal (ts). Method according to claim 9, characterized in that that at the count the clock pulses of the clock signal (ts) on a lower clock frequency formed further clock signal is formed, wherein the periodicity of the count and the predetermined clock frequency information on the clock frequency of to tune another clock signal is. Method according to one of the preceding claims, characterized characterized in that from the clock signal by means of further PLL Functions more clock signals with respect to the clock frequency of the clock signal lower or higher Clock frequencies are formed. Clock device for forming a digital clock signal (Ts), - With a clock oscillator (PXO) and a clock unit (TE) for forming of different phasing generator clock signals (Clk1..clk4) - With a comparison unit (VE) for comparing the clock frequency information of the clock signal (ts) with a predetermined clock frequency information and for forming at least one control signal (ctr) in dependence on the comparison result, and - with a control unit (STE) between clock unit (TE) and comparison unit (VE) for shortening, extending or not influencing the clock periods of the clock signal to be formed (ts) with the aid of the at least one control signal (ctr) and the at least respectively different phase positions having generator clock signals (Clk1..clk4). Clock device according to claim 12, characterized in that a subunit for integrally dividing the formed clock signal (ts) before the comparison with the predetermined clock frequency information is provided in the way that the clock frequency information of the divided clock signal the next to the predetermined clock frequency information is, if the formed Clock signal across the clock signal to be formed (ts) has a higher clock frequency. Clock device according to claim 12 or 13, characterized in that in the control unit (STE) for each formed generator clock signal control logic (SL1..SL4) provided is, in which the respective generator clock signal (clk1..clk4) to the first of series connected delay elements (V1..V3) connected is that in each control logic (SL1..SL4) controls (LT, & 1) with such the delay elements (V1..V3) and additional delay elements (V4..V5) and the control unit (ctr) providing comparison unit (VE) are connected, that no change or a shortening or an extension a period of the current clock signal (ts) is effected, wherein the control signal (ctr) and a in the respective control logic (SL1..SL4) formed logic control signal (cen1..cen4) a the clock signal (ts) shortening in terms of its period or extending or no change causing control logic (SL1) is selected. Clock device according to one of claims 13 to 14, characterized in that the clock means in an integrated Circuit or custom or customer programmable Circuit is realized.