DE102005046371A1 - Digital to analog converter has data word, reference signal inputs, series resistance circuit, tapping for connection via switch to input with first and/or second resistances independently of data word, amplifier with gain setting input - Google Patents

Abstract

The device has an input (3) for the data word, a reference input (25) for a reference signal, a series circuit (2) with a first resistance and at least one second resistance, a tapping (6) for connection via a switch to the input with the first and/or second resistance independently of the data word and an amplifier (50) whose input is coupled to the tapping for a gain setting. An independent claim is also included for a method of digital to analog conversion of a data word.

Description

The The invention relates to a digital-to-analog converter. The invention relates Furthermore, a method for digital-to-analog conversion of a data word.

Digital to analog converter are used in a variety of applications to digital to generate controllable voltages. For example, like this Reference voltages of different strength depending on a digital data word provided become. Another application is in the conversion of digital present signals in purely analog signals, as for example for the Wired or wireless telecommunications necessary is.

such Digital-to-analog converters are almost always discrete-time clocked Operated systems. In this case, for example, in each clock period scanned the value-discrete data word and into a corresponding analog Signal changed. Due to the discreet change of a first Data word to a second data word, that is from a first output level to a second output level, repeat spectra arise in the Output signal of the converter. These are mainly at multiples the used clock frequency. This is why in very many applications the digital-to-analog converter a low-pass filter downstream.

The 7 to 9 show various embodiments of digital-to-analog converter known to the inventor. Specifically, the digital-to-analog converters are based on the 7 and 8th on voltage dividers. For example, the voltage divider 20 in the known embodiment in 6 between the connections 25 and 240 switched, the connection 25 a reference potential is supplied and the connection 240 is at the ground potential. This divides the voltage divider 20 in the form of series resistors 21a . 21b to 21e the voltage drop across the voltage divider in a certain divider ratio. At the taps 22a . 22b to 22e are each switch 23a provided, which are switched by an input supplied digital data word. The output is via a repeater 90 to an active low-pass filter 5 connected. In 8th a similar embodiment for differential signal processing is shown.

The voltage divider 20 . 20b from the known embodiments according to 7 and 8th should not be charged additionally, otherwise the output level will be falsified by the voltage division. On the other hand, the low pass filter 5 . 5b with their operational amplifiers 50 . 50b a relatively low input impedance. Therefore, usually a high-impedance repeater 90 arranged between the voltage divider and the downstream filter. This is designed for a corresponding load capacity.

9 shows a known embodiment of an R-2R digital-to-analog converter. In this case, a resistor chain of a plurality of resistors with the resistance values R and 2R is connected between the outputs of two reference operational amplifiers. Taps lead via further resistors with the resistance values 2R to the switches b1 to b4. The output side are connected to an output amplifier. In this illustrated embodiment, the three Operati onsverstärker be charged by the circuit shown with the voltage divider. The high load capacity and the additional necessary amplifiers increase the space requirement for the digital-to-analog converter.

task The present invention is to provide a digital-to-analog converter, which has a low Has space consumption. Another object of the invention is it, a simple method for digital-to-analog conversion of a digital Indicate signal.

These Tasks become with the objects the independent one claims 1, 16 and 18 solved. Further developments and embodiments of the invention are the subject the dependent claims.

Of the Invention is based on the principle by a change the series connection the digital-to-analog converter with the downstream Couple filters directly. As a result, no repeater or additional Buffer and output amplifier needed. Space and power consumption are reduced.

For this purpose, in one embodiment of the invention, a digital-to-analog converter has an input for supplying a data word and a reference input for a reference signal. A series circuit having a first resistor and at least one second resistor is coupled to the reference input via the first resistor. The digital-to-analog converter comprises a tap, which is connectable via a switching device depending on the data word at the input of the digital-to-analog converter to the first resistor and / or the at least one second resistor. Connected to the tap is an input of an amplifier for gain adjustment. According to the invention is thus for the digital Ana Log transformer no voltage divider longer provided, but the resistor chain is directly coupled to the input of the amplifier for gain adjustment. Thus, no voltage division in the series circuit is performed.

In another embodiment According to the invention, the digital-to-analog converter comprises an active low-pass filter with an entrance. The converter also has a series connection with at least two resistors on, their respective first connections to a reference input to the feeder a reference potential are connected. The second each connections the at least two resistors are each over one Switching device with the input of the active low pass filter switchable connected. As a result, the input is processed via the resistors Reference potential supplied.

In An embodiment of the invention is a first connection the series circuit connected to the reference input. A second Connection of the series connection is due to a floating potential. Thus, the series connection is no longer arranged between two potential terminals, as is the case in the prior art. In other words in an embodiment of the invention, the at least one second Resistor connected to a terminal connected to the first resistor. With a second terminal, the second resistor is only over the Switching device to the amplifier input to adjust the gain connected.

In In another embodiment, the first resistor and the at least one second resistor has the same resistance value on. This will be an approximate linear transfer characteristic a digital-to-analog conversion of a digital data word possible. In In another embodiment of the invention, the resistance values of first and the at least one second resistor different. This makes it possible to realize a digital-to-analog converter, the a non-linear characteristic with respect to the digital-to-analog conversion has. In one embodiment of the invention are the resistance values of the first and at least a second resistor chosen so that the transfer characteristic of the digital-to-analog converter corresponds to a pcm characteristic.

Again in another embodiment of the invention is the reference input for feeding a Reference signal connected to an output of a feedback operational amplifier. By this is provided with a reference potential at the reference input. In one embodiment of the invention, the amplifier forms a Part of the filter device and is in a training on the output side over a Feedback resistor connected to the entrance. Parallel to the feedback resistor can a Charge storage be arranged.

In Another embodiment is the digital-to-analog converter for differential signal processing executed. Thus, the series circuit in one embodiment comprises a first sub-series circuit and a second sub-series circuit. First and second sub-series circuits are each with a first connection to a first or connected to a second reference input for supplying a first reference signal or one with respect to the first reference signal inverted second reference signal. Each with a second Connection are the first and second part series circuit via a Switching device coupled to one of the inputs of the amplifier.

In In one embodiment, each of the sub-series circuits includes several resistors connected in series. Between the resistances is each provided a tap, which via a switching device with the one of the entrances of the amplifier is coupled.

In a development of this embodiment, the amplifier contains a Control input for a setting of a common mode level. This can be fed back to a buffer amplifier be connected.

It may be appropriate in one embodiment the resistance of the feedback resistor and at least one of the resistances of the Series connection equal to choose. Alternatively you can they have a different by a factor of 2 resistance value.

For the switching device It makes sense, this with field effect transistors or with transmission gates perform. The control connections the field effect transistors or the transmission gates are connected to the entrance to the feeder of the Data word coupled. Alternatively, the switching device can also be executed with mechanical or micromechanical switches.

For digital-to-analog conversion Accordingly, the data word to be converted and a reference potential are the first to be converted provided. Subsequently From this, a partial reference potential is generated as a function of the data word. This is done by reinforcing converted into an analogue signal.

In one embodiment, the partial reference potential is generated by providing a series connection with at least two resistors and supplying the reference potential to this series circuit. Subsequently, a Part reference potential at one point of the series connection tapped. The position is dependent on the data word, so that the partial reference potential varies depending on the tap point. This is then suitably reinforced in one embodiment.

in the The invention will be described below with reference to the drawing explained in detail.

It demonstrate:

1 a first embodiment of the invention,

2 a second embodiment for differential signal processing,

3 a section with field effect transistors as a switch,

4 a detail of the digital-to-analog converter according to the invention with transmission gates as a switch,

5 an embodiment of an operational amplifier,

6 an embodiment of an active low-pass filter,

7 a known digital-to-analog converter,

8th the known digital-to-analog converter for differential signal processing,

9 another known digital-to-analog converter.

The 7 and 8th show digital-to-analog converters in the so-called "single-ended" or differential form. Core of the known converter are a voltage divider chain 20 . 20b which between two supply potential connections 25 and 240 are connected. The voltage divider chains comprise a large number of equal individual resistors 21a to 21e , Between these resistors is a tap 22a to 22e provided to a switch 23a connected.

The digital-to-analog converter according to the 7 and 8th further comprise a low-pass filter 5a respectively 5b , as an active low pass with a differential amplifier 50 respectively 50b is executed. The inputs of the differential amplifier 50 . 50b the low-pass filter are low-resistance.

The resistance divider chain 20 . 20b should be at their taps 22 to 22e are not ohmic load, otherwise the output level is distorted by the voltage division and thus errors in the digital-to-analog conversion occur. Therefore, in the known embodiments according to the 6 and 7 high-impedance heavy-duty repeaters 90 . 90b intended. These are the output side via a resistor 51 with the low-impedance input of the differential amplifier 50 . 50b the low-pass filter connected. Your high-impedance inputs 93 are in turn connected to the divider chain. In the shown repeaters 90 . 90b During operation, the input nodes must correspond to the selected output level through the switch position of the switches 23a consequences. As a result, the input stage must operate linearly and with high gain throughout the range. In addition, the input capacitances of the repeaters must be reloaded via the resistor divider chain, so that the time constant of the resistance value of the resistors 21a to 21e and the input capacitance in the repeater 90 . 90a the speed of the entire circuit is limited.

Also in the in 9 shown known embodiment of an R-2R digital-to-analog converter, both the reference voltage V _REF and the reference voltage V _{B are} relatively low-impedance loaded with the resistors R. As a result, powerful high-power amplifiers must be provided.

1 shows the opposite principle, the basic principle of an embodiment of the digital-to-analog converter according to the invention. Thus, the known voltage divider is provided by a series connection of a number of resistors 21a to 21e to replace. The series connection 2 includes a first entrance 25 to which a reference potential is supplied. This is powered by an operational amplifier 30 provided, whose output with the connection 25 the series circuit is connected. The connection 25 is in addition to an input of the amplifier 30 recycled. A second input is supplied with the reference potential + V _REF .

Between the individual resistances 21a . 21b to 21c are each taps 22a . 22b to 22d intended. These are each to a switch 23a to 23d connected.

the last Stand 21e the series connection 2 is with a first connection to the tap 22d and the previous resistor and with a second connection 22e to the switch 23e connected. The respective second connections of the switch 23a to 23e are with the output tap 6 connected. This leads over a resistance 51 directly to the input of a differential amplifier of the low-pass filter 5 , This is the second terminal of the resistor 21e not on a fixed reference potential as in the known embodiments with a voltage divider. Rather, in the case of the digital-to-analog converter according to the invention, in each case a first connection of the resistors 21a . 21b to 21e coupled to the reference potential, a respective active second connection is directly to the relatively low-impedance input of the differential amplifier 50 created. As a result, in the invention, no voltage division is performed by means of a voltage divider chain, but there is a gain adjustment using the supplied via the resistors reference potential.

The low pass filter 5 includes next to the differential amplifier 50 one between the output of the amplifier 50 and the first input switched resistor 52 and a parallel arranged capacity 53 , A second input of the differential amplifier 50 is in this "single-ended" embodiment of the invention with the reference potential terminal 240 coupled. The output of the differential amplifier 50 at the same time forms the exit 4 of the digital-to-analog converter.

For digital-to-analog conversion of a digital data word D this is to the data input 3 created. Depending on the digital data word D then at least one of the switches 23a to 23e closed and the potential generated via the series connection at the tap 6 to the input of the differential amplifier 50 created. In this context, it may seem sensible if, in the case of a supplied data word D, not only the switch associated with the data word but also all subsequent switches are closed. Thus, the switches are also closed, which are connected to nodes in the series circuit below the associated switch. For example, if after feeding a data word at the input 3 the desk 23d closed, so it makes sense, even the switch 23e close. This basically has no effect on the gain settings, but can improve the impedance and switching performance.

In the embodiment according to 2 own the resistors 21a to 21e the same resistance values. They are called so-called unit elements. The feedback resistor 52 within the low-pass filter 5 also includes the resistance of one or two unit elements. For an implementation of a low-pass filter with a low corner frequency then a relatively large capacitance in the form of the parallel-connected capacitor 53 necessary. However, the unit resistances can be left here 21a to 21e interpret something higher impedance than in the known embodiments, because the input node of the differential amplifier 50 always at the reference potential and thus an input capacitance of the output amplifier 50 does not have to be reloaded. This allows a reduction in the capacitance of the capacitor and thus the space consumption.

Moreover, in this embodiment, it also offers, the resistance values of the resistors 21a to 21e different sizes to choose. In such a case, depending on the data word D, no linear conversion of the digital data word into an analog signal is generated, but a transfer characteristic dependent on the ratio of the resistance values is generated. In this way it is possible, for example, with a suitable choice of the resistance values of the series connection 2 to obtain a logarithmic transfer characteristic of the digital-to-analog converter. Likewise, a pcm characteristic is possible.

3 shows a section of the digital-to-analog converter according to the invention with the implementation of the switch 23a to 23e as field effect transistors. Effective or functionally identical components carry the same reference numerals. In this embodiment, the taps 22a . 22b and 22c with the terminals of field effect transistors 230 . 231 and 232 connected. The respective second terminals of the field effect transistors 230 . 231 and 232 are at the output tap 6 connected. The field effect transistors are designed for a higher switching speed than n-channel field effect transistors. Their control connections are at the entrance 3 connected to the supply of the data word.

The data word D itself comprises a series of individual bits, each of which can assume the logic states "0" or "1". Each of these bits within the data word D is one of the field effect transistors 230 to 232 assigned as a switch. Depending on the supplied data word, at least one of the switches is opened as a function of the bits, the others are closed.

A further improvement in the switching behavior is achieved with so-called transmission gates, as in a section of the digital-to-analog converter according to the invention in 4 are shown. The two transmission gates shown 260 and 250 each comprise two field effect transistors 242 . 243 respectively 252 . 253 , Each one of the field effect transistors 242 respectively 252 the two transmission gates is designed as a p-channel field effect transistor. The other transistor 243 . 253 the transmission gates 260 and 250 is called n-channel field effect transistor formed. The tap 21a is in each case connected to a first terminal of the field effect transistors 242 . 243 connected. The second tap 22b the series connection 2 is at the first terminal of the field effect transistors 252 and 253 connected. On the output side, the field effect transistors are in turn connected to the tap 6 connected. For driving the field effect transistors 243 and 253 the transmission gates 260 and 250 these are directly connected to the data input 3 connected. Furthermore, the inverters 241 and 251 provided, the input side are also connected to the data input for the respective transmission gate. On the output side, they are connected to the control terminal of the p-channel field-effect transistors 242 and 252 connected.

2 shows an embodiment of the digital-to-analog converter according to the invention for differential signal processing. In this embodiment, the series circuit comprises two sub-series circuits 2a and 2 B , These each contain a variety of resistors 21a . 21b respectively 29a . 29b , Each of the sub-series circuits is connected to a reference potential terminal with a first connection. Specifically, the first sub-series circuit 2a with the reference potential connection 25 connected. The second series connection 2 B is to the reference potential connection 24 connected. The two potential connections 25 and 24 In each case, a reference potential via the operational amplifier 30 and 30b provided. The reference potential at the connection is 24 regarding the reference potential at the terminal 25 inverted. This is achieved in the embodiment in that the operational amplifier 30b is supplied at its first input with respect to the reference potential + V _REF inverted reference potential -V _REF .

First and second terminals of each resistor of the sub-series circuits 2a and 2 B are over first switch 23a to 23c and 28a to 28c to the output tap 6a connected. Likewise, each of the terminals of the resistors 21a . 21b and 29a . 29b each with a switch 230a to 230c such as 280a to 280c with the second output tap 6b connected. The individual switches of the two sub-series circuits 2a and 2 B are in turn by a at the data input 3 applied data word activated and accordingly closed or opened. This will be at the output taps 6a and 6b generates a corresponding difference signal. In particular, the two operational amplifiers 30 and 30b not coupled with each other via the two sub-series circuits.

The output taps 6a and 6b are about the resistances 51 and 51b with the inputs of a differential amplifier 50b coupled. This in turn forms part of the low-pass filter 5b and at the same time an output amplifier for the analog voltage signal. Each output of the differential amplifier is via a resistor 52 respectively 52b returned to the respective input. Parallel to the two resistors 52 . 52b are the capacitors 53 . 53b arranged.

In addition, the differential amplifier includes 50b a control input for supplying a common mode potential. This is to a buffer amplifier 80 connected above it the common mode potential and thus the operating point of the amplifier 50b the low-pass filter 5b established.

Also in this embodiment is about the two sub-series circuits 2a . 2 B a gain setting of the amplifier 50b performed. Here are the resistance values of the individual resistors of the sub-series circuits 2a and 2 B always the same.

To provide the respective reference potential at the terminals 24 and 25 offer correspondingly robust operational amplifier. Such a so-called Miller operational amplifier is in 5 shown. The two inputs V _IN and V _{IN + of} the operational amplifier are connected to the control terminals of two p-channel field effect transistors M1 and M2, which form an internal differential amplifier. On the source side, these are connected to the supply connection V _SS with a current mirror made of the two transistors M3 and M4. On the sink side, the two transistors M1 and M2 are connected to the supply potential connection V _DD via a p-channel field effect transistor M7. The field effect transistor M7 is part of a current mirror chain with the current mirror transistor M8. The operating point of this transistor is set via the field effect transistor M9 whose control terminal is coupled to its drain terminal.

For independence of the gain setting from the resistive load, the output node between the transistors M2 and M4 is connected to the control terminal of the field effect transistor M6. This forms an inverter circuit together with the transistor M5. To correct the Miller effect, a correction capacitance C _{COMP is} provided between the output node and the drain terminal of the transistor M6. The output V _{OUT of} the operational amplifier is connected between the transistors M5 and M6 of the inverter circuit. To provide a reference potential is also, as already in the 1 and 2 represented, the output _tap V _OUT to the inverted input V _IN- returned.

6 shows an alternative embodiment of an active low-pass filter. It is designed as a second-order low-pass with single-feed, the Also referred to as "Sallen-Key" circuit. The positive feedback is via the capacitor C2, via the resistor 51c with the non-inverting input of the operational amplifier 50 connected is. The second terminal of the capacitor C2 is connected to the output of the low-pass filter and the operational amplifier. The voltage divider from the resistors 500 and 501 adjusts the internal gain and causes negative feedback. Between non-inverting input and the resistor 51c is another node with the second capacitor 502 connected with its second connection to the ground potential connection 503 is coupled.

at Accordingly, the invention does not involve digital-to-analog conversion more about a voltage division using a voltage divider chain, but over a gain adjustment a downstream differential amplifier, the advantageous also Part of the low pass filter can be. The supplied reference potential results This consists of a resistor chain with several switchable resistors. When Switches are suitable in addition to field effect transistors or transmission gates also micromechanical switches as well as other switches. Because of the Elimination of transhipment effects due to parasitic capacitances in the inputs of the difference amplifier higher ones Reach switching speeds.

Depending on the choice of feedback resistance Within the low-pass filter can be rauschärmere or faster Implement digital-to-analog converter. For further improvement Is it possible, a small amplifier with negative reinforcement to arrange at the output of the low pass filter. This allows the capacity of the used Feedback capacitor can be reduced, whereby a total of the space consumption of the converter according to the invention is reduced. The illustrated embodiments can be Naturally also combine. In addition to the operational amplifiers shown are also other arrangements possible, which provide a fixed reference potential. Likewise, others can be connect active circuits downstream of the tap of the series connection. The tapped off at the tap of the series connection potential can be directly for a gain setting use. That would leave also a gain adjustment a power amplifier, for example, in a transmitting or receiving arrangement control. Of the the series circuit downstream amplifier can also for a provision a further supply potential can be used.

2

series circuit

2a, 2 B

Part series circuit

3

data input

5

Low Pass Filter

6

tap

4

output

21a, 21b, ..., 21e

resistors

22a, 22b, ..., 22e

taps

23a, 23b, ..., 23e

switch

24 25

Reference potential connections

28a, ..., 28c

switch

29a, 29b

resistors

30 30b

operational amplifiers

50, 50b

differential amplifier

51 51b

resistors

52 52b

resistors

53 53b

capacitors

80

buffer amplifier

230 231, 232

FETs

230a, ..., 230c

switch

240

Ground potential terminal

241 251

inverter

242 252

p-channel field-effect transistors

243 253

n-channel field-effect transistors

250 260

Transmission gates

280a, ..., 280c

switch

M1, M2, ..., M8

transistors

C _COMP

capacitor

V _IN , V _{IN +}

input terminals

V _OUT

output port

V _SS , V _DD

supply connections

+ V _REF , -V _REF

reference potential

R

resistance

I _R

current value

V _B

reference potential

Claims (19)

Digital-to-analogue converter, comprising: - an input ( 3 ) for supplying a data word (D); - a reference input ( 24 . 25 ) for a reference signal; A series connection ( 2 . 2a . 2 B ) with a first resistor ( 21a . 29b ) and at least one second resistor ( 21b . 21e . 29a ), the first resistance ( 21a . 29b ) with the reference input ( 24 . 25 coupled; - a tap ( 6 . 6a . 6b ), which via a switching device ( 23a . 23b . 28a . 28b ) depending on the data word (D) at the input ( 3 ) with the first resistor ( 21a . 29b ) and / or the at least one second resistor ( 21b . 21e . 29a ) is connectable; - an amplifier ( 50 . 50b ) whose input with the tap ( 6 ) is coupled for gain adjustment. A digital-to-analog converter according to claim 1, wherein a first terminal of the series circuit ( 2 . 2a . 2 B ) with the reference input ( 24 . 25 ) and a second terminal is at a floating potential. Digital to analogue converter according to one of Claims 1 to 2, in which the at least one second resistor ( 21b . 21e . 29a ) with a connection to the first resistor ( 21a . 29b ) and with a second connection only to the switching device ( 23b . 23e ) connected. Digital to analogue converter according to one of Claims 1 to 3, in which the first resistor ( 21a . 29b ) and the at least one second resistor ( 21b . 21e . 29a ) have the same resistance value. Digital / analogue converter according to one of Claims 1 to 4, in which the reference input ( 24 . 25 ) with an output of a feedback operational amplifier ( 30 . 30b ) is connected to provide a reference potential. Digital-to-analogue converter according to one of Claims 1 to 5, in which the amplifier ( 50 . 50b ) a part of a filter device ( 5 . 5b ). Digital to analogue converter according to one of Claims 1 to 6, in which the input of the amplifier ( 50 ) a burden ( 51 ) and the amplifier ( 50 ) comprises a second input connected to a reference potential terminal ( 240 ) connected is. Digital-to-analog converter according to one of claims 1 to 7, the digital-to-analog converter is implemented for differential signal processing. Digital to analogue converter according to Claim 8, in which the series circuit ( 2 ) a first subseries circuit ( 2a ) and a second subseries circuit ( 2 B ), in which the first subseries circuit ( 2a ) with a first connection to the reference input ( 25 ) and to the second terminal via a first switching device ( 23a . 23b . 23c . 230a . 230b . 230c ) with the amplifier ( 50b ), in which the second sub-series circuit ( 2 B ) with a first connection to a second reference input ( 24 ) for supplying a reference signal inverted with respect to the reference signal and with a second connection via a second switching device ( 28a . 28b . 28c . 280a . 280b . 280c ) with the amplifier ( 50b ) is coupled. Digital to analogue converter according to one of Claims 8 to 9, in which the amplifier ( 50b ) comprises a control input for setting a common mode level which is applied to a feedback buffer amplifier ( 80 ) connected. Digital-to-analogue converter according to one of Claims 1 to 10, in which an output of the amplifier ( 50 . 50b ) via a feedback resistor ( 52 . 52b ) and a charge store arranged in parallel thereto ( 53 . 53b ) with the input of the amplifier ( 50 . 50b ) is coupled. Digital / analogue converter according to Claim 11, in which the feedback resistor ( 52 . 52b ) and at least one of the resistors ( 21a . 21b . 21e . 29a . 29b ) of the series circuit ( 2 . 2a . 2 B ) have the same resistance value or a resistance value different by a factor in the range of 1 to 3. Digital / analogue converter according to one of Claims 1 to 12, in which the reference input ( 24 . 25 ) with an output of an operational amplifier ( 30 . 30b ) whose first input is connected to a reference potential terminal and whose second input is connected to the output of the operational amplifier ( 30 . 30b ) is fed back. Digital / analogue converter according to one of Claims 1 to 13, in which the switching device ( 23a . 29b . 23b . 23e . 29a ) comprises at least two switches connected to field effect transistors ( 230 . 231 ) or with transmission gates ( 250 . 260 ) whose control connections to the input ( 3 ) are coupled to the data word. Digital to analogue converter according to one of Claims 1 to 14, in which the switching device ( 23a . 29b . 23b . 23e . 29a ) are formed with micromechanical switches. Digital-to-analogue converter, comprising: - an active low-pass filter ( 5 . 5b ) with an entrance; A series connection with at least two resistors ( 21a . 21b . 21e ), whose respective first connections to a reference input ( 25 ) are connected to supply a reference potential, the respective second terminals via a respective switching device ( 23a . 23b . 23e ) with the input of the active low-pass filter ( 5 . 5b ) are connected. A digital-to-analog converter according to claim 16, wherein the active low-pass filter ( 5 . 5b ) an amplifier ( 50 . 50b ) whose output is connected to the input via a feedback resistor ( 52 . 52b ) and a charge store arranged parallel thereto ( 53 . 53b ) connected is. Method for digital-to-analog conversion of a data word: - providing a data word (D); Providing a reference potential (+ V _REF , -V _REF ); Generating a partial reference potential as a function of the data word (D); - Generating an analog signal from the sub-reference potential by amplifying. The method of claim 18, wherein the step of generating comprises the steps of: providing a series connection with at least two resistors ( 21a . 21b . 21e ); - supplying the reference potential to the series circuit; - Picking up a partial reference potential at a position of the series connection, which is dependent on the data word (D).