DE102005037356B3 - Two coded input operand`s logic function evaluating circuit for safety-relevant application, has summoning circuit terminating memorizing when two dual rail signals have data values and coding signal has coding values - Google Patents

Abstract

The circuit has a logic circuit determining coded output values based on logic function from data values of two inputs and coding values and outputting the output values in a computation cycle. A summoning circuit (102) memorizes summoning values in an output if the summoning values are detected at the output or terminates the memorizing when two dual rail signals have data values and a dual rail coding signal has coding values. An independent claim is also included for a method of evaluating a logic function of a two coded input operand.

Description

The The present invention relates to a circuit and a Method for calculating a logic operation of two input operands, especially for safety-relevant applications can be used.

circuits used to process security-related data, be possible designed to protect the data being processed from attackers, try by analyzing the circuit to the safety-relevant To get data. Due to SPA / DPA attacks (SPA / DPA; SPA / DPA = Simple Power Attack / Differential Power Attack) is for high security applications necessary, the power consumption of an integrated circuit, regardless of to design the processed data.

These Problem can be solved by a dynamic dual-rail circuit technology, however, their design, characterization and verification are time consuming is. A based on the dynamic dual-rail circuit technology Library is due to, for a precharge state between the data states, required precharge Signals not synthesizable and for static timing analysis not suitable.

A static implementation of a circuit arrangement for processing two dual-rail signals is in the patent DE 103 44 647 B3 described. In this case, the dual rail signals have precharge signals with precharge values between valid data values. Valid data values are characterized in that in each case mutually inverted logical states on both individual signals of the dual-rail signal. Precharging values are characterized by the fact that identical logic states prevail on the two signals of a dual rail signal. According to the patent, the precharging values applied to the inputs of the circuit arrangement are passed through to an output of the circuit arrangement.

The said patent does not deal with encrypted Signals.

at The technology "masking" becomes internal signals encrypted by a mask. Special, new logic cells are used in the Location are masked input signals A and B and a mask M also encrypted Output signal Z to produce.

14 shows a block diagram of such a logic cell with the masked inputs A, B, an input for the mask M and an output for outputting the encrypted output signal Z.

The underlying masking is based on the 15a and 15b described.

15a shows a value table for an XOR operation. The signals A, B, Z are not encrypted. The table of values for the XOR2 operation is based on the function equation A xor B = Z.

15b shows a table of values of an XOR operation for masked signals AM, BM, ZM, using the mask M. The encryption or masking is an XOR combination of the signals AM, BM, ZM with the value of the mask M. Thus, AM = A XOR M; BM = B XOR M; ZM = Z XOR M. The table of values of the masked XOR2 link shown is based on the function equation ((AM xor M) xor (BM xor M)) xor M = ZM.

Out the writing "Side-Channel Leakage of Masked CMOS Gates; Stefan Mangard, Thomas Popp, Berndt M. Gammel "is known that in a single-rail implementation of the masked circuit technology any glitches, so glitches make the logic vulnerable.

One possibility for secure encryption of masked signals is a masked dual-rail precharge logic. As with unencrypted dual-rail, the signals encrypted with the mask M and also the mask itself are executed twice. So there are two dual-rail input signals A, AN and B, BN and a dual-rail mask M, MN. Furthermore, an idle phase between two valid value sequences is introduced. The idle phase is a precharge state, also called "precharge", between two evaluation phases, also referred to below as calculation cycles, resulting in an alternating sequence of the two states, as with unencrypted dual rail:
Evaluate → Idle → Evaluate → Idle → Evaluate → Idle → Evaluate ...

The following effect is exploited:
When transitioning from an idle state to a valid value in the Evaluate phase, only rising edges can occur:
(0/0 → (1/0)
(0/0 → (0/1)

It goes by definition at this transitional stage no physical signal from high to low.

The same applies to the transition of a valid value to an idle state.
(1/0 → (0/0)
(0/1 → (0/0)

A table of values for an XOR operation according to such a masked dual-rail technique is shown in FIG 15c shown. According to this value table, the outputs ZM, ZM_N are at undefined values as soon as one of the input signals AM, AM_N, BM, BM_N, M, M_N goes into the idle state. If all input signals are in the idle state, the output signal ZM, ZM_N also goes into the idle state.

It It has been proven that due to glitches in each CMOS circuit occur, a masked dual-rail circuit anyway is vulnerable.

Especially can at a transition from a calculation cycle, ie a cycle with valid data values at the entrances, in a precharge cycle, ie a cycle in the precharge values at the inputs applied, or in a reverse transition glitches occur.

This is especially the case when transitioning from the calculation cycle in the precharge cycle at an input signal already the precharge however, there is still a valid data value at the other input signal is applied. In this case, a precharge value may already be available at the output or even a data value is output. It is also not excluded in the transition in the meantime several different data values are output at the output before Finally, preload values are output at the output. The same Problem occurs at the transition from precharge cycle to the calculation cycle. Is at one the inputs already a valid one Data value, but at the other input still a preload value, so it is again open, whether at the exit already a valid data value, changing data values or even a preload value is present. These uncertainties can to interference pulses lead and provide a point of attack for latest attack scenarios where by a higher temporal resolution of the Power consumption of a circuit is trying different To detect switching times and then the current curve accordingly to rate.

US 2002/0101262 A1 shows a logic circuit for calculating a result operand from input operands. The circuit has corresponding inputs and outputs for receiving the input operands and for outputting the result operand on. In addition, the circuit has a first logic stage and a second Logic level with corresponding intermediate nodes. The result operand takes a "hold value" as soon as one the input operand assumes this "hold value".

It The object of the present invention is a circuit and a Method for calculating a logical connection of encrypted To create input operands that secure processing of Enable operands.

These The object is achieved by a circuit according to claim 1 and a method according to claim 14 solved.

The present invention provides a circuit for calculating a logical operation of two input operands, comprising:
a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle;
a second input for receiving a second dual-rail signal, which in the calculation cycle Da having values of the second input and precharge values in the precharge cycle;
a third input for receiving a dual rail encryption signal having encryption values in the calculation cycle and precharge values in the precharge cycle;
an output for outputting an encrypted dual rail result signal having result values encrypted in the calculation cycle and precharge values in the precharge cycle;
wherein the data values of the first and second dual-rail signals and the encrypted result values of the dual-rail result signal are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule;
a logic circuit for determining the encrypted result values according to the logical combination of the data values of the first input and the second input and the encryption values, and for outputting the encrypted result values in the calculation cycle at the output; and
a precharge circuit, which is designed to already impress precharge values in the output when precharge values are detected at a single input, or which is designed to terminate an impressing of the precharge values only when the first dual rail signal and the second dual rail signal data values and the encryption signal comprises encryption values.

The present invention further provides a method for calculating a logical operation of two input operands, comprising the steps of:
Receiving a first dual rail signal at a first input having data values of the first input in a calculation cycle and precharge values in a precharge cycle;
Receiving a second dual rail signal at a second input having data values of the second input in the calculation cycle and precharge values in the precharge cycle;
Receiving a dual rail encryption signal having encryption values in the calculation cycle and precharge values in the precharge cycle;
Determining encrypted result values according to the logical combination of the data values of the first input and the second input and the encryption values and outputting the encrypted result values in the calculation cycle at an output for outputting a dual rail result signal containing the encrypted result values in the calculation cycle and having precharge values in the precharge cycle;
wherein the data values of the first and second dual-rail signals and the result values of the third dual-rail signal are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule;
Imposing pre-charge values at the output already when precharge values are detected at a single input, or terminating the memorization of the precharge values only when the first and second dual-rail signals have data values and the dual-rail encryption signal has encryption values.

Of the inventive approach extends the value tables according to the state the technique to the case that once any dual-rail input pair Vorladewerte also has the gate output preload values. Conversely, the extension also means that the dual-rail output pair only then leaves the precharge state, if there is no input more in pre-charge state.

By Application of these extensions becomes the current waveform to be measured substantially harmonized between different input changes.

In addition, so-called "do not care" states occur the input side of such a value table according to the invention for simplicity the circuit according to the invention. In the "do not care" states they are states, in which at least one of the input signal has precharge values. In In this case, the rest Input signals disregarded, since on the output, regardless of the other input signals, preload values are impressed.

Of the inventive approach allows Gate implementations, which are driven at any time. That is, there is no dynamic Condition before. Thus, a library is based on these gate implementations based, suitable for the synthesis of a circuit.

The proposed circuitry prevents a timing a change the starting date of each time of change depends on the input data. Furthermore, hazards, ie parasitics or glitches, ie glitches while switchover avoided. This prevents when measuring the current flow Conclusions on the processed data succeed.

The present invention is based on the finding that the transition from a Be Calculation cycle, also called Evaluate, in a pre-charge cycle, also called idle, happens as soon as the first input signal goes into the pre-charge state. Furthermore, a transition from the precharge cycle into the calculation cycle must not occur until the last input signal has also gone into the calculation state. Even if there were no further functional changes, the output signal must not change at an early stage.

Consequently becomes the output change, triggered by the last input and the observability is further reduced as an early one Change data-dependent would.

preferred embodiments The present invention will be described below with reference to FIGS enclosed drawings closer explained. Show it:

1 a schematic representation of a circuit according to an embodiment of the present invention;

2 a timing chart of calculation cycles and precharge cycles according to an embodiment of the present invention;

3 a schematic representation of a circuit according to another embodiment of the present invention;

4 Value table of a logical operation according to an embodiment of the present invention;

5 and 6 Schematics of Vorladeschaltungen according to embodiments of the present invention;

7 to 13 Circuit diagrams of logic circuits according to embodiments of the present invention;

14 Block diagram of a used for masking logic cell according to the prior art;

15a -b value tables according to the prior art; and

15c Value table with a basic logic function realized by value tables according to the invention.

In the following description of the preferred embodiments of the present invention are for those in the various Drawings shown and similar acting elements have the same or similar reference numerals, omitting a repeated description of these elements becomes.

1 shows a circuit for calculating a logical operation of two encrypted input operands according to an embodiment of the present invention. The circuit is executed in dual rail circuit technology. In this case, each bit transmitted on a dual-rail line is represented by two nodes, each bit having a valid logical value if the first of the two nodes corresponds to the true logical value of that bit and the second of the two nodes is inverted thereto Value. Such valid logical values are referred to below as data values. Between two data values with valid logical values of 1.0 or 0.1, a so-called pre-charge state is inserted, in which case both nodes of the dual-rail line are charged to the same electrical potential and assume logically invalid values 1, 1 or 0.0 Such logically invalid values are referred to below as preload values In the following embodiments, the preload values are assumed to be 0, 0. In this case, the states 1, 1 are not allowed Alternatively, the precharge values can also be assumed to be the states 0.0, in which case the states 1.1 are not allowed.Calculation cycles in which valid data values are applied to the circuit alternate with precharge cycles in which invalid logic values are in the form If there are precharge values at one input of the circuit, they will be applied to the output of the circuit ng, without requiring an additional clock signal or precharge signal is derlich. According to the present invention, precharge values are output at the output of the circuit as soon as precharge values are applied to at least one input of the circuit. This corresponds to the transition from a calculation cycle in which valid data values are present at the input of the circuit to the precharge cycle by applying precharge values to the input of the circuit. During the transition from the precharge cycle into the calculation cycle, precharge values are output at the output of the circuit until no precharge values are applied to all inputs of the circuit.

In the 1 The circuit shown is based on the masked dual-rail precharge logic and operates with masked input signals as well as with a masked output signal. For this purpose, the circuit receives a mask with which both the input signals and the output signal to be output are masked.

In the 1 The circuit shown has a precharge circuit 102 and a logic circuit 104 on. The circuit has a first input for receiving a first dual-rail signal AM, AMN and a second input for receiving the dual-rail signal BM, BMN. Furthermore, the circuit has a third input for receiving a dual-rail Vignale signal M, MN. The dual-rail signals AM, AMN, BM, BMN have the calculation cycle data values and precharging values in the precharge cycle. This means that, for example, in the calculation cycle, a 0 is present on the signal AM and a 1 is present on the signal AMN or a 0 on the signal AM and a 0 on the signal AMN. In the precharge cycle, a 0 or a 1 is applied to the signals AM, AMN. The encryption signal has encryption values in the calculation cycle and precharge values in the precharge cycle. The circuit also has an output for outputting a dual-rail signal ZM, ZMN. The dual rail output as well as the dual rail inputs have data values in the calculation cycle and precharge values in the precharge cycle. The encryption signal M, MN contains the mask with which the input signals AM, AMN and BM, BMN are encrypted and with which the output signal ZM, ZMN is encrypted. The dual rail signals AM, AMN, BM, BMN, M, MN are both the precharge circuit 102 as well as the logic circuit 104 fed.

The logic circuit 104 is designed to perform a logical combination of the values applied to the dual-rail signals AM, AMN, BM, BMN. In this case, the encryption values which are present on the encryption signal M, MN are taken into account. The logical connection is made in one go, ie the input signals AM, AMN, BM, BMN are not first decrypted and then logically linked, but the logic operation is based on the encrypted input signals AM, AMN, BM, BMN taking into account the Mask M, MN performed. Likewise, an encryption of the output signal ZM, ZMN is not performed in a subsequent encryption step, but is performed directly in the logical combination of the encrypted input signals AM, AMN, BM, BMN, taking into account the mask M, MN. The result of the logic operation is provided by the logic circuit 104 placed on the output of the circuit and is output from the dual rail output signal ZM, ZMN in the calculation cycle.

The precharge circuit 102 is designed to ensure that the calculation cycle of the dual-rail output signal ZM, ZMN, in which the result values of the logic circuit 104 only when none of the input signals AM, AMN, BM, BMN, M, MN has more precharge values, or when all of the input signals AM, AMN, BM, BMN, M, MN have valid data values or encryption values , As long as precharging values are still present at one of the input signals AM, AMN, BM, BMN, M, MN and are detected at the input of the circuit, the precharge circuit impresses 102 on the output signal ZM, ZMN preload values.

2 illustrates a transition from the calculation cycle to the precharge cycle and from the precharge cycle to another calculation cycle. In the calculation cycle valid values are applied to the input signals AM / AMN, BM / BMN, M / MN and to the output signal ZM / ZMN 2 are denoted by A ₁ , B ₁ , M ₁ and Z ₁ . The signals AM, BM, M, ZM have a logic state 0 or 1 and the associated dual-rail signals AMN, BMN, MN, ZMN have the logic state inverted thereto. During the transition from the calculation cycle to the precharge cycle, all signals AM, AMN, BM, BMN, ZM, ZMN assume the same logical value, here logical 0.

The approach according to the invention ensures that the output signal ZM, ZMN has a precharge value, here logical 0, as soon as the first input signal, in this case the input signal AM, AMN assumes the precharge value. This is done by the in 1 shown precharge circuit 102 guaranteed. Without this precharge circuit 102 At the output ZM, ZMN, data values may still be present as long as the second input signal BM, BMN or the encryption signal M, MN has valid data values. Further, it could be during this period without the precharge circuit 102 to undefined states and glitches come. The precharge circuit 102 prevents such undefined states on the output signal ZM, ZMN, which could lead to glitches or a multiple switching of the output signal ZM, ZMN. During the transition from the precharge cycle to the calculation cycle, the precharge circuit is set 102 It is also certain that the output signal ZM, ZMN has precharge values as long as precharge values are still applied to at least one of the input signals. In this case, this means that the output signal ZM, ZMN assumes valid data values only when the input signals AM, AMN, BM, BMN and the encryption signal M, MN have accepted valid data values. The precharge circuit 102 thus prevent the output from changing in advance when individual input values arrive, even if the logical function would permit this. The output change is only executed when all input values have changed from the pre-charge state to the evaluated state.

3 shows another block diagram of a circuit for calculating a logical operation of two encrypted input operands according to the present invention. The circuit according to the invention again has a precharge circuit 102 and a logic circuit 104 which are both designed to receive the masked dual-rail signals AM, AMN and BM, BMN and the dual-rail encryption signal M, MN. The precharge circuit 102 as well as the logic circuit 104 are connected on the output side to a dual rail intermediate node ZM_INT, ZMN_INT. Furthermore, the circuit has an inverter pair 106a . 106b on, which are connected between the output of the circuit and the intermediate node. The first inverter 106a is configured to invert a logic state of the first node ZMN_INT of the intermediate node and output as an output signal ZMN at the output of the circuit. The second inverter 106b is configured to invert a logic state of the second node ZM_INT of the intermediate node and output as an output signal ZM at the output of the circuit. The not yet inverted output signals at the intermediate node ZM_INT, ZMN_INT are already encoded with the mask M, MN.

In this embodiment becomes a logical first state 1 physically by a high voltage potential VDD and a second logic state 0 by a low voltage potential VSS realized.

The precharge circuit 102 is realized as a pull-up network, which impresses on the intermediate node ZM_INT, ZMN_INT, depending on the input signals AM, AMN, BM, BMN, M, MN, the high voltage potential VDD. This is the Vorladeschaltung 102 connected to a first, high potential terminal VDD.

The logic circuit 104 is realized in this embodiment as a pull-down network, which is designed to pull the intermediate node ZM_INT, ZMN_INT, depending on the input signals AM, AMN, BM, BMN, M, MN to the low electrical potential. This is the logic circuit 104 to a second, low potential terminal, in this case a ground terminal VSS.

In the logic circuit 104 it may be, for example, a logic circuit which performs a logical XOR operation on the encrypted operands transmitted via the input signals AM, AMN, BM, BMN.

4 shows a lookup table that underlies such an XOR link.

According to the inventive approach, the in 15c shown value table in the first three lines expanded. Accordingly, the output signals ZM, ZMN are in the precharge state or idle state when precharge values are applied to at least one of the input signals AM, AMN, BM, BMN, M, MN. It is therefore sufficient that in each case a logical 0 is applied to the input signals AM, AMN in order to also output a 0 on the output signals ZM, ZMN. The logical state of the signals BM, BMN, M, MN is not considered. This is indicated in the value table in that do not care (-) is entered for the signals BM, BMN, M, MN. Do not care and stands for a logical 0 or logical 1, whereby the combination logical 1, logical 1 is forbidden for an input pair. Correspondingly, precharging values are already output at the output ZM, ZMN when the second input signal BM, BMN is in the precharge state, regardless of whether data values or precharge values are applied to the first input signal AM, or if encryption values or precharge values are applied to the encryption signal M, MN , The same applies to the encryption signal M, MN. If precharge values are present on the encryption signal M, MN, then precharging values are output at the output signal ZM, ZM_N, regardless of whether data values or precharge values are applied to the input signals AM, AM_N or BM, BM_N.

By specializing the output values at 0/0 instead of dc / dc at idle inputs, ie at input signals having precharge values, the circuit according to the invention becomes larger, but the Um Switching time is always the same regardless of the input data.

The Gates can be implemented so that the pull-up network only the Precharge state coded and thus independent of the implementation Function is. The cells can therefore half again be used.

In addition, the "do not gares" on the input page the table of values for a standardization of the pull-up network, this means, that for all logic functions the pull-up network is the same and therefore can be used again.

The However, the pull-down network has to be extended to the extent that Only one maximum path is activated continuously. With that floating states and short circuits avoided.

Of the inventive approach was explained here by way of example on a value table for an XOR2 function. Appropriate Tables of values can also be used for other logical functions put up.

5 shows a detailed circuit diagram of a precharge circuit 102 , as for example for the basis of 3 described embodiment can be used. The precharge circuit 102 is a transistor circuit that implements a pull-up network. Depending on the dual-rail input signals AM, AMN, BM, BMN, M, MN pulls the Vorladeschaltung 102 the nodes of the dual rail intermediate node ZM_INT, ZMN_INT to the high voltage potential VDD. If at one of the input signals AM, AMN or BM, BMN or M, MN precharge values, in this case a low voltage potential, for example on the signal AM and the signal AMN, the precharge circuit switches 102 the high voltage potential of the potential terminal VDD on both nodes of the intermediate node ZM_INT, ZMN_INT by. For this purpose, the precharge circuit 102 comparators 510a . 510b . 510c configured to pass through the high voltage potential VDD to the intermediate node ZM_INT, ZMN_INT when precharge values are applied to one of the dual rail input signals AM, AMN, BM, BMN, M, MN. A comparison device, for example the comparison device 510a has two series-connected transistors according to this embodiment. The source terminal of the first transistor is connected to the high voltage potential VDD and the drain terminal of the second transistor is connected to the intermediate node ZM_INT or ZMN_INT. The gate terminal of the first transistor is driven by the signal AMN of the first dual rail input signal AM, AMN and the gate terminal of the second transistor by the signal AM of the dual rail input signal AM, AMN. The transistors are p-type transistors. Both transistors thus switch through when the low voltage potential is present at both gate terminals. If a high voltage potential is present at one of the gate terminals, as is the case when a valid data value is applied to the input signal AM, AMN, then the comparator blocks 510a , The second comparison device 510b is the first comparator 510a connected in parallel and is driven by the second dual rail input signal BM, BMN. Accordingly, the third comparison device 510c to the first and second comparison means 510a , b connected in parallel and is driven by the dual-rail encryption signal M, MN. The comparison devices 510a . 510b . 510c are each executed twice in order to control both intermediate nodes ZM_INT, ZMN_INT.

If a valid data value or encryption value is present at the input signals AM, AMN, BM, BMN and the encryption signal M, MN, then the comparison devices block 510a . 510b . 510c , However, in order to apply a valid data value on the intermediate node ZM_INT, ZMN_INT, it is necessary for a node of the intermediate node ZM_INT, ZMN_INT to be connected to the high voltage potential VDD. For this purpose, the precharge circuit 102 a holding member 512 on, which consists of two transistors which are connected at their source inputs to the high voltage potential VDD and at its drain outputs to the node ZMN_INT and the node ZM_INT of the intermediate node. The gate terminals are each driven by the other node of the intermediate node ZMN_INT, ZM_INT, as the node to which the drain terminal of the respective transistor is connected. The transistors are also p-type transistors. The holding member 512 ensures that one of the nodes of the intermediate node ZM_INT, ZMN_INT is held at the high voltage potential VDD as soon as the other node through the logic circuit 104 is pulled to a low voltage potential VSS.

6 shows another precharge circuit 102 for a circuit according to the invention with three inputs for the signals AM, AMN, BM, BMN, CM, CMN and an encryption input for the signal M, MN. Unlike the in 5 the precharge circuit shown in FIG 6 shown precharge circuit 102 depending on a further comparison device, which ensures that the intermediate node ZM_INT, ZMN_INT is connected to the high voltage potential VDD, as soon as at the third input signal CM, CMN Vorla values lie.

The 7 to 13 show embodiments of logic circuits 104 as for the in 3 described embodiment can be used. Here are the in 7 and 8th described logic circuits for linking two encrypted input signals taking into account the encryption signal and in the 9 to 13 shown logic circuits 104 designed to link three input signals taking into account the encryption signal. Accordingly, the in 7 and 8th shown logic circuits 104 together with the in 5 shown precharge circuit 102 and those in the 9 to 13 shown logic circuits 104 with the in 6 shown precharge circuit 102 be used. In the 7 to 13 shown logic circuits 104 are realized as transistor circuits that implement a pull-down network. It uses N-type transistors. The logic circuits 104 are connected between a second potential terminal with a ground potential GND or VSS and the intermediate node ZM_INT, ZMN_INT. The gate connections in the in the 5 - 13 shown logic circuits 104 , as well as in the precharge circuits 102 used transistors are driven by the input signals AM, AMN, BM, BMN and the other input signals in circuits for three or more input signals, taking into account the encryption signal M, MN. According to, in the 5 - 13 The embodiments shown are the precharge circuits 102 and the logic circuits 104 designed as independent circuits that have no common transistors.

The in the 7 to 13 shown logic circuits 104 are designed to interrupt a connection between the low potential terminal GND and the intermediate nodes ZM_INT, ZMN_INT as soon as at least one of the input signals AM, AMN, BM, BMN, M, MN present precharge values. However, if valid data values are present at all input signals AM, AMN, BM, BMN, M, MN, then the logic circuits shown are 104 designed to connect one of the nodes of the intermediate node ZM_INT, ZMN_INT to the low voltage potential GND in accordance with the logic operation to be implemented, and thus to output a valid data value.

7 shows a logic circuit 104 in the form of a transistor circuit for realizing an AND operation. The transistor circuit 104 has Endladetransistoren 720 which are used both to unload the node ZM_INT and to unload the node ZMN_INT. The drain terminals of the two transistors 720 are connected. Such common transistors 720 be in the other embodiments of the 8th to 13 used to reduce the required transistor count.

To realize the AND operation, three transistors are connected in series between the node ZMN_INT and the potential connection GND, the gates of which are controlled by the signals M, AMN and BMN. In parallel, a further transistor circuit is arranged, with a first transistor whose drain terminal is connected to the node ZMN_INT and whose gate terminal is connected to the signal MN. The source terminal of this transistor is connected via a first or a second transistor series circuit to the ground potential GND. The first series circuit consists of two transistors whose gate terminals are connected to the signal AM or BMN. The second series circuit consists of two transistors whose gate terminals are connected to the signal AMN and the signal BM, respectively. The drain terminals of the two transistors 720 are connected. The transistor circuit connected to the node ZMN_INT corresponds to the transistor circuit which is connected to the node ZM_INT, with the difference that the gate terminals of the respective transistors are connected to the respectively inverted signal of the dual rail signals.

8th shows a logic circuit 104 according to a further embodiment, which implements a logical XOR combination of second input signals AM, AMN, BM, BMN taking into account the encryption signal M, MN.

The intermediate node ZMN_INT is connected to the ground potential GND via a series circuit of three transistors whose gate terminals are driven by the signal M, BM, AMN. The drain terminal of the transistor M controlled by the signal M is connected to the source terminal of a further transistor, which is driven by the signal BMN whose drain terminal is in turn connected to the source terminal of a transistor which is connected to the signal AM is driven, wherein its drain terminal is connected to the node ZMN_INT. A corresponding circuit is arranged between the node ZM_INT and the ground potential GND, wherein the corresponding transistors are in turn driven by the respectively inverted signals. Furthermore, there is a connection between the source terminals of the corresponding transistors which are connected directly to the intermediate nodes ZMN_INT, ZM_INT are connected.

9 shows a further embodiment of a logic circuit 104 , which is designed to perform an AND operation between three input signals AM, AMN, BM, BMN, CM, CMN in consideration of the encryption signal M, MN.

10 shows a logic circuit 104 of a further embodiment, which perform a logical AND-OR operation between three input signals AM, AMN, BM, BMN, CM, CMN taking into account the encryption signal M, MN.

11 shows a further embodiment of a logic circuit 104 configured to perform a logical XOR operation between three input signals AM, AMN, BM, BMN, CM, CMN in consideration of the encryption signal M, MN.

12 shows a further embodiment of a logic circuit 104 , which is designed to perform a multiplexer connection between two input signals AM, AMN, BM, BMN and a select signal SEL, SELN taking into account the encryption signal M, MN.

13 shows another embodiment of a logic link 104 adapted to perform a majority association between three input signals AM, AMN, BM, BMN, CM, CMN in consideration of the encryption signal M, MN.

The exact connection of the in the 5 to 13 used transistors can be seen from the corresponding figures.

The in the 5 to 13 shown circuits 102 . 104 can be used for the inventive circuit, as shown in block diagram in 3 is shown used. These are the in 3 shown inverter used to invert a logic state of the intermediate nodes ZM_INT, ZMN_INT and output at the output as a result signal ZM, ZMN.

All gates in a Libray based on this embodiment have the same structure, which is divided into three groups. A pull-down network 104 implements the logic functionality. A pull-up network 102 implements the precharge functionality, ie precharging the output signals. The pull-up network is the same for all gates with the same number of inputs. The third group are the two output inverters.

By the pull-up network is always pre-charged, as long as is at least one input in the pre-charge state.

By the pull-down network is used in the evaluation case, ie the calculation cycle, only unload either the ZMN_INT node or or ZM_INT node. The pull-down networks are designed to be a maximum of only one Path to the low voltage potential, so switched to VSS is, otherwise different discharge currents at different input combinations flow would.

The networks for discharging the nodes ZMN_INT and ZM_INT can, if the function permits, use in part the same transistors, for example the in 8th shown pull-down network 104 to implement an XOR functionality, the two transistors whose source terminal is connected to the ground potential.

Thereby that in the dual-rail circuit techniques in the evaluation state always differential values can be assumed 1/0 or 0/1, can by exchanging the two output lines ZM, ZMN a logical Inversion of the gate can be achieved. Will continue too still the input pairs AM, AMN and BM, BMN reversed, can with two different pull-down networks all possible Logic functions with two inputs be imaged. For The illustration of all logic functions with three inputs only five Structures needed.

In addition will every time the mask dual rail input is needed. Thus, the corresponding pull-up Networks each with an additional P-path added, whose gates are connected to the signals "M" and "MN".

features with several inputs can be realized accordingly.

The in the 5 - 13 shown transistor circuits are exemplary and can be replaced by circuits with the same functionality. The inventive approach can be extended to circuits with four or more inputs for receiving additional dual-rail signals. Likewise, the present invention is not limited to the transistor logic shown. The logical operations may be, for example, an AND, NAND, OR, NOR, XOR, NXOR, ANDOR, ORRND, multiplexor or majority function. The encryption policy can be an XOR or an NXOR.

102

precharge circuit

104

logic circuit

106a, 106b

inverter pair

510a, 510b, 510c

comparators

512

retaining member

720

discharging

AT THE, AMN

first Dual-rail signal

BM, BMN

second Dual-rail signal

ZM, ZMN

Dual-rail result signal

CM, CMN

additional Dual-rail signal

M, MN

encryption signal

ZMN_INT, ZM_INT

Dual-rail intermediate node

VDD

first potential terminal

VSS, GND

second potential terminal

Claims (14)

A circuit for computing a logical combination of two encrypted input operands, comprising: a first input for receiving a first dual rail signal (AM, AMN) having data values of the first input in a calculation cycle and precharge values in a precharge cycle; a second input for receiving a second dual rail signal (BM, BMN) having data values of the second input in the calculation cycle and precharge values in the precharge cycle; a third input for receiving a dual rail encryption signal (M, MN) having encryption values in the calculation cycle and precharge values in the precharge cycle; an output for outputting a dual rail result signal (ZM, ZMN) having result values encrypted in the calculation cycle and precharge values in the precharge cycle; wherein the data values of the first and second dual-rail signals and the encrypted result values of the dual-rail result signal are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule; a logic circuit ( 104 ) for determining the encrypted result values according to the logical combination of the data values of the first input and the second input and the encryption values, and for outputting the encrypted result values in the calculation cycle at the output; and a precharge circuit ( 102 ), which is designed to already impress pre-charging values in the output when precharge values are detected at a single input, or which is designed to terminate an impressing of the precharge values only when the first dual rail signal (AM, AMN) and the second dual-rail signal (BM, BMN) data values and the dual-rail encryption signal (M, MN) have encryption values. Circuit according to claim 1, each dual-rail signal (AM, AMN, BM, BMN, ZM, ZMN, M, MN) each of a first signal (AM, BM, ZM, M) and a second signal (AMN, BMN, ZMN, MN), and wherein the first and second signals of the dual-rail signals at Preload values each have the same logical states and data values, encryption values or result values have mutually inverted logical states. Circuit according to a of the preceding claims, wherein the precharge values of the dual rail signals (AM, AMN, BM, BMN; ZM, ZMN; M, MN) have the same logical states. A circuit according to any one of the preceding claims, wherein the logical link is an XOR link according to the look-up table

where the wildcard (-) stands for any of the logical states 1 or 0. A circuit according to any one of the preceding claims, further comprising a first potential terminal (VDD) for a high potential and a second potential terminal (VSS) for a low potential; the logic circuit ( 104 ) is a pull-down network, which is connected between the second potential terminal and a dual rail intermediate node (ZMN_INT, ZM_INT) and is designed to impress the low potential on a node of the dual rail intermediate node (ZMN_INT, ZM_INT) if precharge values are detected at neither the first input nor the second input nor at the third input for receiving the dual rail encryption signal; and wherein the precharge circuit ( 102 ) is a pull-up network, which is connected between the first potential terminal and the dual-rail intermediate node, and is designed to memorize the high potential of both nodes of the dual-rail intermediate node, as long as at least one single input or the third input for receiving the dual-rail encryption signal, the precharge values are detected; and an inverter pair ( 106a . 106b ), which is connected between the dual-rail intermediate node and the output, and is designed to the high potential or the low potential corresponding logical states of the dual-rail intermediate node inverted as a dual-rail result signal (ZM, ZMN) to provide at the exit. Circuit according to one of the preceding claims, wherein the logic circuit ( 104 ) and the precharge circuit ( 102 ) are each realized as independent transistor circuits. A circuit according to claim 6, wherein the transistor circuit of the logic circuit ( 104 ) and the transistor circuit of the precharge circuit ( 102 ) have no shared transistors. A circuit according to claim 6 or 7, wherein the logic circuit ( 104 ) a discharge transistor ( 720 ), which is designed to memorize the low potential in a first calculation cycle to a node (ZM_INT) of the dual rail intermediate node E (ZM_INT, ZMN_INT) and, in a second calculation cycle, to the other node (ZMN_INT) of the dual rail intermediate node to memorize the low potential. Circuit according to a of the preceding claims, where the logical link an AND, an NAND, an OR, a NOR, an XOR, an NXOR an ANDOR, an ORAND a multiplexor or a majority function is. Circuit according to one of claims 5 to 9, wherein the precharge circuit ( 102 ) a first comparison device ( 510a ), a second comparator ( 510b ) and a third comparison device ( 510c ), wherein the first comparison means is adapted to impress pre-charge values on the intermediate nodes (ZM_INT, ZMN_INT) when the first signal and the second signal of the first dual-rail signal (AM, AMN) have the same logical values, the second comparison device ( 510b ) is designed to impress precharge values on the intermediate nodes (ZM_INT, ZMN_INT) if the first signal and the second signal of the second dual-rail signal (BM, BMN) have identical logical values, and wherein the third comparison device ( 510c ) is configured to impress pre-charge values on the intermediate nodes (ZM_INT, ZMN_INT) when the first signal and the second signal of the dual-rail encryption signal (M, MN) have identical logical values. Circuit according to one of claims 5 to 10, wherein the precharge circuit comprises a holding member ( 512 ) configured to hold one of the nodes of the dual rail intermediate node (ZM_INT, ZMN_INT) at the high potential (VDD) when impressing the low potential (VSS) to the other node of the dual rail intermediate node from the logic circuit is. Circuit according to one of the preceding claims, further comprising a further input for receiving a further dual rail signal (CM, CMN) which has data values of the further input in the calculation cycle and precharge values in the precharge cycle, the data values of the further dual rail Signals are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule; and wherein the logic circuit ( 104 ) is configured to determine the result values according to the logical combination of the data values of the first, second and further dual-rail signals and the encryption values; and wherein the precharge circuit ( 102 ) is formed in order to terminate the impressing of the precharge values only when the first, second and further dual rail signals have data values. Circuit according to a of the preceding claims, the encryption rule an XOR link or an NXOR link is. Method for calculating a logical combination of two Input operands, with the following steps: Receiving a first dual rail signal (AM, AMN) at a first input, the in a calculation cycle, data values of the first input and in a precharge cycle has precharge values; Receiving a second dual rail signal (BM, BMN) at a second input, the in the calculation cycle, data values of the second input and in having precharge values in the precharge cycle; Receive a dual-rail encryption signal (M, MN), the encryption values in the calculation cycle and in the precharge cycle Having precharge values; Determine encrypted Result values according to the logical shortcut from the data values of the first input and the second input and the encryption values and spend the encrypted Result values in the calculation cycle at an output for output of a dual rail result signal (ZM, ZMN), which is in the calculation cycle the encrypted Result values and precharge values in the precharge cycle; in which the data values of the first and second dual-rail signal and the result values of the dual-rail result signal the encryption values of the dual-rail encryption signal according to a encoding rule encoded are; inculcate pre-load values at the exit already when pre-load values be detected at a single input, or terminate the memorization of the Precharge values only when the first and the second dual-rail signal Data values and the dual-rail encryption signal (M, MN) encryption values exhibit.