DE102005033003A1 - Integrated circuit arrangement e.g. DC converter, for use in e.g. electrically erasable programmable ROM, has potential enhancing circuits with controllable switches, and N-doped or P-doped wells connected with outputs of circuits - Google Patents

Abstract

The arrangement has two potential enhancing circuits (1, 2) with controllable switches (T2, T5) that have control inputs for applying control signals (B1, B2), respectively. The circuits are respectively connected with outputs (A1, A2) over control units (T3, T6). N-doped or P-doped wells are respectively connected with the outputs of the circuits, where the N-doped or P-doped wells are connected with an output terminal. An independent claim is also included for a method for operating an integrated circuit arrangement.

Description

The The invention relates to an integrated circuit arrangement for increasing the potential, in the one supply potential into a higher level output potential is converted.

the Specialists are many Circuit arrangements for generating an output potential, which higher than the input potential is known. Such circuitry are u. a. known as DC-DC converter or charge pumps and are integrated into. Circuits preferred with switched capacities realized. In a first phase, there will be a capacity with the input potential connected and charged. In a second phase, the capacity of the Input potential separated and thus with a further potential, z. B. another capacity or a clock signal that results in a potential, the higher than the input potential is. To the ripple of the output potential Frequently two identical transducers are used to reduce the transformer connected in parallel and operated in anti-phase. Potential increase circuits are missing other in semiconductor memories use, such as in EEPROM memories, where to delete the memory requires a potential that is higher than the supply potential is.

With Help of CMOS (Complimentary Metal Oxide Semiconductor) manufacturing technology can be used both N-channel transistors (NMOS) and P-channel transistors (PMOS), always one of the two types of transistors are formed directly in the substrate, while the other variety of Transis tors are arranged in their own, so-called "tubs." In today's standard process is the substrate is P-doped and source and drain of NMOS devices are formed directly in the substrate. PMOS devices are against it in their own N-doped wells, which are arranged in the substrate, educated. The substrate is usually connected to ground and the tubs are of any potential, but mostly with the supply potential.

at Potential increase circuits which use a P-doped substrate is the required withstand voltage the NMOS devices higher because between gate and the other terminals drain, source and substrate that increased Potential occurs. For PMOS devices, however, the required Dielectric strength lower because the well of a PMOS device with the Supply potential can be connected and thus the voltage between gate and the other terminals drain, source and substrate less than the increased Potential. In a circuit for increasing the potential of, for example, VDD on 2 · VDD would be one Dielectric strength of the NMOS devices of 2 · VDD is required, while for the PMOS devices, whose well is at the potential VDD, a dielectric strength would be sufficient from VDD.

The Use of NMOS Devices in Potential Boosting Circuits, P-doped Substrate, thus requiring the use of components, the one higher Voltage withstand between gate and terminals Drain, Source and substrate. Namely the highest allowed Voltage exceeded, this damages the gate oxide and thus the circuit.

A higher Dielectric strength of the transistors can in principle by a thicker gate oxide can be achieved. A disadvantage with transistors with thicker gate oxide, however, that is the threshold voltage elevated, the power efficiency drops and that manufacturing technology is its own Process step for the Gate oxide is necessary.

Of the Use of components with higher dielectric strength let yourself avoid if the NMOS devices in their own P-wells, the so called "triple wells "arranged their potential as well as the potential of the tubs of the PMOS devices can be lifted. However, this is also possible due to the more complex manufacturing process with economic Disadvantages connected.

The above also apply to a process in which an N-doped substrate is used. In this case, the NMOS devices would be in own tubs arranged and for the PMOS devices would be increased Dielectric strength or triple wells required.

Of the The invention is therefore based on the object, an integrated circuit arrangement for potential increase in a process with P-doped substrate only PMOS transistors or in a process with N-substrate only NMOS transistors. Compared to the State of the art is the required dielectric strength of Transistors too reduced without requiring extra tubs or process steps needed become.

The object is achieved according to the invention by providing an integrated circuit arrangement for increasing the potential, with a supply potential input for supplying a supply potential and with an output connection for picking up an output potential. The circuit arrangement comprises a first and a second potential-increasing circuit, each having an input connected to the supply potential input, each having a first clock signal input for applying a respective first clock signal and a second clock signal input for applying a respective second clock signal and each having an output to Output of a respective potential. Furthermore, the circuit arrangement comprises an evaluation circuit having a first input, a second input and an output, the first input of the evaluation circuit being connected to the output of the first potential-increasing circuit and the second input of the evaluation circuit being connected to the output of the second potential-increasing circuit. The output of the evaluation circuit is connected to the output terminal. The first potential-increasing circuit and the second potential-increasing circuit each have a controllable switch with a respective control input for applying a respective control signal, a drive element with a respective control input, a first capacitor and a second capacitor. The respective controllable switches connect the respective input to the respective output of the respective potential-increasing circuit. The respective control input of the respective controllable switch is connected via the respective second capacitor to the respective second clock signal input and further connected via the respective drive element to the respective output of the respective potential boosting circuit. The respective control input of the respective drive element is connected to the respective input of the respective potential-increasing circuit and the respective output of the respective potential-raising circuit is connected via the respective first capacitor to the respective first clock signal input.

With Such a circuit arrangement can be connected to the controllable Switch and the control elements reduce maximum occurring voltage.

advantageously, are the respective controllable switch transistors.

advantageously, the respective drive elements are transistors.

transistors can be easily realized with CMOS manufacturing techniques.

advantageously, the transistors are PMOS transistors. Are all transistors formed as PMOS transistors, they can in a P-substrate process be arranged in separate N-doped tubs.

advantageously, For example, the PMOS transistors are arranged in a well and this well is connected to the output terminal.

advantageously, are the PMOS transistors of the first potential-boosting circuit arranged in a first tub and the first tub is connected to the Output of the first potential-boosting circuit connected, and the PMOS transistors of the second potential-increasing circuit are arranged in a second tub and the second tub is connected to the output of the second potential-increasing circuit.

The required dielectric strength between gate and the terminals drain, Source or substrate can be connected by connecting the tubs to the be reduced potentials.

advantageously, the transistors are NMOS transistors. Because only NMOS transistors can be used, all transistors in an N-substrate process in their own P-doped Arrange tubs.

advantageously, For example, the NMOS transistors are arranged in a well and this well is connected to the output terminal.

advantageously, are the NMOS transistors of the first potential-increasing circuit arranged in a first tub and the first tub is connected to the Output of the first potential-boosting circuit connected, and the NMOS transistors of the second potential-increasing circuit are arranged in a second tub and the second tub is connected to the output of the second potential-increasing circuit.

The required dielectric strength between gate and the terminals drain, Source or substrate can be connected by connecting the tubs to the be reduced potentials.

Advantageously, the evaluation circuit has a first controllable switch with a control input and a second controllable switch with a control input. The first controllable switch connects the first input of the evaluation circuit to the output of the evaluation circuit and the second controllable switch connects the second input of the evaluation circuit to the output of the evaluation circuit. The control input of the first controllable switch is connected to the second input of the evaluation circuit and the control input of the second controllable switch is connected to the first input of the evaluation circuit. The evaluation circuit uses the first and second controllable switches to output the potential increase forwarded to the output of the evaluation circuit, which has the higher potential. In an anti-phase operation of the first and the second potential-increasing circuit, a gap-free potential is generated at the output of the integrated circuit arrangement and its ripple is reduced.

advantageously, are the first controllable switch and the second controllable switch the evaluation circuit transistors.

advantageously, the transistors are PMOS transistors. This is especially beneficial if the potential increase circuits only PMOS transistors have, since thus only PMOS transistors used, all in N-doped Tubs can be arranged.

Advantage oats way are the PMOS transistors of the evaluation circuit together with the PMOS transistors the first potential boosting circuit and the PMOS transistors of the second potential-increasing circuit placed in a tub and this tub is connected to the output port connected.

advantageously, are the PMOS transistors of the evaluation circuit in a third Arranged tub and the third tub is connected to the output terminal connected.

By the connection of the tubs to the corresponding potentials can be reduce the required dielectric strength of the transistors.

advantageously, the transistors are NMOS transistors. This is especially beneficial if the potential increase circuits only NMOS transistors have, since thus only NMOS transistors used, all in P-doped Tubs can be arranged.

Advantage oats way are the NMOS transistors of the evaluation circuit together with the NMOS transistors the first potential boosting circuit and the NMOS transistors of the second potential-increasing circuit placed in a tub and this tub is connected to the output port connected.

advantageously, are the NMOS transistors of the evaluation in a third Arranged tub and the third tub is connected to the output terminal connected.

By the connection of the tubs to the corresponding potentials can be reduce the required dielectric strength of the transistors.

• 1. Anlegen eines Versorgungspotenzials an den Versorgungspotenzialeingang der integrierten Schaltungsanordnung,
• 2. Anlegen eines ersten Potenzialpegels an die ersten Taktsignaleingänge und an die zweiten Taktsignaleingänge der integrierten Schaltungsanordnung,
• 3. Anlegen eines zweiten Potenzialpegels an den ersten Taktsignaleingang der ersten Potenzialerhöhungsschaltung,
• 4. Anlegen eines zweiten Potenzialpegels an den zweiten Taktsignaleingang der ersten Potenzialerhöhungsschaltung,
• 5. Anlegen eines ersten Potenzialpegels an den zweiten Taktsignaleingang der ersten Potenzialerhöhungsschaltung,
• 6. Anlegen eines ersten Potenzialpegels an den ersten Taktsignaleingang der ersten Potenzialerhöhungsschaltung,
• 7. Anlegen eines zweiten Potenzialpegels an den ersten Taktsignaleingang der zweiten Potenzialerhöhungsschaltung,
• 8. Anlegen eines zweiten Potenzialpegels an den zweiten Taktsignaleingang der zweiten Potenzialerhöhungsschaltung,
• 9. Anlegen eines ersten Potenzialpegels an den zweiten Taktsignaleingang der zweiten Potenzialerhöhungsschaltung,
• 10. Anlegen eines ersten Potenzialpegels an den ersten Taktsignaleingang der zweiten Potenzialerhöhungsschaltung und
• 11. Abgreifen des Ausgangspotenzials am Ausgangsanschluss.

The object is achieved as regards a method by a method for operating the integrated circuit arrangement, which has the following steps in this order:

• 1. application of a supply potential to the supply potential input of the integrated circuit arrangement,
• 2. applying a first potential level to the first clock signal inputs and to the second clock signal inputs of the integrated circuit device,
• 3. applying a second potential level to the first clock signal input of the first potential-boosting circuit,
• 4. applying a second potential level to the second clock signal input of the first potential-boosting circuit,
• 5. applying a first potential level to the second clock signal input of the first potential-boosting circuit,
• 6. applying a first potential level to the first clock signal input of the first potential-boosting circuit,
• 7. applying a second potential level to the first clock signal input of the second potential-boosting circuit,
• 8. applying a second potential level to the second clock signal input of the second potential-boosting circuit,
• 9. applying a first potential level to the second clock signal input of the second potential-boosting circuit,
• 10. Applying a first potential level to the first clock signal input of the second potential-increasing circuit and
• 11. Picking up the output potential at the output terminal.

By applying the first and second levels to the first and second levels Clock signal inputs of first and second potential increase circuit becomes the supply potential alternately placed on one of the first capacitors, these charged, separated from the supply potential input, by the first clock signals to a higher one Reference potential lifted and connected to the output, so that the Output potential of the integrated circuit arrangement is higher as the entry potential.

advantageously, Steps 3 to 10 are repeated periodically. By the periodic Repetition of these steps will further increase the starting potential elevated until the output potential of the integrated circuit arrangement about the difference between the first potential level and the second Potential level higher is considered the supply potential.

Advantageously, the supply is potential zial a positive potential, the first potential level a positive potential and the second potential level lower than the first potential level when the integrated circuit arrangement is constructed only with PMOS transistors. Such potentials ensure that the output potential is higher than the supply potential.

advantageously, the second potential level is a zero potential. Zero potentials can be passed through ground terminals easy to realize.

advantageously, the supply potential is a negative potential, the first one Potential level is a negative potential and the second potential level higher than the first potential level when the integrated circuit only with NMOS transistors is constructed. Such potentials ensure that the starting potential lower than the supply potential. It can be with The invention thus also further reduce negative supply potentials.

advantageously, the second potential level is a zero potential. Zero potentials can be passed through ground terminals easy to realize.

The Invention will be described below with reference to an embodiment with reference to the drawings explained in more detail.

In show the drawings:

1 the circuit diagram of an embodiment according to the invention,

2 the time course of the clock signals,

3 the curves of the potentials N1 and N2, and

4 the curves of the potential N1 and the control signal B1.

1 shows the circuit diagram of an embodiment according to the invention in a realization with only PMOS transistors. The circuit arrangement consists of a first potential increase circuit 1 , a second potential increase circuit 2 and an evaluation circuit 3 , The inputs E1 and E2 of the first and second potential increase circuit 1 and 2 are connected to the supply potential input E. The output A1 of the first potential increase circuit 1 is connected to the first input I1 of the evaluation circuit 3 connected, the output A2 of the second potential booster circuit 2 is connected to the second input I2 of the evaluation circuit 3 connected. A supply potential VDD is applied to the supply potential input E, and an output potential VOUT, which has a higher potential level than the supply potential VDD, can be tapped off at the output terminal A. The first and second potential increase circuit 1 and 2 each have a first clock signal input C1, C2, to which the first clock signals CK1 and CK2 are applied and via a second clock signal input C3, C4 to which the second clock signals CK3 and CK4 are applied.

Because the first potential booster circuit 1 and the second potential increasing circuit 2 are constructed identically, in the following only the first potential increase circuit 1 described. For the second potential boost circuit 2 apply the same versions with the correspondingly adapted reference numerals. The output A1 of the first potential increase circuit 1 can be connected to the supply potential input E via the controllable switch T2, which is designed as a PMOS transistor. At the control input G2 of the controllable switch T2 is the control signal B1. The control input G2 is connected via a second capacitor CB1 to the second clock signal input C3. Furthermore, the control input G2 is connected to the output A1 of the first potential-increasing circuit via the drive element T3, which is designed as a PMOS transistor 1 connected. The control input G3 of the drive element T3 is connected to the input E1 of the first potential increase circuit 1 connected is. The output A1 of the first potential increase circuit 1 is further connected via a first capacitor CP1 to the first clock signal input C1.

In 1 is a realization of the evaluation circuit 3 shown with first and second controllable switches T1, T4, which are designed as PMOS transistors. The control input G1 of the first controllable switch T1 is connected to the second input I2 of the evaluation circuit 3 connected, the control input G4 of the second controllable switch T4 is connected to the first input I1 of the evaluation circuit 3 connected.

The evaluation circuit 3 serves to connect the potentials N1 and N2 at the outputs A1, A2 of the potential-boosting circuit 1 . 2 to forward to the output terminal A. In an evaluation circuit constructed with PMOS transistors 3 Weil ever the higher of the potentials N1 and N2 is forwarded to the output terminal A.

In 2 3, the time profiles of the first clock signals CK1, CK2 and of the second clock signals CK3, CK4 are shown, which are connected to the first C1, C2 and second clock signal inputs C3, C4 of the in 1 shown circuit must be applied to a Increase potential. The clock signals CK1, CK2, CK3, CK4 are periodic and occupy either a first potential level P1 or a second potential level P2. In the embodiment, the second potential level P2 is a ground potential and the clock signal amplitude VC, which is determined by the difference between the first potential level P1 and the second potential level P2, is 1.5 volts. The clock signals CK1, CK2, CK3, CK4 have the same frequency, from z. 1 MHz.

For the function of in 1 The sequence of the periodic transitions of the clock signals CK1, CK2, CK3, CK4 from the first potential level P1 to the second potential level P2 and back again is of decisive importance. In the 2 shown time histories are divided into two sections to facilitate understanding. In the first section "1", which comprises the times t1 to t4, in the first potential-increasing circuit 1 connected through the transitions of the clock signals CK1 and CK3, the transistor T2 and first capacitor CP1 loaded. During this time, the clock signals CK2 and CK4 are at the second potential boost circuit 2 applied constant at the first potential level P1, so that the increased potential N2 is present at the output A2. In the second section "2", which includes the times t5 to t8, becomes in the second potential increasing circuit 2 connected through the transitions of the clock signals CK2 and CK4, the transistor T5 and first capacitor CP2 loaded. During this time, the clock signals CK1 and CK3 are at the first potential boost circuit 1 Constant at the first potential level P1, so that the increased potential N1 is present at the output A1. The two sections "1" and "2" repeat periodically, so that in each case alternately the first and second potential increase circuit 1 . 2 provide an increased potential at their outputs A1, A2.

In 3 are the potentials N1 at the output A1 of the first potential-boosting circuit 1 and the potential N2 at the output A2 of the second potential-increasing circuit 2 shown. The potentials N1 and N2 oscillate between the supply potential VDD and the output potential VOUT = VDD + VC with the frequency of the clock signals and overlap slightly.

The voltage waveforms of the potential N1 and the control signal B1 are together with the times t1 to t9 in FIG 4 shown. In addition, the supply potential VDD = 3.3 V and the output potential VOUT = 4.7 V are plotted in the figures.

The following is now the functioning of in 1 shown circuitry, when used with the in 2 operated clock signals is operated. It is assumed that there is a steady state in which VOUT = VDD + VC. At a point in time which is shortly before time t1, therefore, the potential N1 is at the output A1 of the first potential-increasing circuit 1 higher than the supply potential VDD. The control input G3 of the transistor T3 is thus at a lower potential than the source of Transis sector T3, so that the transistor T3 conducts. The control signal B1 is thereby charged to the potential N1. As a result, the transistor T2 turns off. The potential N1 can therefore not discharge via the supply potential input E. The potential N2 at the output A2 of the second potential-increasing circuit 2 runs in phase opposition to the potential N1, so that at the control input G1 of the transistor T1 is applied to a source-related negative voltage and this passes. The charge stored in the first capacitor CP1 can thus be passed on to the output terminal A.

Now falls at time t1, the first clock signal CK1 from the first potential level P1 to the second potential level P2, the potential N1 drops approximately VDD. Since transistor T3 is still conducting, control signal B1 follows first the potential N1 down. The signals separate when the voltage between the control input G3 and the output A1 the threshold voltage of the transistor T3 approaches. If the potential N1 in the vicinity of the supply potential VDD, the transistor T3 blocks since its control input G3 is connected to the supply potential VDD is.

To the Time t2 falls also the second clock signal CK3 from the first potential level P1 to the second potential level P2. With the clock signal CK3 drops the control signal B1 below the supply potential VDD. Because of it the control input G2 of the transistor T2 negative with respect to source is, this manages. Electricity flows from the supply potential input E1 to the first capacitor CP1 and load this to the supply potential VDD. Since the potential N2 out of phase to the potential N1, the transistor T1 becomes at this time locked, so that the charge can not flow to the output terminal A.

At time t3, the second clock signal CK3 rises from the second potential level P2 back to the first potential level P1. As a result, the control signal B1 also rises slightly above the potential N1, so that the transistor T3 conducts again and the control signal B1 is again coupled more firmly to the potential N1. The control signal B1 is greater than the supply potential VDD, so that the control input G2 of the transistor T2 becomes more positive than its source. The transistor T2 stops conducting and disconnects the first capacitor CP1 from Ver supply potential input E.

To the At time t4, the first clock signal CK1 rises from the second potential level P2 back to the first potential level P1, so that the initial state recovered at the time before t1 and the potential N1 is raised from VDD to VDD + VC.

The second potential boost circuit 2 behaves like the first potential boost circuit 1 but where N1 is N2, B1 is B2, T1 is T4, T2 is T5, T3 is T6, CK1 is CK2, and CK3 is CK4, and times t1, t2, t3, t4 are t5, t6, t7, t8 in FIG above description must be replaced. At time t9, then the entire sequence is repeated.

The first capacitors CP1 and CP2 are so-called "pump capacitors", which affect the supply potential VDD are charged and their reference potential through the first Clock signals CK1 and CK2 raised by the clock signal amplitude VC becomes. They will be provided according to the output terminal A to be provided Power dimensioned. and can realized by external capacitors with capacities of approx. 50 to 100 pF become.

The second capacitors CP1 and CP2 serve to drive the transistors T2 and T5. When the second clock signals CK3, CK4 are at the low second potential level P2, the control signals B1 and B2 are pulled down and the transistors T2 and T5 are conducting. The first capacitors CP1 and CP2 are then charged to the supply potential VDD. On the other hand, when the second clock signals CK3 and CK4 are at the high first potential level P1, the control inputs G2 and G5 of the transistors T2 and T5 are respectively connected to the potentials N1 and N2 through the transistors T3 and T6 and raised to VDD + VC. Thus, the transistors T2 and T5 block, and the charge on the first capacitors CP1 and CP2 can not back to the supply potential input E, but only to the evaluation circuit 3 flow. The capacitances of the second capacitors CP1, CP2 are orders of magnitude smaller than the pump capacitors CP1, CP2, typical capacitances are 100 fF. The capacitance is determined essentially by the size of the transistors T2 and T5, since these capacitors must be able to reload their control inputs G2 and G5. Due to the low capacitances, the control signals B1 and B2 are closely coupled to the second clock signals CK3, CK4.

Essential feature of in 1 is shown that the double clock signal amplitude 2 · VC does not occur at the transistors T2 or T5 but only at the second capacitors CP1 and CP2. The control signals B1 and B2 at the control inputs G2 and G5 only sink below the supply potential VDD when the potentials N1 and N2 have already dropped to VDD, as in FIG 4 shown. If the control signals B1 and B2 were pulled down by the second clock signals CK3 and CK4 if the potentials N1 and N2 were still at VOUT + VDD, the transistors T2 and T5 would be damaged by the occurring double clock signal amplitude of 2 * VC. In previous potential-boosting circuits, the control inputs G2 and G5 of the transistors T2 and T5 have been driven by NMOS circuits, the transistors in these circuits requiring twice as high withstand voltage as those in US Pat 1 shown transistors.

Of the exact value of the supply potential VDD is thus arbitrary, so long the well of PMOS transitors this voltage endures. In the embodiment VDD = 3.3V was chosen. It can quite higher Supply potential VDD be used as long as the clock signal amplitude VC remains limited.

The maximum clock signal amplitude VC, however, is used by the Technology given, as the PMOS transistors in the circuit between control input and one of its other connections exactly have to endure this amplitude. The Clock signal amplitude VC is therefore chosen so that the maximum allowable voltage is not achieved. In the embodiment the clock signal amplitude VC = 1.5 volts is selected.

This in 1 embodiment shown and in 2 shown clock signal waveforms can be modified such that the circuit is constructed only with NMOS transistors. The supply potential VDD and the output potential VOUT then become negative, the clock signals CK1, CK2, CK3 and CK4 must also have negative first potential levels P1 and second potential levels P2. The first potential level P1 would be lower than the second potential level P2. The second potential level P2 could be a ground potential. The circuit arrangement is then a circuit for lowering the potential.

1

first Potential raising circuit

2

second Potential raising circuit

3

evaluation

t1-t9

changeover

A

output port

A1, A2

Outputs of the Potential increase circuits

B1, B2

control signals

C1, C2

first Clock signal inputs

C3, C4

second Clock signal inputs

CP1, CP2

first capacitors

CB1, CB2

second capacitors

CK1, CK2

first clock signals

CK3 CK4

second clock signals

e

Supply potential input

E1, E2

Inputs of the Potential increase circuits

G1, G4

Control inputs of the controllable switch T1, T4

G2, G5

Control inputs of the controllable switch T2, T5

G3, G6

Control inputs of the Control element T3, T6

I1, I2

first and second input of the evaluation circuit

N1, N2

output potential the potential increase circuits

P1, P2

first and second potential level

T1, T4

first and second controllable switch of the evaluation circuit

T2, T5

steuerbarere Switch of the potential increase circuits

T3, T6

Actuation

VC

Clock signal amplitude

VDD

supply potential

VOUT

output potential

Claims (23)

Integrated potential increase circuit comprising a supply potential input (E) for supplying a supply potential (VDD) and an output terminal (A) for sampling an output potential (VOUT), comprising - a first potential increasing circuit (E) 1 ) and a second potential increase circuit ( 2 ), each having an input (E1, E2), which is connected to the supply potential input (E), each having a first clock signal input (C1, C2) for applying a respective first clock signal (CK1, CK2) and respectively a second clock signal input (C3 , C4) for applying a respective second clock signal (CK3, CK4) and each having an output (A1, A2) for outputting a respective potential (N1, N2), and - an evaluation circuit ( 3 ) having a first input (I1), a second input (I2) and an output, wherein the first input (I1) of the evaluation circuit ( 3 ) with the output (A1) of the first potential-increasing circuit ( 1 ) and the second input (I2) of the evaluation circuit ( 3 ) to the output (A2) of the second potential-increasing circuit ( 2 ), and the output of the evaluation circuit ( 3 ) is connected to the output terminal (A), characterized in that the first potential- increasing circuit ( 1 ) and the second potential increase circuit ( 2 ) - a controllable switch (T2, T5) with a respective control input (G2, G5) for applying a respective control signal (B1, B2), - a drive element (T3, T6) with a respective control input (G3, G6), - a first capacitor (CP1, CP2) and - a second capacitor (CB1, CB2), wherein - the respective controllable switches (T2, T5) connect the respective input (E1, E2) to the respective output (A1, A2), - The respective control input (G2, G5) of the respective controllable switch (T2, T5) via the respective second capacitor (CB1, CB2) with the respective second clock signal input (C3, C4) is connected and further via the respective drive element (T3, T6 ) with the respective output (A1, A2) of the respective potential-boosting circuit ( 1 . 2 ), wherein - the respective control input (G3, G6) of the respective drive element (T3, T6) to the respective input (E1, E2) of the respective potential increase circuit ( 1 . 2 ), and - the respective output (A1, A2) of the respective potential-boosting circuit ( 1 . 2 ) is connected to the respective first clock signal input (C1, C2) via the respective first capacitor (CP1, CP2). The integrated circuit arrangement according to claim 1, characterized in that the respective controllable switch (T2, T5) are transistors. The integrated circuit arrangement according to claim 1 or 2, characterized in that the respective control elements (T3, T6) are transistors. The integrated circuit arrangement according to claim 3, characterized in that the transistors PMOS transistors are. The integrated circuit arrangement according to claim 4, characterized in that the PMOS transistors in a well are arranged and this tub connected to the output terminal (A) is. The integrated circuit arrangement according to claim 4, characterized in that - the PMOS transistors of the first potential-boosting circuit ( 1 ) are arranged in a first well and the first well is connected to the output of the first potential-increasing circuit (A1), and - the PMOS-transistors of the second potential-increasing circuit ( 2 ) are arranged in a second well and the second well is connected to the output of the second potential-increasing circuit (A1). The integrated circuit arrangement according to claim 3, characterized in that the transistors NMO5 transistors are. The integrated circuit arrangement according to claim 7, characterized in that the NMOS transistors in a well are arranged and this tub connected to the output terminal (A) is. The integrated circuit arrangement according to claim 7, characterized in that - the NMOS transistors of the first potential-increasing circuit ( 1 ) are arranged in a first well and the first well is connected to the output of the first potential-increasing circuit (A1), and - the NMOS transistors of the second potential-increasing circuit ( 2 ) are arranged in a second well and the second well is connected to the output of the second potential-increasing circuit (A1). The integrated circuit arrangement according to one of claims 1 to 9, characterized in that the evaluation circuit ( 3 ) has a first controllable switch (T1) with a control input (G1) and a second controllable switch (T4) with a control input (G4), wherein - the first controllable switch (T1) the first input (I1) of the evaluation circuit ( 3 ) with the output of the evaluation circuit ( 3 ) and the second controllable switch (T4) connects the second input (I2) of the evaluation circuit ( 3 ) with the output of the evaluation circuit ( 3 ), and - the control input (G1) of the first controllable switch (T1) with the second input (I2) of the evaluation circuit ( 3 ), and - the control input (G4) of the second controllable switch (T4) to the first input (I1) of the evaluation circuit ( 3 ) connected is. The integrated circuit arrangement according to claim 10, characterized in that the first controllable switch (T1) and the second controllable switch (T4) are transistors. The integrated circuit arrangement according to claim 11, characterized in that the transistors PMOS transistors are. The integrated circuit arrangement according to claim 12, characterized in that the PMOS transistors of the evaluation circuit ( 3 ) together with the PMOS transistors of the first potential-boosting circuit ( 1 ) and the PMOS transistors of the second potential-boosting circuit ( 2 ) are arranged in a trough and this trough is connected to the output terminal (A). The integrated circuit arrangement according to claim 12, characterized in that the PMOS transistors of the evaluation circuit ( 3 ) are arranged in a third well and the third well is connected to the output terminal (A). The integrated circuit arrangement according to claim 11, characterized in that the transistors NMOS transistors are. The integrated circuit arrangement according to claim 15, characterized in that the NMOS transistors of the evaluation circuit ( 3 ) together with the NMOS transistors of the first potential-boosting circuit ( 1 ) and the NMOS transistors of the second potential-boosting circuit ( 2 ) are arranged in a trough and this trough is connected to the output terminal (A). The integrated circuit arrangement according to claim 15, characterized in that the NMOS transistors of the evaluation circuit ( 3 ) are arranged in a third well and the third well is connected to the output terminal (A). Method for operating the integrated circuit arrangement according to one of the preceding claims, comprising the following steps in this order: 1) applying a supply potential (VDD) to the supply potential input (E) of the integrated circuit device, 2) applying a first potential level (P1) to the first clock signal inputs (C1, C2) and to the second clock signal inputs (C3, C4) of the integrated circuit arrangement, 3) application of a second potential level (P2) to the first clock signal input (C1) of the first potential increase circuit ( 1 4) applying a second potential level (P2) to the second clock signal input (C3) of the first potential-increasing circuit ( 1 5) applying a first potential level (P1) to the second clock signal input (C3) of the first potential boosting circuit (P1) 1 6) applying a first potential level (P1) to the first clock signal input (C1) of the first potential-increasing circuit ( 1 7) applying a second potential level (P2) to the first clock signal input (C2) of the second potential-increasing circuit ( 2 8) applying a second potential level (P2) to the second clock signal input (C4) of the second potential boosting circuit (P2) 2 9) applying a first potential level (P1) to the second clock signal input (C4) of the second potential-boosting circuit (P1). 2 ) 10) applying a first potential level (P1) to the first clock signal input (C2) of the second potential-increasing circuit ( 2 ), 11) picking up the output potential (VOUT) at the output terminal (A). Method according to claim 18, characterized that steps 3) to 10) are repeated periodically. Method according to claim 19, characterized that when the integrated circuit is constructed with PMOS transistors is, the supply potential (VDD) is a positive potential, the first potential level (P1) is a positive potential and the second potential level (P2) lower than the first potential level (P1) is. Method according to claim 20, characterized in that the second potential level (P2) is a zero potential. Method according to claim 19, characterized that when the integrated circuit is constructed with NMOS transistors is, the supply potential (VDD) is a negative potential, the first (P1) potential level is a negative potential and the second potential level (P2) higher as the first potential level (P1). Method according to claim 22, characterized in that the second potential level (P2) is a zero potential.