DE102005001590A1 - Board on chip package for high frequency integrated circuit, has silicon chip with core including copper wires having build-up layers, which are structured, such that copper wires on substrate is directly accessible in canal for wire bonds - Google Patents
Board on chip package for high frequency integrated circuit, has silicon chip with core including copper wires having build-up layers, which are structured, such that copper wires on substrate is directly accessible in canal for wire bonds Download PDFInfo
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- DE102005001590A1 DE102005001590A1 DE102005001590A DE102005001590A DE102005001590A1 DE 102005001590 A1 DE102005001590 A1 DE 102005001590A1 DE 102005001590 A DE102005001590 A DE 102005001590A DE 102005001590 A DE102005001590 A DE 102005001590A DE 102005001590 A1 DE102005001590 A1 DE 102005001590A1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
Description
Die Erfindung betrifft ein BOC-Package (Board on Chip Package) mit einem Silizium-Chip, das mit seiner aktiven Seite an einem Substrat befestigt ist und mit wenigstens einer zentralen Reihe von Bondpads versehen ist, die über Drahtbrücken mit Kontakten und Leitbahnen elektrisch verbunden sind, die sich am und im Substrat befinden und auf der dem Chip gegenüber liegenden Seite des Substrates mit Kontaktkugeln versehen sind, und wobei sich die Drahtbrücken durch einen ein- oder mehrstufigen Schlitz im Substrat erstrecken.The The invention relates to a BOC package (Board on Chip Package) with a Silicon chip, which with its active side attached to a substrate is and provided with at least one central row of bond pads is that over jumpers are electrically connected to contacts and interconnects that are located on and in the substrate and on the opposite side of the chip Side of the substrate are provided with contact balls, and wherein the wire bridges by an on or extend multi-stage slot in the substrate.
Es hat sich gezeigt, dass sich die Frequenz, mit der Speicherprodukte betrieben werden, bei jeder Architekturänderung mindestens verdoppelt. Beispielsweise betrug die maximale Taktfrequenz beim DDR2 400 MHz, beim DDR3 800 MHz und beim DDR4 wird die Taktfrequenz bei 1,6 GHz und eventuell sogar bei 3,2 GHz liegen. Verbunden damit sind erheblich steigende Ansprüche an eine stabile Spannungsversorgung um das Signalrauschen der Spannungsversorgung (Supply Noise) gering zu halten.It has been shown to be the frequency with which memory products operate at least doubled with each architecture change. For example, the maximum clock frequency of the DDR2 was 400 MHz, the DDR3 800 MHz and the DDR4, the clock frequency at 1.6 GHz and possibly even at 3.2 GHz. Connected with it are significant rising demands to a stable power supply around the signal noise of the power supply (Supply Noise) to keep low.
Durch die wachsende Anzahl an Versorgungspads (Anschlusskontakte für Versorgungsspannungen) und durch den Zuwachs an Funktionalität und auch durch die Notwendigkeit, ggf. auf differentiale Signale überzugehen, wächst die Anzahl der notwendigen Pads (Anschlüsse), die angeschlossen werden müssen.By the growing number of supply pads (connection contacts for supply voltages) and by the increase in functionality and also by the need to if necessary to transfer to differential signals, grows the number of necessary pads (connectors) to be connected have to.
Bevorzugte Package-Technologie (Verpackungs- und Montagetechnologie) ist nach wie vor die Drahtbond-basierte BOC-BSP-Technologie (Board On Chip mit Backside Protection (Rückseitenschutz)), da diese für zentral angeordnete Bondpads auf dem Silizium-Chip am günstigsten und kostengünstiger ist und keine Änderungen des Chipdesigns erfordert, wie z.B. die Flip-Chip-Technologie.preferred Package technology (packaging and assembly technology) is behind as before the wirebond-based BOC-BSP technology (board on chip with backside Protection (back protection)), since these are for centrally arranged bond pads on the silicon chip most favorable and cheaper is and no changes of the chip design, e.g. the flip-chip technology.
Allerdings kann beim konventionellen BOC-BSP nur eine Kupferebene mittels Drahtbonden kontaktiert werden, was grundsätzlich auch für die Vierlagen-BOC-BSP-Technologie gilt. Diese Technologie bietet zusätzlich zur Cu-Lage für Lötbälle (Solder Balls), Drahtbonden und deren Verbindungsleitungen drei weitere Cu-Lagen, die für Masse- und Versorgungspotential sowie Signalverbindungen genutzt werden können.Indeed In conventional BOC-BSP, only one copper plane can be wire-bonded be contacted, which is basically also for them Four-layer BOC-BSP technology applies. This technology offers in addition to Cu layer for Soldering balls (Solder Balls), wire bonding and their interconnections three more Cu layers for Ground and supply potential and signal connections used can be.
Da bei dieser Technologie nur auf die oberste Signallage gebondet werden kann, müssen auch die Versorgungssignale erst eine Wegstrecke auf dieser Ebene zurück legen und durch ein Via (mit einem leitfähigen Material beschichtetes Loch) geführt werden, bis sie auf die Versorgungsebene mit geringsten Widerständen und Induktivitäten geführt werden können.There With this technology, only the highest signal layer is bonded can, must Also, the supply signals only a distance at this level back and through a via (coated with a conductive material Hole) until they reach the level of care with least resistance and inductors guided can be.
Diese Wegstrecke verursacht eine zusätzliche Versorgungsinduktivität, die das Rauschen auf dem Versorgungspotential erhöht. Eine weitere Einschränkung der BOC-BSP-Technologie liegt in dem Wedgepadpitch (Bondpadpitch (Abstand der Bondkontakte zueinander) auf der Substratseite). Auf Grund technologischer Notwendigkeiten (Bondprozess, Substratstrukturierung) kann dieser Pitch zukünftig nicht in dem erforderlichen Maße reduziert werden, wie es die Shrink-Roadmap der Speicherchips erfordert.These Distance causes an additional supply inductance, which increases the noise on the supply potential. A further restriction BOC-BSP technology lies in the wedge-pad pitch (Bondpadpitch (Distance of the bond contacts to each other) on the substrate side). On reason technological needs (bonding process, substrate structuring) can this pitch in the future not to the required extent be reduced, as required by the shrink roadmap of memory chips.
Ein
Teil dieser Nachteile wird durch die
Eine ähnliche
Speicher-Anordnung geht auch aus der
Der Erfindung liegt nunmehr die Aufgabe zugrunde, ein BOC-Package zu schaffen, bei dem das Problem der Durchbiegung (Warpage) im Wesentlichen beseitigt ist und bei dem deutlich verbesserte Eigenschaften bezüglich der Zuverlässigkeit erreicht werden.Of the Invention is now based on the object to provide a BOC package, in which the problem of warpage is substantially eliminated is and with the significantly improved properties in terms of reliability be achieved.
Die der Erfindung zugrunde liegende Aufgabenstellung wird dadurch gelöst, dass das Substrat aus einem Substrat-Kern (Core) besteht, der beidseitig mit Kupferlagen (Verdrahtungsebenen) versehen ist, auf der (symmetrisch) sich jeweils mindestens jeweils eine weitere Aufbauebene (Build-Up-Layer) mit jeweils einer weiteren Kupferlage (Verdrahtungsebene) befindet.The The object underlying the invention is achieved in that the substrate consists of a substrate core (core), the two sides provided with copper layers (wiring levels) on which (symmetrical) in each case at least one additional build-up level (build-up layer) with each another copper layer (wiring level) is located.
In einer ersten Ausgestaltung der Erfindung ist die Aufbauebene durch Druck- oder Rückätzverfahren auf der Ballseite derart strukturiert, dass die Kupferlage auf dem Substrat-Kern (Core-Oberfläche) im späteren Bondbereich (Bondkanal) für das Wirebonden direkt zugänglich ist.In a first embodiment of the invention, the build-up plane is structured on the ball side by pressure or etching-on methods in such a way that the copper layer is deposited on the substrate core (core surface). in the later bond area (bond channel) for the wirebonding is directly accessible.
Eine vorteilhafte Fortführung der Erfindung ist dadurch gekennzeichnet, dass der Bondkanal im Substrat eine Stufengeometrie mit maximal einer Stufe pro Aufbauebene (Build-up-Layer) aufweist.A advantageous continuation The invention is characterized in that the bonding channel in the substrate has a step geometry with a maximum of one level per build level (build-up layer).
Der Bondkanal kann auch zumindest auf der Ballseite mit zunehmender Öffnung zur Ballseite abgestuft, oder auf der Ball- und der Chipseite gegenläufig abgestuft sein. Damit kann die Chipseite auf ähnliche Weise wie die ballseitige Ebene geöffnet werden, was zu einer größtmöglichen Symmetrie im Aufbau führt. Die Folge ist bei Temperaturänderungen ein geringes Warpage.Of the Bondkanal can also at least on the ball side with increasing opening to Graded on the ball side, or stepped in opposite directions on the ball and the chip side be. This allows the chip side in a similar way as the ball side Level to be opened what to the greatest possible Symmetry in construction leads. The consequence is with temperature changes a low warpage.
Eine besondere Ausgestaltung der Erfindung ist dadurch gekennzeichnet, dass der Bondkanal von der Ball- zur Chipseite durchgängig abgestuft ist, so dass auf der Chipseite ein schmalerer Bondkanal entsteht.A particular embodiment of the invention is characterized in that the bonding channel from the ball to the chip side graded throughout is, so that on the chip side, a narrower bond channel is formed.
Die einzelnen Verdrahtungsebenen sind durch mit Metall oder einem leitfähigen Material gefüllte Vias miteinander verbunden.The individual wiring levels are through with metal or a conductive material filled Vias interconnected.
In einer besonderen Ausgestaltung der Erfindung sind unmittelbar benachbarte Verdrahtungsebenen durch Blind-Vias, die mit Metall oder einem leitfähigen Material gefüllt sind, miteinander verbunden.In a particular embodiment of the invention are immediately adjacent Wiring levels through blind vias made with metal or a conductive material filled are interconnected.
In einer weiteren Ausgestaltung der Erfindung sind innere Verdrahtungsebenen durch vergrabene Vias, die mit Metall oder einem leitfähigen Material gefüllt sind, miteinander verbunden.In Another embodiment of the invention are internal wiring levels through buried vias made with metal or a conductive material filled are interconnected.
Eine spezielle Fortführung der Erfindung ist dadurch gekennzeichnet, dass eine der inneren Verdrahtungsebenen durch Galvanisierung in den Bondkanal verlängert ist, so dass eine weitere Drahtbondebene zur Verfügung steht.A special continuation the invention is characterized in that one of the inner Wiring levels is extended by galvanization in the bonding channel, so that another wire bonding level is available.
Vorteile der Erfindung sind darin zu sehen, dass eine direkte Drahtbondverbindung zu den einzelnen Versorgungsebenen möglich wird und damit eine geringere Versorgungsinduktivität verbunden mit einem geringeren Rauschen auf der Versorgungsleitung möglich wird. Die Kosten der erfindungsgemäßen Build-Up-Technologie sind erheblich günstiger als das Laminieren von zwei Substratcores (Leiterplattenmaterial). Darüber hinaus verringert der symmetrische Aufbau das Substratwarpage erheblich.advantages The invention can be seen in that a direct Drahtbondverbindung to the individual supply levels is possible and thus a lower supply inductance associated with less noise on the supply line possible becomes. The costs of the inventive build-up technology are considerably cheaper as laminating two substrate cores (circuit board material). About that In addition, the symmetrical structure significantly reduces the substrate warpage.
Mit Hilfe der Build-up-Technologie kann der Abstand der einzelnen Kupferlagen zueinander eingestellt werden, so dass eine Impedanzkontrolle möglich wird und ein vorgegebener Wert eingestellt werden kann. Schließlich verringert die Präsenz von mehreren Kupferlagen den thermischen Widerstand ganz erheblich, der durch eine geeignete Verteilung der Vias weiter verbessert werden kann.With Help the build-up technology, the distance of each copper layers adjusted to each other, so that an impedance control is possible and a predetermined value can be set. Finally reduced the presence of several copper layers the thermal resistance quite considerably, which can be further improved by a suitable distribution of the vias can.
Schließlich lassen sich bei einem Bondkanal basierten Package Wedgepads zum Drahtbonden auf unterschiedlichen Substratebenen bereitstellen.Finally leave In a bond channel based package, wedge pads are used for wire bonding provide different substrate levels.
Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden. In den zugehörigen Zeichnungen zeigen:The Invention will be explained in more detail below using an exemplary embodiment. In the associated Drawings show:
In
Die
Befestigung des Chips
Wesentlich
ist, dass der Substrataufbau
Durch
Veränderung
der Dicke der Aufbauebenen
Durch
den erfindungsgemäßen Substrataufbau
In
- 11
- Standard-PackageStandard Package
- 22
- Chipchip
- 33
- TapeTape
- 44
- Leiterplattecircuit board
- 55
- BondkanalBond channel
- 66
- Drahtbrückejumper
- 77
- KontaktContact
- 88th
- Verdrahtungwiring
- 99
- KontaktkugelContact ball
- 1010
- Vergussmassepotting compound
- 1111
- 4-Lagen-Leiterplatte4-layer printed circuit board
- 1212
- Substrat (Core)substratum (Core)
- 1313
- BondkanalBond channel
- 1414
- Substrataufbausubstrate assembly
- 15.115.1
- Cu-VerdrahtungCu wiring
- 15.215.2
- Cu-VerdrahtungCu wiring
- 16.116.1
- Aufbauebeneconstruction level
- 16.216.2
- Aufbauebeneconstruction level
- 17.117.1
- Cu-VerdrahtungCu wiring
- 17.217.2
- Cu-VerdrahtungCu wiring
- 18.118.1
- Lötstoppmaskesolder mask
- 18.218.2
- Lötstoppmaskesolder mask
- 1919
- Klebemitteladhesive
- 2020
- Bondpadbonding pad
- 2121
- Bondpadbonding pad
- 2222
- Drahtbrückejumper
- 2323
- viavia
- 2424
- Aussparungrecess
- 2525
- Lötkugel (Solder Ball)Solder ball (Solder Ball)
- 26.126.1
- Aufbauebeneconstruction level
- 26.226.2
- Aufbauebeneconstruction level
- 27.127.1
- Cu-VerdrahtungCu wiring
- 27.227.2
- Cu-VerdrahtungCu wiring
- 2828
- Galvanisierunggalvanization
Claims (10)
Priority Applications (1)
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DE102005001590A DE102005001590B4 (en) | 2005-01-12 | 2005-01-12 | BOC Package |
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DE102005001590A DE102005001590B4 (en) | 2005-01-12 | 2005-01-12 | BOC Package |
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DE102005001590A1 true DE102005001590A1 (en) | 2006-07-20 |
DE102005001590B4 DE102005001590B4 (en) | 2007-08-16 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007014198A1 (en) * | 2007-03-24 | 2008-09-25 | Qimonda Ag | Integrated component |
CN101740530A (en) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | Integrated circuit substrate |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6049129A (en) * | 1997-12-19 | 2000-04-11 | Texas Instruments Incorporated | Chip size integrated circuit package |
US6423622B1 (en) * | 1999-12-29 | 2002-07-23 | Advanced Semiconductor Engineering, Inc. | Lead-bond type chip package and manufacturing method thereof |
US20040065473A1 (en) * | 2002-10-08 | 2004-04-08 | Siliconware Precision Industries, Ltd., Taiwan | Warpage preventing substrate |
EP1460687A1 (en) * | 2003-03-21 | 2004-09-22 | Texas Instruments Inc. | Recessed Wire Bonded Semiconductor Package Substrate |
-
2005
- 2005-01-12 DE DE102005001590A patent/DE102005001590B4/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6049129A (en) * | 1997-12-19 | 2000-04-11 | Texas Instruments Incorporated | Chip size integrated circuit package |
US6423622B1 (en) * | 1999-12-29 | 2002-07-23 | Advanced Semiconductor Engineering, Inc. | Lead-bond type chip package and manufacturing method thereof |
US20040065473A1 (en) * | 2002-10-08 | 2004-04-08 | Siliconware Precision Industries, Ltd., Taiwan | Warpage preventing substrate |
EP1460687A1 (en) * | 2003-03-21 | 2004-09-22 | Texas Instruments Inc. | Recessed Wire Bonded Semiconductor Package Substrate |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007014198A1 (en) * | 2007-03-24 | 2008-09-25 | Qimonda Ag | Integrated component |
US8143714B2 (en) | 2007-03-24 | 2012-03-27 | Qimonda Ag | Integrated circuit and method for producing the same |
DE102007014198B4 (en) * | 2007-03-24 | 2012-11-15 | Qimonda Ag | Integrated component and method for manufacturing an integrated component |
CN101740530A (en) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | Integrated circuit substrate |
Also Published As
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DE102005001590B4 (en) | 2007-08-16 |
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