DE102004058395A1 - Stackable semiconductor chip wiring method, involves applying filling material into semiconductor chip adjacent region, and applying conductive layer on chip front side, and connecting chip contacting region with contacting surfaces - Google Patents
Stackable semiconductor chip wiring method, involves applying filling material into semiconductor chip adjacent region, and applying conductive layer on chip front side, and connecting chip contacting region with contacting surfaces Download PDFInfo
- Publication number
- DE102004058395A1 DE102004058395A1 DE102004058395A DE102004058395A DE102004058395A1 DE 102004058395 A1 DE102004058395 A1 DE 102004058395A1 DE 102004058395 A DE102004058395 A DE 102004058395A DE 102004058395 A DE102004058395 A DE 102004058395A DE 102004058395 A1 DE102004058395 A1 DE 102004058395A1
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- chip
- semiconductor chip
- contacting
- horizontal surface
- filling
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract
Description
Die vorliegende Erfindung betrifft Verfahren zum Verdrahten von einem stapelbaren Halbleiterchip und eine Halbleitervorrichtung mit gestapelten Halbleiterchips, welche mit dem erfindungsgemäßen Verfahren herstellbar ist.The The present invention relates to methods of wiring one stackable semiconductor chip and a semiconductor device with stacked semiconductor chips, which with the inventive method can be produced.
Die Länge von Verdrahtungen zwischen Halbleiterchips in einer Halbleitervorrichtung ist mit maßgeblich für die Verlustleistung und auch die Probleme mit der Impedanzanpassung von Verdrahtungen für Hochfrequenzanwendungen. Die Länge der Verdrahtung kann neben einer Erhöhung der Integrationsdichte auf der Ebene eines einzelnen Halbleiterchips auch durch eine dichte Anordnung der Halbleiterchips auf einer Leiterplatte erreicht werden. Eine besonders dichte Anordnung lässt sich erreichen, wenn die Halbleiterchips gestapelt werden.The length of Wirings between semiconductor chips in a semiconductor device is relevant for the Power loss and also the problems with the impedance matching of wiring for High frequency applications. The length The wiring can be next to an increase in the integration density at the level of a single semiconductor chip also by a dense Arrangement of the semiconductor chips can be achieved on a circuit board. A particularly dense arrangement can be achieved if the Semiconductor chips are stacked.
Eine Stapelung von Halbleiterchips ist möglich, wenn eine Verdrahtungseinrichtung bereitgestellt wird, welche von einer Oberseite und einer Unterseite des Halbleiterchips kontaktierbar ist und zugleich mit einem Chipkontaktierungsbereich des Halbleiterchips verbunden ist.A Stacking of semiconductor chips is possible if a wiring device which is provided from a top and a bottom the semiconductor chip is contacted and at the same time with a Chipkontaktierungsbereich the semiconductor chip is connected.
Obwohl die vorliegende Erfindung anhand eines Verfahrens zum Verdrahten und Stapeln von mehreren Halbleiterchips beschrieben wird, ist dieses Verfahren nicht darauf beschränkt, sondern betrifft allgemein Verfahren zum Verdrahten von Halbleiterchips, wobei die Halbleiterchips optional auch gestapelt werden können.Even though the present invention by a method for wiring and stacking is described by a plurality of semiconductor chips, this is Method not limited to but generally relates to methods for wiring semiconductor chips, wherein the semiconductor chips can optionally also be stacked.
Zur
Erläuterung
der vorliegenden Problematik ist in
Das Verfahren zur Herstellung dieses Stapels ist jedoch sehr aufwändig. An jeden einzelnen Halbleiterchip müssen unter anderem die Bondingdrähte, der Interposer und die externen Kontakte angebracht werden. Eine parallele Verarbeitung vieler Halbleiterchips durch einige wenige Verfahrensschritte ist hierbei nicht möglich. Daher ergeben sich hohe Herstellungskosten für einen einzelnen Halbleiterchip, da diese nicht auf eine Mehrzahl an Halbleiterchips umgelegt werden können. Zudem ist die Verwendung der Interposer aufgrund derer hohen Anzahl an Herstellungs- und Verarbeitungsschritten unerwünscht.The However, a method for producing this stack is very complicated. At need every single semiconductor chip including the bonding wires, the interposer and the external contacts are attached. A Parallel processing of many semiconductor chips by a few Process steps is not possible here. Therefore, high results Production costs for a single semiconductor chip, since these are not on a plurality can be transferred to semiconductor chips. In addition, the use is the Interposer due to its high number of manufacturing and Processing steps undesirable.
Ein weiteres dem Anmelder bekanntes Verfahren bildet Durchkontaktierungen unmittelbar durch das Halbleitersubstrat des Halbleiterchips aus, um Kontaktierungsflächen auf der Oberseite und der Unterseite des Halbleiterchips miteinander zu verbinden. Jedoch ist das Einbringen ausreichend tiefer und durchgehender Öffnungen in das Halbleitersubstrat sehr aufwändig.One Another method known to the Applicant forms vias directly through the semiconductor substrate of the semiconductor chip to contacting surfaces on the top and bottom of the semiconductor chip with each other connect to. However, the insertion is sufficiently deep and through openings in the semiconductor substrate very expensive.
Es ist Aufgabe der vorliegenden Erfindung ein Verfahren zum Verdrahten von stapelbaren Halbleiterchips bereitzustellen, welches mit einer geringeren Anzahl an Verfahrensschritten und insbesondere mit einer geringeren Anzahl an seriell auszuführenden Verfahrensschritten auskommt. Es ist eine weitere Aufgabe der vorliegenden Erfindung aufwändige Strukturierungsprozesse und/oder Substrate zu vermeiden.It The object of the present invention is a method for wiring of stackable semiconductor chips to be provided with a less number of process steps and in particular with a fewer number of serially executed process steps gets along. It is another object of the present invention elaborate structuring processes and / or to avoid substrates.
Die vorgenannten Aufgaben werden durch das Verfahren mit den Merkmalen des Patentanspruchs 1 gelöst und durch die Halbleitervorrichtung mit den Merkmalen des Anspruchs 10.The The above objects are achieved by the method with the features of claim 1 and by the semiconductor device having the features of claim 10th
Das erfindungsgemäße Verfahren sieht folgende Verfahrenschritte vor, um mindestens einen stapelbaren Halbleiterchip zu verdrahten. In einem ersten Verfahrensschritt wird mindestens einer der Halbleiterchips mit dessen Rückseite auf einer horizontalen Fläche und zwischen Kontaktierungsflächen auf der horizontalen Fläche angeordnet, wobei eine strukturierte Vorderseite des Halbleiterchips einen Chipkontaktierungsbereich aufweist. In einem weiteren Verfahrensschritt wird eine Füllmasse auf der horizontalen Fläche in mindestens einem lateral an den Halbleiterchip angrenzendem Bereich aufgebracht, wobei mindestens eine der Kontaktierungsflächen auf der horizontalen Fläche nicht von der Füllmasse überdeckt wird. Nachfolgend wird eine leitfähige Schicht auf die strukturierte Vorderseite und auf die Füllmasse zum Verbinden des Chipkontaktierungsbereichs mit der Kontaktierungsfläche aufgebracht und strukturiert.The inventive method provides the following method steps to at least one stackable To wire the semiconductor chip. In a first process step is at least one of the semiconductor chips with its back on a horizontal surface and between contacting surfaces on the horizontal surface arranged, wherein a structured front side of the semiconductor chip has a chip contacting region. In a further process step becomes a filling material on the horizontal surface in at least one laterally adjacent to the semiconductor chip area applied, wherein at least one of the contacting surfaces the horizontal surface not covered by the filling compound becomes. Subsequently, a conductive layer on the structured Front and on the filling applied for connecting the chip contacting region with the contacting surface and structured.
Eine wesentliche Idee der vorliegenden Erfindung ist, dass mindestens eine Mehrzahl an Halbleiterchips auf der horizontalen Fläche angeordnet werden. Die nachfolgenden Verfahrensschritte werden dann parallel auf alle Halbleiterchips auf der horizontalen Fläche angewandt.A essential idea of the present invention is that at least a plurality of semiconductor chips are arranged on the horizontal surface. The subsequent process steps are then parallel to all Semiconductor chips applied on the horizontal surface.
Ein weitere Idee der vorliegenden Erfindung ist, dass die vertikale Verdrahtung in einem lateral an den Halbleiterchip angrenzenden Bereich vorgenommen wird. Dazu wird die Füllmasse angrenzend aufgebracht, wobei die Kontaktierungsfläche auf der horizontalen Fläche nicht bedeckt wird. Eine nachfolgende Herstellung der strukturierten leitfähigen Schicht kann dann den Chipkontaktierungsbereich mit der Kontaktierungsfläche verbinden. Der Vorteil dieses Verfahrens ist, dass sich die Füllmasse einfacher strukturieren lässt als das Halbleiterma terial des Halbleiterchips, insbesondere um eine Öffnung in das Substrat einzubringen, welche die Kontaktierungsfläche nicht bedeckt.One Another idea of the present invention is that the vertical Wiring in a laterally adjacent to the semiconductor chip Area is made. For this, the filling compound is applied adjacent, wherein the contacting surface on the horizontal surface not covered. A subsequent production of the structured conductive layer can then connect the chip contacting region with the contacting surface. The advantage of this method is that the filling mass easier to structure as the Halbleiterma material of the semiconductor chip, in particular to an opening into the substrate, which does not have the contacting surface covered.
Zur Begriffsklärung seien folgende Anmerkungen angeführt. Die Halbleiterchips sind vereinzelte ungehäuste Halbleiterchips. Die strukturierte Vorderseite der Halbleiterchips bezeichnet hierbei die Oberfläche, in deren unmittelbarer Nähe Halbleiterbauelemente, wie zum Beispiel Transistoren, des Halbleiterchips angeordnet sind. Eine Kontaktierung der Halbleiterbauelemente ist über den Chipkontaktierungsbereich möglich. Der Chipkontaktierungsbereich weist im allgemeinen eine Vielzahl an einzelnen Kontakten auf. Der Vorderseite liegt die Rückseite gegenüber. Die horizontale Fläche ist eine fiktive Fläche, welche weitgehend eben ist und nicht durch einen spezifischen Körper in ihrer Ausdehnung beschränkt ist. Die Kontaktierungsfläche ist die Oberfläche eines Abschnitts einer beliebigen leitfähigen Struktur in der horizontalen Fläche.to disambiguation the following comments are given. The semiconductor chips are isolated unhoused semiconductor chips. The structured Front side of the semiconductor chips denotes the surface, in their immediate vicinity Semiconductor devices, such as transistors, of the semiconductor chip are arranged. A contacting of the semiconductor components is via the Chip contacting possible. The chip contacting region generally has a plurality on individual contacts. The front is opposite the back. The horizontal surface is a fictitious surface, which is largely flat and not by a specific body in limited in their extent is. The contact surface is the surface a section of any conductive structure in the horizontal Area.
In den Unteransprüchen finden sich vorteilhafte Weiterbildungen und Ausgestaltungen des im Patentanspruch 1 angegebenen Verfahrens und der im Patentanspruch 10 angegebenen Vorrichtung, welche mit dem erfindungsgemäßen Verfahren hergestellt wird.In the dependent claims find advantageous developments and refinements of in claim 1 specified method and in the claim 10 specified device, which with the inventive method will be produced.
Eine besonders bevorzugte Weiterbildung des erfindungsgemäßen Verfahrens sieht vor, dass eine Abfolge der Verfahrensschritte mindestens einmal wiederholt wird, wobei die den Abfolgen zugehörigen horizontalen Flächen vertikal beabstandet sind, so dass die Halbleiterchips vertikal gestapelt werden. Eine der Kontaktierungsflächen in der horizontalen Fläche wird durch einen Abschnitt einer der strukturierten leitfähigen Schichten gebildet, welche in einer der vorhergehenden Abfolgen erstellt wurden.A Particularly preferred embodiment of the method according to the invention provides that a sequence of process steps at least once is repeated, wherein the sequences associated horizontal surfaces vertically are spaced so that the semiconductor chips stacked vertically become. One of the contacting surfaces in the horizontal surface becomes through a portion of one of the structured conductive layers formed, which were created in one of the previous sequences.
Eine Ausgestaltung des erfindungsgemäßen Verfahrens sieht vor, dass vor dem ersten Verfahrensschritt ein Träger mit einer Oberseite als horizontale Fläche bereitgestellt wird, wobei auf dem Träger mindestens eine obere Kontaktierungsfläche auf der Oberseite des Trägers als Kontaktierungsfläche der horizontalen Fläche vorgesehen ist. Der Träger bildet die Grundlage für einen Stapel von Halbleiterchips und gewährt die mechanische Stabilität. Zudem ist es möglich den Träger mit externen Kontaktierungen auf der Unterseite zu versehen und diese innerhalb des Trägers mit der Oberseite zu verbinden, um die Halbleitervorrichtung für eine Endmontage bereitzustellen.A Embodiment of the method according to the invention provides that before the first step, a carrier with an upper surface is provided as a horizontal surface, wherein on the carrier at least an upper contacting surface on the top of the carrier as a contact surface the horizontal surface is provided. The carrier forms the basis for a stack of semiconductor chips and provides the mechanical stability. moreover Is it possible the carrier to provide with external contacts on the bottom and these within the vehicle connect to the top to the semiconductor device for a final assembly provide.
Eine weitere Ausgestaltung des erfindungsgemäßen Verfahrens sieht vor, dass das Aufbringen der Füllmasse die folgenden zwei Verfahrensschritte aufweist, Aufbringen mindestens einer leitfähigen Erhebung auf mindestens eine der Kontaktierungsflächen der horizontalen Fläche und Auffüllen des lateral angrenzenden Bereichs mit der Füllmasse. Die leitfähigen Erhebung bildet somit eine vertikale Durchkontaktierung in der Füllmasse aus, um die strukturierte leitfähige Schicht mit der Kontaktierungsfläche auf der horizontalen Fläche zu verbinden. Vorteilhafterweise ragt die leitfähigen Erhebung aus der Füllmasse heraus, so dass ein sicherer Kontakt mit der leitfähigen Schicht gewährleistet ist.A Further embodiment of the method according to the invention provides that the application of the filling material the following two steps, applying at least a conductive Survey on at least one of the contact surfaces of the horizontal surface and padding the laterally adjacent area with the filling material. The conductive survey thus forms a vertical via in the filling off to the structured conductive Layer with the contact surface on the horizontal surface connect to. Advantageously, the conductive elevation protrudes from the filling compound out, leaving a secure contact with the conductive layer guaranteed is.
Eine besonders bevorzugte Ausgestaltung des erfindungsgemäßen Verfahrens sieht vor, dass das Aufbringen der Füllmasse die folgenden zwei Verfahrensschritte aufweist: Auffüllen des lateral angrenzenden Bereichs mit der Füllmasse und Einbringen einer durchgehenden vertikalen Öffnung in die Füllmasse von einer oberen Seite der Füllmasse aus bis zu der horizontalen Fläche dieser Abfolge oder einer vorhergehenden Abfolge. Die leitfähige Schicht scheidet sich dann auch in der vertikalen Öffnung ab und gewährleistet die Verbindung der Kontaktierungsfläche mit dem Chipkontaktierungsbereich. Vorteilhafterweise ist das Einbringen von Öffnungen in eine Füllmasse mit geringem Aufwand möglich. Bevorzugterweise weisen die vertikalen durchgehenden Öffnungen Seitenwände mit einer Neigung von weniger als 90° zur horizontalen Fläche auf. Dies erleichtert das Aufbringen der leitfähigen Schicht auf die Seitenwände.A particularly preferred embodiment of the method according to the invention provides that the application of the filling compound the following two steps has: fill up the laterally adjacent area with the filling compound and introducing a continuous vertical opening in the filling from an upper side of the filling out to the horizontal area this sequence or a previous sequence. The conductive layer separates then also in the vertical opening and guaranteed the connection of the contacting surface with the Chipkontaktierungsbereich. Advantageously, the introduction of openings in a filling material possible with little effort. Preferably, the vertical through openings side walls with an inclination of less than 90 ° to the horizontal surface. This facilitates the application of the conductive layer to the sidewalls.
Eine besondere Ausgestaltung des erfindungsgemäßen Verfahrens sieht vor, dass vor dem ersten Verfahrensschritt eine adhäsive Schicht auf die horizontale Fläche aufgebracht wird, um die Halbleiterchips zu fixieren.A particular embodiment of the method according to the invention provides that before the first process step, an adhesive layer on the horizontal area is applied to fix the semiconductor chips.
Eine Halbleitervorrichtung mit gestapelten Halbleiterchips weist auf: einen Träger, der eine Oberseite aufweist, auf welcher Kontaktierungsflächen angeordnet sind; mindestens zwei Halbleiterchips, welche auf vertikal zueinander beabstandeten Flächen angeordnet sind und jeweils eine strukturierte Vorderseite aufweisen, auf welcher ein Chipkontaktierungsbereich angeordnet ist, welcher von dem Träger abgewandt orientiert ist; eine Füllmasse, welche lateral angrenzend an dem Halbleiterchip vorgesehen ist und in welcher eine vertikale Verdrahtungseinrichtung vorgesehen ist, welche mit den Kontaktierungsflächen verbunden ist; und eine laterale Verdrahtungseinrichtung, welche den Chipkontaktierungsbereich mindestens eines Halbleiterchips mit dem vertikalen Verdrahtungseinrichtung verbindet.A semiconductor device having stacked semiconductor chips comprises: a carrier having an upper surface on which pads are arranged; at least two semiconductor chips, which are arranged on vertically spaced-apart surfaces and each have a structured front side, on which a Chipkontaktierungsbereich is arranged, which is oriented away from the carrier; a filler material provided laterally adjacent to the semiconductor chip and in which a vertical wiring device connected to the pads is provided; and a lateral ver a wiring device connecting the chip contacting region of at least one semiconductor chip to the vertical wiring device.
Ausführungsbeispiele der Erfindung sowie vorteilhafte Weiterbildungen sind in den Figuren der Zeichnungen dargestellt und in der nachfolgenden Beschreibung erläutert.embodiments The invention and advantageous developments are in the figures the drawings and in the following description explained.
Die schematischen Figuren zeigen:The schematic figures show:
In den Figuren bezeichnen gleiche Bezugszeichen gleiche oder funktionsgleiche Bauelemente.In the same reference numerals designate the same or functionally identical Components.
Mit
Bezug auf die
Mit
Bezug auf die
Nach
dem Bereitstellen des vorgenannten Trägers
In
an den Halbleiterchip
In
einem nachfolgenden Verfahrensschritt (
In
Das
Stapeln wird mit Bezug auf
In
einem der abschließenden
Verfahrensschritte (
Die meisten Verfahrensschritte werden für mehrere Stapel parallel ausgeführt, wie z. B. das Aufbringen der adhäsiven Schicht, das Aufbringen des Füllkörpers, das Aufbringen der leitenden Schicht und das Strukturieren der leitenden Schicht. Daher ist dieses Verfahren vorteilhafterweise sehr effizient.The Most process steps are performed in parallel for multiple stacks, such as z. B. the application of the adhesive Layer, applying the filler, the Applying the conductive layer and structuring the conductive Layer. Therefore, this method is advantageously very efficient.
In
den
Die
Umverdrahtungseinrichtungen
In
den
Wie
in den vorhergehenden Ausführungsformen
werden in dem ersten Bereich auf die Oberseite
In
einem weiteren Verfahrensschritt (
Eine
Stapelung der Halbleiterchips ist in
In
Die
horizontalen Fläche
der ersten Ausführungsform
findet sich in den weiteren Ausführungsformen
wieder. Hierbei wird die horizontalen Fläche
Obwohl die vorliegende Erfindung anhand von vier bevorzugten Ausführungsbeispielen beschrieben wurde, ist die Erfindung darauf nicht beschränkt.Even though the present invention with reference to four preferred embodiments has been described, the invention is not limited thereto.
Insbesondere ist es einem Fachmann offensichtlich, dass die Reihenfolge der Ausführung der einzelnen Verfahrensschritte, wie in den Ausführungsbeispielen beschrieben, in vielfältiger Weise geändert werden kann.Especially It is obvious to a person skilled in the art that the order of execution of the individual Method steps, as described in the exemplary embodiments, in more diverse Changed way can be.
Zudem ist denkbar, das Füllmaterial so aufzudrucken, dass die oberen Kontaktierungsflächen nicht bedeckt werden, um einen abschließenden Strukturierungsschritt einzusparen.moreover is conceivable, the filler printed so that the upper contact surfaces not be covered to a final structuring step save.
- 1, 11, 21, 311, 11, 21, 31
- HalbleiterchipSemiconductor chip
- 2, 12, 22, 322, 12, 22, 32
- ChipkontaktierungsbereichChipkontaktierungsbereich
- 3, 13, 23, 33, 433, 13, 23, 33, 43
- Füllmassefilling compound
- 4, 14 4, 14
- Freibereichoutdoor Space
- 5, 15, 25, 35, 455, 15, 25, 35, 45
- Verdrahtungseinrichtungwiring means
- 6, 166 16
- Kontaktierungsflächecontacting surface
- 2626
- obere Kontaktierungsflächeupper contacting surface
- 27, 3727 37
- adhäsive Schichtadhesive layer
- 28, 3828 38
- durchgehende vertikale Öffnungthrough vertical opening
- 29, 3929 39
- leitfähige Erhebungconductive survey
- 100, 110, 120, 130100 110, 120, 130
- strukturierte Vorderseitestructured front
- 101, 111, 121, 131101 111, 121, 131
- Rückseiteback
- 128, 138, 148128 138, 148
- SeitenwandSide wall
- 200, 210200 210
- horizontalen Flächehorizontal area
- 201201
- Grenzlinieboundary line
- 220220
- Oberseitetop
- 221221
- Unterseitebottom
- 300300
- Trägercarrier
- 301301
- untere Kontaktierungsflächelower contacting surface
- 302302
- interne Verdrahtungseinrichtunginternal wiring means
- 303303
- externer Kontaktexternal Contact
- 401401
- HalbleiterchipSemiconductor chip
- 402402
- ChipkontaktierungsbereichChipkontaktierungsbereich
- 403403
- Interposerinterposer
- 405405
- Verdrahtungseinrichtungwiring means
- 406406
- Bondingdrahtbonding wire
- 407407
- adhäsive Schichtadhesive layer
- 408408
- externer Kontaktexternal Contact
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE102004058395A DE102004058395A1 (en) | 2004-12-03 | 2004-12-03 | Stackable semiconductor chip wiring method, involves applying filling material into semiconductor chip adjacent region, and applying conductive layer on chip front side, and connecting chip contacting region with contacting surfaces |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004058395A DE102004058395A1 (en) | 2004-12-03 | 2004-12-03 | Stackable semiconductor chip wiring method, involves applying filling material into semiconductor chip adjacent region, and applying conductive layer on chip front side, and connecting chip contacting region with contacting surfaces |
Publications (1)
Publication Number | Publication Date |
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DE102004058395A1 true DE102004058395A1 (en) | 2006-06-08 |
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DE102004058395A Ceased DE102004058395A1 (en) | 2004-12-03 | 2004-12-03 | Stackable semiconductor chip wiring method, involves applying filling material into semiconductor chip adjacent region, and applying conductive layer on chip front side, and connecting chip contacting region with contacting surfaces |
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DE (1) | DE102004058395A1 (en) |
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2004
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EP0987760A2 (en) * | 1998-08-31 | 2000-03-22 | General Electric Company | Multimodule interconnect structure and process |
WO2001037338A2 (en) * | 1999-11-16 | 2001-05-25 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Method for integrating a chip in a printed board and integrated circuit |
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EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
WO2011042256A1 (en) * | 2009-10-09 | 2011-04-14 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
CN102696105A (en) * | 2009-10-09 | 2012-09-26 | 意法爱立信有限公司 | Chip package with a chip embedded in a wiring body |
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