DE102004044882B3 - Semiconductor module having stacked semiconductor devices and electrical interconnects between the stacked semiconductor devices - Google Patents

Abstract

The invention relates to a semiconductor module (3) with stacked semiconductor components (7, 8) and electrical connection elements (31) between the stacked semiconductor components (7, 8), the stacked semiconductor components (7, 8) having wiring structures (25 ) exhibit. On at least one of its housing outer edge sides (26, 27) outer edge terminals (28) are arranged. These outer edge terminals (28) are connected via wiring structures (25) to inner terminals (29) of the semiconductor devices (7, 8), wherein the semiconductor module (3) on at least one outer side (30) of a grid of the electrical aligned vertically to the wiring structures (25) Connecting elements (31) which are cohesively and electrically connected to the outer edge terminals (28).

Description

Semiconductor module with stacked semiconductor devices and electrical connectors between the stacked semiconductor devices

The The invention relates to a semiconductor module with stacked semiconductor devices and electrical connection elements between the stacked semiconductor devices. The stacked semiconductor devices point to their Bottom side wiring structures to be connected to each other. Such substrate-based housing BGA packages (ball grid array - housing) called and have connected because of their good electrical properties with a low form factor and comparatively low production costs meanwhile found a wide application. Increasingly, BGA packages are also for memory semiconductor components used. Partially there are modern storage architectures, such as the DDR2 semiconductor devices (Double Data Rate 2 semiconductor devices), the only with BGA packages can be realized because these meet the necessary electrical requirements to a doubling of the data rate from 200 to 400 megabits per second to reach.

To the Achieving a high stack density will cause the stacking of semiconductor devices becoming more interesting to semiconductor modules, with two trends have emerged, on the one hand a stack of several internal Semiconductor chips within a housing, which also "stacked the FBGA" (Fine Pitch Ball Grid Array), and on the other hand. a stack of two or more individual housings each other. These solutions have different disadvantages, the internal semiconductor chip stack testing problems because the individual semiconductor chips after their final assembly are no longer testable, and stacking of individual housings produces high Costs due to the different measures needed to connect the finished semiconductor components must be taken with each other.

The previously known solutions for stacking of two or more individual housings have the following disadvantages. In a first solution will be thin single substrates with special peripheral arrangements of ball contacts one above the other stacked. This requires expensive materials and special ones Handling in the production necessary. Also the test of the individual elements is mechanically demanding, since no standard ball contacts with permanent increase in area possible are.

One further solution provides a redistribution foil that goes from extra solder balls to the top one stacked semiconductor device leads, for what, however an expensive lower base semiconductor component has to be manufactured. A triple "reflow" provided in this structure results in additional Manufacturing problems. Another problem solution provides that an upper Semiconductor device carries a separate small circuit board, which has solder contacts is connected to the main circuit board of the semiconductor module. there Difficulties arise in the surface mounting of the solder contacts. It also gives a big one height and an additional one Increase in area, the space requirements of the semiconductor module stacked semiconductor components increased.

From the DE 102 59 221 A1 An electronic component with a stack of semiconductor chips is known, in which a first semiconductor chip is arranged on a rewiring substrate and at least one stack semiconductor chip is arranged on the first semiconductor chip. Between the semiconductor chips a rewiring layer is arranged. The contact surfaces of the semiconductor chips are connected via the rewiring layer and the rewiring substrate with external contacts of the component.

From the JP 2004221372 A is a semiconductor device is known, the rewiring substrates are provided for space-saving connection between multiple layers with vertical grooves. Subsequently, the grooves are filled or lined with a conductive material.

Another solution to the stacking problem is from the document DE 101 38 278 C1 known. For stacking semiconductor devices conventional semiconductor devices with BGH or LBGA housing (large ball grid array) are provided with additional flexible len Umverdaltungsungsfolien. These additional redistribution foils are larger in area than the semiconductor devices to be stacked and protrude beyond the edge of the semiconductor devices so that they can be bent toward a semiconductor device of a semiconductor device stack disposed underneath and electrically connected to the underlying semiconductor device via the flexible film.

One Semiconductor module with such stacked semiconductor devices has the disadvantage that the semiconductor devices are not with the lowest possible Space requirements can be stacked, especially the bent rewiring foil has a bending radius requires, which can not be exceeded, without microcracks in the rewiring lines arranged on the rewiring foil to risk.

The object of the invention is a semiconductor specify module with semiconductor devices or in the manufacturing process for this, with a stacking is not limited to a few predetermined patterns of semiconductor devices, but in which the arrangement and assignment of connecting external contacts can be varied as desired while minimizing the space requirement and the space requirement of a semiconductor module in particular to reduce the space requirement of a memory module made of DRAM semiconductor components and / or microprocessors.

Is solved the object with the subject of independent claims 1 and 2. Advantageous developments of the invention will become apparent from the dependent Claims.

According to the invention is a Semiconductor module provided with semiconductor devices, wherein the semiconductor devices stacked on top of each other. The bottoms of the semiconductor devices have rewiring structures and have at least a housing outside edge side Outer edge connectors. These outer edge connections are over the Redistribution structures with internal connections of the semiconductor components electrically connected. On at least one outer side, the semiconductor module a vertically aligned with the wiring structures of the semiconductor devices Grid of electrical connectors on. This electrical Connecting elements are firmly bonded to the outer edge connections and electrically connected.

This Semiconductor module has the advantage that the three-dimensional wiring by the horizontally arranged wiring structures of each semiconductor device and by additional Outside edge connections, the when stacking the main conductor components are aligned with each other, no additional space requirements for the Connecting these edge connections in the vertical direction is required. In addition, thin connecting wires or Connecting webs as connecting elements, to rectilinear the outer edge terminals of the Semiconductor components to interconnect. Because these fasteners on the outside the semiconductor module can be located in case of malfunction Semiconductor module are decomposed and defective semiconductor devices can accordingly be replaced.

Also the individual testing of the semiconductor components before assembly of the Semiconductor module is unrestricted possible. All Heat cycle tests as well as vibration tests with the most different loads are in the assembly of semiconductor modules in each of the single semiconductor devices, to be stacked, possible.

The Attaching vertical fasteners to the provided outer edge terminals is unproblematic and can be realized with low production costs become. Also a laying of internal connections of the semiconductor components on the edge sides of the semiconductor devices, unless they are anyway already exist in the semiconductor devices, no costly Action. Thus, a semiconductor module can be cost-effective in the simplest way any storage capacity is made by stacking DRAMs. But it is just as possible, memory elements to couple with logic devices by adding additional logic integrated circuits, such as microprocessors, in the semiconductor module as Stackable semiconductor device can be installed.

In a first embodiment the invention, the electrical connection elements are separated Through contacts on an outer edge a wiring substrate of one of the stacked semiconductor devices. As a matter of principle each semiconductor device in BGA technology BGA = ball grid array or FBGA technology FBGA = fine-pitch BGA such a wiring substrate Having on its underside, it is possible with the closest to disposal standing and realizable connection grid on the circumference of the Wiring substrate that is sawn out of a benefit to provide a maximum number of vias on the traces of the benefit. When dividing the utility into individual wiring substrates for the semiconductor devices, then arises a variety of outer edge connections in Shape of halved vias. These outer edge connections in the form of separated through contacts can be connected to internal connections at the same time an internal stack of semiconductor chips connect to the outer edge connections.

Thus, even with this first embodiment of the invention, a maximum increase of the storage capacity can be provided, for example, a first semiconductor chip can be fixed with its rear side on the wiring substrate and with its active upper side, the outer edge connections can be achieved via bonding connections to a wiring structure of the wiring substrate. Since logic semiconductor chips have their contact areas in the edge region, the center region of the logic chip can be used to adhere an insulating spacer plate and to accommodate a memory chip with a central bonding channel on this spacer plate. The upper side of the stacked semiconductor chip with a central bonding channel may in turn have a rewiring structure, in order in turn to lead the electrical connections from the electrodes in the central bonding channel to internal connections in the edge region of the stacked semiconductor chip. Of these internal connections in the edge region of the stacked semiconductor chip then again bond wires to ent lead speaking contact pads on the wiring substrate, which in turn has a wiring structure, which is in communication with the outer edge terminals of the semiconductor module.

at a further preferred embodiment The invention has the housing outer edge the stacked semiconductor devices vertical to the wiring structures molded grooves on. These molded grooves have the outer grooves of the individual semiconductor devices, so that by arranging Wire bars in the molded grooves a vertical connection between the semiconductor devices can be made in a confined space. The number of stacked semiconductor devices is arbitrary, Preferably, however, two semiconductor devices with internal Chip stacks using this technique Outside edge connections and corresponding wire webs connected.

In a further embodiment the invention, several fasteners using a Flat conductor frame held in position, wherein the leadframe has a grid of wire webs between transverse webs. at This semiconductor module are first on the Crossbars all fasteners shorted in the form of wire bridges, allowing for transportation and for the transfer of the modules can be beneficial. Just before the Using the semiconductor modules, the crossbars are removed so that now the wire ridges the individual stacked semiconductor devices connect vertically with each other.

As already mentioned, Preferably, the stacked semiconductor devices also have internal Semiconductor chip stacks that over a common wiring structure of the stacked semiconductor device and on the Outside edge connections of the Stacked semiconductor device with the connecting elements of Semiconductor module communicate electrically. With this structure can the storage capacity stacked Semiconductor devices advantageously further increased.

Preferably has the internal chip stack semiconductor chips on their have active surfaces in a central area contact surfaces. These contact surfaces in cental range can be double row be arranged and are about Conductor tracks with inner connection surfaces on edge areas of the Semiconductor chips electrically connected. Unlike memory components with central bonding channel in a wiring foil or in one Wiring substrate, these semiconductor chips have neither a wiring foil still a wiring substrate, but tracks, by a structured metal coating on the active top of the Semiconductor chips are formed. On the arranged in the center contact surfaces can thus over the arranged in the edge region inner pads and the tracks of the Metal coating accessed from the edge of the semiconductor chips become. The inner connection surfaces can for the chip stack as bonding surfaces be used.

In a further embodiment According to the invention, the semiconductor module has external contacts on its underside on. These are over a wiring substrate and over Outer edge terminals of the wiring substrate with the wire bars arranged vertically to the wiring substrate electrically connected to the semiconductor module. Thus, it is possible that Semiconductor module on a parent Circuit board with a variety of located on the bottom external contacts connect and at the same time through the vertically aligned wire webs the circuit capacity the stacked semiconductor devices to the arranged on the bottom external contacts to disposal to deliver.

In a further preferred embodiment The invention features the semiconductor module as external contact on the underside of the wiring substrate uniformly distributed solder balls. With these solder balls is a simple surface mounting of the semiconductor module on a parent circuit substrate possible, by a short-time soldering process carried out becomes.

The storage capacity The individual stacked DRAMs may preferably be in the gigabere range. Such DRAMs have the advantage that they are embedded in flat, large-area plastic housings are so large accordingly Edge sides a mounting of a variety of edge contact terminals and thus attaching a plurality of vertically aligned wire webs enable.

In a further preferred embodiment it is provided that the semiconductor module is a stacked semiconductor device having a wiring substrate, which in turn is internal Connection contacts solder balls has. With these solder balls However, the height is of the semiconductor module increases, so solutions without solder balls on the wiring substrates of the stacked semiconductor devices to be favoured.

In a further preferred embodiment, the wiring structure may be accommodated on a wiring film, in particular if the semiconductor module has a stacked component memory component with a central bonding channel. The wiring film allows extremely dense-packed semiconductor modules if the wiring film is designed to accept outer edge terminals Provides that are contactable via vertical wire webs.

One Method for producing a semiconductor module with semiconductor components, which are stacked on top of each other and on their undersides wiring structures have, is characterized by the following process steps: First, individual Semiconductor devices with outer edge connections on at least one of its outer sides produced. Subsequently The semiconductor devices are aligned by aligning the outer edge terminals in the vertical direction stacked. After all become the one above the other arranged outer edge connections Applying connecting elements to the outer edge terminals electrically connected with each other.

at These connection steps, the lower semiconductor device already on the bottom distributed solder balls as external contacts on external contact surfaces of a Have wiring substrate. The addition of the external contact surfaces of each semiconductor device to the outer edge to leading tracks, to realize outer edge connections, can already during the creation of the layout for the wiring structure of the wiring substrate become. Furthermore can already while making the wiring substrate using a Benefit to be provided on the edge sides vias, the halved when separating the benefit and thus first outer edge connections or vertical fasteners for form an internal semiconductor chip stack.

Furthermore can at least on a housing outside edge side the semiconductor devices to be stacked vertically to the wiring structures and in the positions of the outer edge connections grooves be formed for receiving wire webs. This molding can preferably be carried out in the injection molding process, by inserting wire webs into the injection mold so that when forming at predetermined positions in the edge sides of the Semiconductor components grooves are present in the then wire bridges of the semiconductor module can be introduced.

The Connect one above the other arranged outer edge connections through Applying wire bars on the outer edge connections can using laser welding technology or by soldering or by adhesive bonding with a conductive adhesive. The cohesive Compounds have been proven in semiconductor technology and make a reliable Process base for the production of semiconductor modules.

In summary It should be noted that by providing a simple lead frame, the flat conductor for has the attachment of wire webs, a cost effective solution of Stack problem is provided. This is the leadframe not horizontally but vertically provided and connects specially modified substrate connections in the form of outer edge connections one above the other. In this case, the laser welding is advantageously used, especially this Processes even when stacking other semiconductor devices already successful recorded.

The Modification of the required wiring substrate is relative low. From provided external contact pads each semiconductor device, on which otherwise solder balls are provided, are additional Connecting cables led to the edge area, what with a large number Semiconductor devices without bond channel is already provided. at housings with bond channel can These lines can be added to the edge areas without difficulty. At the housing edge flow the additional Conductor tracks of the wiring structure in corresponding vias through the wiring substrate and can additionally by gilding their surface properties be improved.

at Singulating the individual housing from a designated common substrate, such as a benefit, to several Semiconductor devices become the contact holes in the peripheral area so cut through in the middle, that the inner radius is exposed. Advantageously separates a singulation two housings, so that the exposed halved vias as outer edge terminals and serve as vertical connection elements for internal semiconductor chip stacks can.

In a further embodiment The invention are in an injection molding tool or "mold tool" corresponding cable webs the positions above the outer edge connections, so these bars for it make sure that no molding compound settles there. By the molding resulting groove-shaped Recesses will be the shape of the outer edge connections for the connection a corresponding vertically equipped flat conductor frame extended, what kind of the attachment of vertical conductor bars is an advantage.

Semiconductor devices prepared in this manner can now be assembled to form a semiconductor module for stacking two and more substrate-based packages. The decisive factor is that the edge side contacts to be connected lie one above the other at the same edge positions. The stack partners themselves may have two or more similar components with the same chips or memory chips or they may be two or more similar devices with different semiconductor chips, for Example in a multi-chip package, or in a "stacked the FBGA" exhibit. Finally, it is possible that various types of semiconductor devices, such as logic semiconductor devices and memory semiconductor devices or any other combination of these semiconductor devices, are stacked together.

The individual stack partner can again with solder balls equipped be tested with a standard process. On the other hand it is also possible over the External contact surfaces, on which such external contacts are arranged by semiconductor devices, corresponding needle contacts apply during testing and thus also semiconductor components without To test such solder balls in a simple way, before a semiconductor module is compiled.

to Making the stack connection are the individual partners so aligned that the cavities or through contacts (either only consisting of vias or by vertical recesses or grooves extended contact holes having) one above the other are arranged horizontally. Furthermore, a preformed leadframe is over all Contacts are laid and by laser welding are the individual connections closed with the outer edge contact terminals and by laser cutting are corresponding transverse webs or mounting rails of the lead frame for separated the wire webs. After all contacts connected are, the stacked semiconductor module can be retested and be used afterwards.

• 1. eine kostengünstige Stapeltechnologie;
• 2. ein Nutzbarmachen von substratbasierten Gehäusen, wie z.B. FBGA-Gehäuse für die Stapeltechnologie;
• 3. eine Erhöhung der elektrischen Leistungsfähigkeit;
• 4. eine Verringerung der vertikalen Größenausdehnung eines Halbleitermoduls;
• 5. ein Vorabtesten der einzelnen zu stapelnden Halbleiterbauteile, sodass ein verminderter Ausschuss für die Halbleitermodule auftritt;
• 6. eine hohe Vielfalt von Stapelmöglichkeiten durch Einzelchipgehäuse, Multichipgehäuse und Kombinationen derselben.

In summary, the following advantages result:

• 1. a cost-effective stacking technology;
• 2. Utilization of substrate-based packages, such as FBGA packages for stacking technology;
• 3. an increase in electrical performance;
• 4. a reduction in the vertical size extent of a semiconductor module;
• 5. pre-scanning the individual semiconductor devices to be stacked so that a reduced rejection of the semiconductor modules occurs;
• 6. A wide variety of stacking capabilities through single-chip packages, multi-chip packages, and combinations thereof.

With This technology will double or quadruple the storage density compared to standard storage densities possible. For example, 120 force vertical connections result, for example, 30 vias per edge side of the semiconductor components, with a connection grid of 0.65 mm results in a minimum length to such a number to accommodate of wire webs on the edge sides, of 20 mm. The for Such stacking in a semiconductor module interesting memory chips are the chips with big ones Storage density, for example, from 1 gigabit to 2 gigabit, since these Semiconductor chips already have an edge length of greater than 18 mm. Consequently Also, the terminal grid is sufficient to provide sufficient outer edge contact terminals.

The The invention will now be described with reference to the accompanying figures.

1 shows a schematic cross section through a semiconductor module of a first embodiment of the invention;

2 shows a schematic cross section through a semiconductor module of a second embodiment of the invention;

3 shows a schematic plan view of a vertically oriented flat conductor frame with electrical connection elements;

4 shows a schematic cross section through a semiconductor module of a third embodiment of the invention;

5 shows a schematic cross section through a semiconductor module of a fourth embodiment of the invention;

6 shows a schematic cross section through a semiconductor module of a fifth embodiment of the invention.

1 shows a schematic cross section through a semiconductor module 1 a first embodiment of the invention. This semiconductor module 1 has an internal semiconductor chip stack 40 from the semiconductor chips 13 and 14 on. Between the semiconductor chips 13 and 14 is a spacer insulating layer 52 arranged as the semiconductor chips 13 and 14 have identical external dimensions. Both semiconductor chips 13 and 14 have central and double row contact surfaces 54 on the active top side of the semiconductor chips 13 and 14 on. From the contact surfaces 54 in the central area 44 lead tracks 48 a wiring structure formed by a patterned metal coating on the active tops of the semiconductor chips 13 and 14 is connected to internal connections 29 in the edge regions of the semiconductor chips 13 and 14 from where the inner shorts 29 via bonds 49 with a wiring structure 25 on a wiring substrate 34 are connected.

The wiring substrate 34 points to be ner underside 41 external contacts 42 on, on external contact surfaces 50 are arranged. The external contact surfaces 50 stand over lines of the bottom 41 and through contacts 51 with the wiring structure 25 electrically connected. At the outer edge 33 of the wiring substrate 34 are severed vias 32 arranged, in turn, both with the bonds 49 or with the external contacts 42 are electrically connected. Thus, at least on these separated through contacts 32 , which are also called hollow contacts, on the outer edge 33 of the wiring substrate 34 three contact levels together, namely the contact level of the external contacts 42 as well as the contact level of the internal connections 29 of the two semiconductor chips 13 and 14 , In addition, the contacts of the three contact levels can additionally via the vias 51 be closed together.

The sectional drawings A, B, C and D, the under 1 With 1A . 1B . 1C and 1D are characterized, the different structure of the outer edge 33 in the area of the wiring substrate 34 and the structure of the outside 30 in the area of the plastic housing 47 clear. In this first embodiment of the invention, only the hollow or through contacts 32 in the edge region on a groove or grooves, while the outside 30 of the semiconductor module 1 like it 1B and 1C show is completely smooth.

To improve the resistance to corrosion and oxidation, the vias 32 made of a copper alloy with a gold layer in the outer edge 33 of the wiring substrate 34 be coated. The advantage of these outer edge connections 28 This first embodiment of the invention is that a plurality of vias 32 in the edge region of the semiconductor device 6 can be attached so that about these outer edge connections 28 from separated through contacts 32 a test is possible without the solder balls 43 must be charged. Even with a surface mount of this semiconductor module 1 on a parent circuit board can still on the outside edge connections 28 on the outside of the case 26 and 27 be accessed, which is advantageous when testing the component.

2 shows a schematic cross section through a semiconductor module 2 a second embodiment of the invention. Components with the same functions as in 1 are denoted by like reference numerals and will not be discussed separately. Also this semiconductor module 2 has an internal semiconductor chip stack 40 with memory chips of a few gigabits. The difference between the embodiment according to 1 and the embodiment according to 2 is at the sectional drawings 2A . 2 B . 2C and 2D visible, noticeable. In this embodiment of the invention, grooves or recesses are both in the area of the wiring substrate 34 as well as in the area of the plastic housing 47 provided, like the 2 B and 2C demonstrate. These recesses are filled with wire webs 36 as vertical connecting elements 31 , about which another semiconductor device with an internal semiconductor chip stack 40 as it eg 1 shows, to the present semiconductor module 1 can be coupled.

By the vertical opposite the wiring structure 25 aligned wire webs 36 For example, it is possible to establish a connection between semiconductor components to be stacked in the smallest possible space. For this purpose, the recesses or grooves 35 in the plastic housing 47 be prepared by that in an injection mold or an embossing mold corresponding cable webs 36 are inserted so that when removing the form of these wire webs 36 either poured immediately or in the resulting grooves 35 then be inserted. The electrical connection of the cable webs 36 with the outer edge connections 28 in the form of split vias 32 can be achieved by laser welding. This is the most reliable cohesive process with which the wire webs 36 with the separated through contacts 32 of the wiring substrate 34 can be connected. In general, it is also possible, these wire bridges 36 on the separated vias 32 to solder or electrically connect them with a conductive adhesive.

3 shows a schematic plan view of a vertically oriented leadframe 37 with electrical connection elements 31 , To simultaneously several fasteners 31 to be applied to the housing outer edge sides of a semiconductor module in the grooves provided, are the electrical connection elements 31 in the form of wire webs 36 via a leadframe 37 held grid-shaped. The lead frame 37 has transverse webs 39 on which the wire webs 36 hold in their position. The grid 38 can first be placed completely on the housing outer edge sides of a semiconductor module with stacked semiconductor devices and then connected to the provided outer edge terminals. The short circuit caused by the crossbars 39 arises after attaching the frame and contacting the outer edge contacts 32 by laser separation of the supernatant 46 of the grid 38 be removed.

4 shows a schematic cross section through a semiconductor module 3 a third embodiment of the invention. The lower semiconductor device 7 corresponds to the semiconductor components 6 , in the 1 and 2 be shown, and has an in a semiconductor chip stack 40 with the semiconductor chips 15 and 16 on. The stacked semiconductor device 8th with its internal semiconductor chip stack 40 the semiconductor chips 17 and 18 is on top of the lower semiconductor device 8th glued directly and has no solder balls or solder balls, especially the two stacked semiconductor chips 17 and 18 over their internal connections 29 and the wiring structure 25 with corresponding outer edge connections 28 connected so that solder balls 43 on the external contact surfaces 50 of the stacked semiconductor device 8th are superfluous. The electrical connection to the upper and lower semiconductor device takes place in this case by connecting elements 31 , which are formed as a flat conductor. By eliminating solder balls between the two semiconductor devices 7 and 8th becomes the entire semiconductor module 3 reduced in height h.

5 shows a schematic cross section through a semiconductor module 4 a fourth embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately.

This fourth embodiment of the invention largely corresponds to the third embodiment of the invention according to 4 However, the height h of the semiconductor module 4 bigger, because solder balls 43 of the stacked semiconductor device 9 were maintained. With the internal semiconductor chip stack 40 from the semiconductor chips 19 and 20 is the stacked semiconductor device 9 the same as the embodiment according to 2 , Also the basic semiconductor component 10 has an internal semiconductor chip stack 40 with the semiconductor chips 21 and 22 and corresponds in its structure to the semiconductor device 6 , this in 2 will be shown. The advantage of this semiconductor module is that no modifications and changes to the semiconductor devices to be stacked 9 and 10 must be performed so that similar semiconductor devices 9 and 10 stacked on top of each other and with each other via the cable bars 36 on the outside 30 of the semiconductor module 4 can be connected. This brings advantages in testing the semiconductor devices 9 ,

6 shows a schematic cross section through a semiconductor module 5 a fifth embodiment of the invention, in which case two semiconductor devices 11 and 12 stacked on each other, the semiconductor chips 23 and 24 with a central bonding channel 44 exhibit. In the central bond channel 44 are two-row contact surfaces 54 arranged via bonding wires 49 with tracks 48 on a wiring foil 45 are connected. On the wiring foil 45 are external contacts 42 in the form of solder balls 43 in the case of the lower semiconductor device 11 arranged. The upper stacked semiconductor device 12 in contrast has no solder balls 43 on.

The arranged in two rows contact surfaces 54 are here via bonding wires 49 with a wiring structure 25 a central bond channel 55 connected directly to outside edge connections 28 are connected and over the fasteners 31 in the form of wire webs 36 on the outside of the case sides 26 and 27 with the external contacts 42 of the lower semiconductor device 11 of the semiconductor module 5 are connected. Between the semiconductor components 11 and 12 is an adhesive mass 53 arranged with the stacked semiconductor device 12 on the base semiconductor device 11 is fixed. The difference of the semiconductor module 5 to the previous embodiments of the invention is that the central bonding channels 55 the stacked semiconductor devices 11 and 12 in the direction of the external contacts 42 of the semiconductor module 5 are aligned and therefore can be dispensed with a self-supporting wiring substrate for semiconductor chips, especially since no internal semiconductor chip stack is provided in this embodiment of the invention.

1

Semiconductor module (1st embodiment)

2

Semiconductor module (2nd embodiment)

3

Semiconductor module (3rd embodiment)

4

Semiconductor module (4th embodiment)

5

Semiconductor module (5th embodiment)

6

Semiconductor device (1st and 2nd Embodiment)

7.8

Semiconductor components (3rd embodiment)

9.10

Semiconductor components (4th embodiment)

11.12

Semiconductor components (5th embodiment)

13.14

Semiconductor chips (1st and 2nd Embodiment)

15-18

Semiconductor chips (3rd embodiment)

19-22

Semiconductor chips (4th embodiment)

23-24

Semiconductor chips (5th embodiment)

25

wiring structure of the semiconductor device

26.27

Housing outer edge side

28

Outer edge connector

29

Interior pads

30

outside of the semiconductor module

31

connecting element

32

by contact or hollow contacts

33

outer edge a wiring substrate

34

wiring substrate

35

groove

36

conduction web

37

Leadframe

38

grid

39

crosspiece

40

internal Semiconductor chip stack (1st to 4th embodiments)

41

bottom of the semiconductor module

42

external contacts

43

solder ball

1

44

centrally Area

45

wiring film

46

Got over the lead pins

47

Plastic housing

48

conductor path

49

bond or bonding wires

50

External contact areas

51

through contacts of the wiring substrate

52

distance-maintaining layer

53

adhesive composition

54

contact area

55

centrally Bond channel

H

Height of the semiconductor module

Claims (18)

Semiconductor module with semiconductor components ( 6 - 12 ), wherein the semiconductor components ( 6 - 12 ) are stacked on top of each other and on their underside wiring structures ( 25 ) and on at least one housing outer edge side ( 26 . 27 ) Outer edge connections ( 28 ), wherein the outer edge connections ( 28 ) via the wiring structures ( 25 ) with internal connections ( 29 ) of the semiconductor components ( 6 - 12 ) and wherein the semiconductor module ( 1 - 5 ) on at least one outer side ( 30 ) a vertical to the wiring structures ( 25 ) aligned grid ( 38 ) electrical connection elements ( 31 ), which are connected to the outer edge connections ( 28 ) are cohesively and electrically connected. Semiconductor module according to claim 1, characterized in that the electrical connection elements ( 31 ) separated contacts ( 32 ) on an outer edge ( 33 ) of a wiring substrate ( 34 ) of the stacked semiconductor devices ( 6 - 10 ) exhibit. Semiconductor module according to claim 1 or claim 2, characterized in that the housing outer edge sides ( 26 . 27 ) of the stacked semiconductor devices ( 6 - 12 ) vertical to the wiring structures ( 25 ) molded grooves ( 35 ), in which cable webs ( 36 ) as electrical connection elements ( 31 ) and with the outer edge connections ( 28 ) are electrically connected. Semiconductor module according to one of the preceding claims, characterized in that a plurality of connecting elements ( 31 ) using a leadframe ( 37 ) are held in place and a grid ( 38 ) from wire webs ( 36 ) between transverse webs ( 39 ) exhibit. Semiconductor module according to one of the preceding claims, characterized in that the stacked semiconductor components ( 6 - 10 ) internal semiconductor chip stacks ( 40 ), which via a common wiring structure ( 25 ) of the stacked semiconductor device ( 6 - 12 ) and via the outer edge connections ( 28 ) of the stacked semiconductor device ( 6 - 12 ) with the connecting elements ( 31 ) of the semiconductor module ( 1 - 5 ) communicate electrically. Semiconductor module according to one of the preceding claims, characterized in that the semiconductor module ( 1 - 5 ) on its underside ( 41 ) External contacts ( 42 ) via a wiring substrate ( 34 ) and outer edge connections ( 28 ) of the wiring substrate ( 34 ) with the vertical to the wiring substrate ( 34 ) arranged wire webs ( 36 ) of the semiconductor module ( 1 - 5 ) communicate electrically. Semiconductor module according to claim 5, characterized in that the internal chip stack ( 40 ) Semiconductor chips ( 13 . 14 ) on its active upper side in a central area ( 44 ) Contact surfaces ( 54 ), which via conductor tracks ( 48 ) with inner connection surfaces ( 29 ) on edge regions of the semiconductor chips ( 13 . 14 ), the printed conductors ( 48 ) of a structured metal coating on the active tops of the semiconductor chips ( 13 . 14 ) are formed. Semiconductor module according to one of claims 5 to 7, characterized in that the internal semiconductor chip stack ( 40 ) Memory components, preferably DRAMs having storage capacities in the gigabit range. Semiconductor module according to one of claims 5 to 7, characterized in that the internal semiconductor chip stack ( 40 ) at least one logic chip preferably comprises a microprocessor. Semiconductor module according to one of the preceding claims, characterized in that for the semiconductor module ( 1 - 5 ) a stacked semiconductor device ( 6 - 10 ) with a wiring substrate ( 34 ), the solder balls ( 43 ) as external contacts ( 42 ) is provided. Semiconductor module according to one of vorherge dependent claims, characterized in that the semiconductor module ( 1 - 5 ) a memory component with a central bonding channel ( 55 ) and wiring foil ( 45 ) having a wiring structure ( 25 ), which with the outer edge connections ( 28 ) is electrically connected. Method for producing a semiconductor module ( 1 - 5 ) with semiconductor components ( 6 - 12 ), wherein the semiconductor components ( 6 - 12 ) are stacked on top of each other and on their underside wiring structures ( 25 ), the method comprising the following method steps: - producing individual semiconductor components ( 6 - 12 ) with outer edge connections ( 28 ) on at least one outer side ( 30 ); Stacking the semiconductor components ( 6 - 12 ) aligning the outer edge connections ( 28 ) in vertical direction one above the other; - connecting superimposed outer edge connections ( 28 ) by applying fasteners ( 31 ) on the outer edge connections ( 28 ). A method according to claim 12, characterized in that in at least one of the housing outer edge sides ( 26 . 27 ) of the semiconductor components to be stacked ( 6 - 12 ) vertical to the wiring structures ( 34 ) and in the positions of the outer edge connections ( 28 ) Grooves ( 35 ) for receiving wire webs ( 36 ) are formed. A method according to claim 12 or claim 13, characterized in that first a leadframe ( 37 ) with parallel wire webs ( 36 ) is produced, which via transverse webs ( 39 ) are held in position, wherein the distances of the cable webs ( 36 ) the distances of the outer edge connections ( 28 ) of the semiconductor components ( 6 - 12 ) and the length of the conductor bars ( 36 ) greater than the total height (h) of the semiconductor module ( 1 - 5 ), so that when connecting the cable webs ( 36 ) with the outer edge connections ( 28 ) the transverse webs ( 39 ) via the semiconductor module ( 1 - 5 ) protrude and the supernatants ( 46 ) with the transverse webs ( 39 ) are removed. Method according to one of claims 12 to 15, characterized in that the joining of superimposed outer edge connections ( 28 ) by applying wire webs ( 36 ) on the outer edge connections ( 28 ) by means of laser welding technology. Method according to one of claims 12 to 14, characterized in that the joining of superimposed outer edge connections ( 28 ) by applying wire webs ( 36 ) on the outer edge connections ( 28 ) by soldering the wire webs ( 36 ) on the outer edge connections ( 28 ) he follows. Method according to one of claims 12 to 14, characterized in that the joining of superimposed outer edge connections ( 28 ) by applying wire webs ( 36 ) on the outer edge connections ( 28 ) by means of adhesive technology with a conductive adhesive. Method according to one of claims 13 to 17, characterized in that the molding of grooves ( 35 ) for receiving wire webs ( 36 ) in at least one of the outer sides of the housing ( 26 . 27 ) of the semiconductor components to be stacked ( 6 - 12 ) by inserting wire webs ( 36 ) in an injection mold before an injection molding of the plastic housing ( 47 ) of the semiconductor components to be stacked ( 6 - 12 ) he follows.