DE102004035126A1 - Circuit structure for supplying a load with an alternative voltage uses two or more sources of voltage linked to supply voltage connections - Google Patents

Abstract

On supply voltage connections (SVC) (1,2) there are means (3,4) for making a conductive link between the SVC and a common load connection (CLC) (12). These means are set up to produce a connection of low impedance, if the difference between a voltage (U1,U2) on the SVC and a voltage (UL) on the CLC exceeds a threshold value. An independent claim is also included for a method for making an alternative connection between supply voltage connections and a common load connection.

Description

The The invention relates to a circuit arrangement for alternative power supply a load of at least two connected to power supply terminals Voltage sources, wherein each power supply connection means for conductive connection of the supply voltage terminal with a common load connection are provided.

at In many applications, one device will be made up of different ones Power sources supplied, often it is an internal battery and a mains voltage source. While the battery voltage constantly available is, for example, during a standby state, is the other, network-connected supply voltage not all the time available. Depending on the operating situation, a load must therefore either from the battery be fed or from the mains voltage source. Also it can happen that the battery is completely discharged and therefore the load from the other power source, such as a charger supplies must become.

Often should hold user data in a non-volatile memory become. But if an integrated circuit in CMOS technology is built up, lets yourself a non-volatile Do not realize memory. In CMOS technology are only volatile memory realizable. To save user data even when the device is switched off to be able to Therefore, a battery is required, the voltage is always available. Besides there are also other Schaltungskompnenten, which an uninterrupted Need supply voltage.

In As a rule, it is advantageous if the voltage source for Supply of the load, so for example, the memory used that will be the higher Has tension. A used mains supply voltage is usually higher as a battery voltage. If the voltage source with the higher voltage is used to supply the load is therefore ensured that the mains voltage source takes precedence over the battery Has. This is thus spared and only used, if no other power source is available.

For this purpose, it is known to connect two supply voltage sources in each case via a diode with a common load connection, as in 6 is shown. The arrangement of the diodes D1 and D2 ensures that a load 5 is supplied with the voltage U1 or U2, which is higher than the other supply voltage. The diode which is supplied with the higher supply voltage is poled in the flow direction, while the other diode is automatically poled in the reverse direction or the other supply voltage is not sufficient to exceed the forward voltage of the diode. In this way it is ensured at the same time that no current flow from one voltage source to the other voltage source takes place. A disadvantage of this known circuit arrangement is the high voltage drop across the diodes. Therefore, such a circuit is not suitable for applications that operate at a very low operating voltage.

An improved circuitry in this regard is also known from the prior art and in 7 shown. Instead of the diodes are two switches 10 and 11 , For example, switching transistors, provided, which are controlled by a comparator. The inputs of the comparator are with the two supply voltage connections 1 and 2 connected to which the voltage sources are connected. Depending on which of the supply voltages is higher, the voltage level at the comparator output is a logical "1" or a logic "0". While the one switch 10 is connected directly to the comparator output is in the drive path of the other switching transistor 11 an inverter switched. If, for example, the voltage U1 is greater than the voltage U2, a logic "1" is generated at the comparator output and the switch 10 becomes low impedance. At the same time the switching transistor 11 is driven with a logical "0" because of the intermediate inverter and becomes high-impedance. Due to the occurring switching times of the comparator and the inverter jeoch is not sure that the load is supplied at any time with voltage. It may experience the operating condition that both switches 10 and 11 are high impedance.

task The invention is a circuit arrangement for alternative Power supply of a load from at least two voltage sources to ensure, on the one hand, that a lower one Voltage drop by switching means occurs and on the other hand ensured is that a connected load without interruption with a the voltage sources is connected.

This object is achieved by a circuit arrangement of the aforementioned type, which is characterized in that the means are each adapted to produce a low-resistance connection, when the difference between the voltage at the supply voltage terminal and the voltage at the load terminal is a threshold exceeds value.

at the circuit arrangement according to the invention becomes the difference of the voltage at the supply voltage terminal and evaluated at the load terminal to trigger a switching action. If a supply voltage is applied, which is higher than the current Supply of the load used supply voltage, so is due the embodiment of the invention the circuit first the voltage source with the higher Supply voltage connected to the load terminal, so that the Voltage at the load terminal increases. This will reduce the voltage on the Load connection greater than the voltage of the previously active voltage source and its associated Switching means disconnect the connection to the load connection. Because the disconnecting the previously active voltage source in response to connecting the Load connection with a higher Supply voltage occurs, it can not cause a break the power supply of the load come.

The inventive circuit arrangement has the advantage that the load always with the supply voltage source connected, which is the higher Voltage, thereby interrupting the power supplies are prevented and also prevents a current from one Voltage source flows into the other voltage source. Of the Voltage drop over The switching transistors preferably used can thereby a few millivolts can be reduced if necessary. The circuit arrangement can be implemented in CMOS technology, wherein also a realization in other technologies is possible.

Of the Threshold when exceeded Switching takes place, is preferably in the range of the voltage drop across the used switching means in low-resistance state. He should go with it be so high that a statistical fluctuation of the comparator offset no reverse line can cause.

In an advantageous embodiment are the switching means by a comparator and a switching transistor formed, wherein the control terminal of the switching transistor with a Output of the comparator is connected.

Further advantageous embodiments of the invention are specified in the subclaims.

The The invention will be explained in more detail with reference to embodiments. It shows:

1 a schematic representation of a first embodiment of a circuit arrangement according to the invention,

2 a diagram with temporal voltage curves within the circuit of 1 .

3 a more detailed representation of the circuit arrangement of 1 .

4 a further developed embodiment of a circuit arrangement according to the invention,

5 a more detailed representation of the circuit arrangement of 4 .

6 a first circuit arrangement according to the prior art and

7 a second circuit arrangement according to the prior art.

In the 1 is a circuit arrangement according to the invention for supplying a load 5 shown. In the embodiment shown, there are two voltage sources 6 and 7 available as an alternative to supplying the load 5 can be used. The voltage source 6 is with a power supply connection 1 and the voltage source 7 with a power supply connection 2 connected. Weight 5 is with a load connection 12 connected. Between the power supply terminals 1 respectively 2 and the load connection 12 are means 3 and 4 arranged for the conductive connection of the respective supply voltage terminal 1 or 2 with the common load connection 12 are set up. The means 3 and 4 each have a comparator 8th respectively 9 and a switch 10 respectively 11 on. The switches 10 and 11 are from the respective comparators 8th and 9 driven.

To describe the function of the circuit arrangement, it is assumed that initially the second supply voltage connection 2 with the load connection 12 connected is. Accordingly, the switch is at this time 11 low resistance. Will the voltage U1 of the first voltage source 6 at the first supply voltage connection 1 is applied, greater than the voltage UL at the load terminal 12 So this is done by the comparator 8th detected and the switch 10 so that a low-resistance connection between the first supply voltage terminal 1 and the load connection 12 will be produced. The voltage U1, which until the time of switching the switch 10 higher than the voltage UL, is also connected to the load connection after switching 12 at. It follows that the voltage U2 at the second supply voltage terminal 2 now less than the voltage UL, since previously U2 was equal to UL and UL was now increased. The comparator 9 recognizes this and controls the switch 11 such that the connection becomes high impedance. The voltage source 7 is thus from the load connection 12 separated.

To illustrate these processes are in the. Diagram of 2 the relevant processes are shown schematically. The voltage U2 is at a constant level throughout the period considered sufficient to supply the load. At time t1, the first supply voltage connection is made 1 a voltage U1 is applied, which is higher than the voltage U2 at the second supply voltage terminal 2 , The comparator 8th recognizes this and gives with a time delay, which is due to the internal operations of the comparator 8th arises, at a time t2, a signal UG10 at its output, with which the switch 10 is charged. In the illustrated voltage curve, it is assumed that the switch 10 is low-impedance, if it is controlled with a logical "0". Therefore, the switch 10 low impedance and the voltage U1 is applied to the load terminal 12 connected through. The voltage UL, which used to be UL equal to U2, increases to UL equal to U1. This voltage increase at the load connection 12 As a result, the comparator 9 tilts and at time t3 the switch 11 drives, so the switch 11 is opened.

In the circuit arrangement according to the invention, the disconnection of a connection takes place between a supply voltage connection 1 or 2 and the load connection 12 always in response to closing another switch instead. Therefore, it can not interrupt the power supply of the load 5 come.

3 shows a more concrete embodiment of the circuit of 1 , The comparators 8th and 9 are switched so that in each case the inverting input to the supply voltage terminal 1 respectively 2 connected is. Between the respective non-inverting input and the load connection 12 are sources of voltage 13 respectively 14 each connected to the potential at the non-inverting input to the potential at the load terminal 12 increase. On the output side are the comparators 8th and 9 each to the gate of a p-MOS transistor 10 respectively 11 connected. These transistors correspond to those in 1 shown switches 10 and 11 ,

The voltage sources 13 and 14 define the minimum voltage drop across the transistors 10 and 11 , In order to prevent the backward conduction or the short-circuiting of the two supplies, this voltage must be higher than the maximum expected offset in the comparator. Of course, the voltage sources could 13 and 14 also at the inverting input of the comparators 8th respectively. 9 be connected. The same function can also be realized by an asymmetrical input stage of the comparator.

In the circuit arrangement of 3 P-MOS transistors are used, since they have more favorable properties for the purpose shown. By connecting the comparator inputs a tuned to the p-MOS transistors switching behavior is achieved. When you look for the transistors 10 and 11 n-MOS transistors would use the inputs of the comparators 8th and 9 be reversed.

The voltage drop across the transistors 10 and 11 can be reduced by constructive measures until it reaches the height of the offset voltage of the comparators used.

The 4 shows a development of the circuit of 3 , wherein by an additional wiring of the gate terminals of the transistors 10 and 11 a decrease in the voltage drop across the transistors 10 and 11 is reached. The gate of the transistor 10 is with an arrangement of two transistors 15 and 19 and a power source 17 connected. The transistor 15 is from the voltage U2 at the second supply voltage terminal 2 driven. When the voltage U2 is smaller than the voltage U1 by a certain amount, the transistor becomes 15 low impedance and a current flows through the transistor 15 and the power source 17 , This shifts the potential at the gate of the transistor 19 so that this becomes conductive and the potential at the gate of the transistor 10 continues to lower. This will cause the voltage drop across the transistor 10 further reduced.

At the gate of the transistor 11 a corresponding circuit is provided, there being a transistor 16 from the voltage U1 at the first supply voltage terminal 1 is charged.

The 5 shows a concrete implementation of the circuit of 4 in a standard CMOS technology. From the figure it is clear that the circuit arrangement according to the invention is easy to implement and thus is a cost-effective solution for the alternative supply of a load from different voltage sources.

The comparator 8th as well as the voltage source 13 be with transistors 26 to 31 realized. The input of the comparator form the sources of the transistors 26 and 27 , The transistors 28 to 31 generate the bias currents for the transistors 26 and 27 , By appropriate dimensioning of the transistors 26 to 31 can be imprinted an offset to the comparator, thus obtaining the voltage source 13 ,

To ensure the proper functioning of the comparators under all operating conditions it is necessary that the transistors 26 and 27 always supplied with bias current. To achieve this, the bias current sources were each made double. If the voltage source U1 is present, by means of the resistor 22 and the transistor 24 generates a reference current. This current is then also impressed on all transistors having the same gate and source nodes. This applies to the transistors 28 . 30 . 34 and 36 to. The Elements 23 . 25 . 29 . 31 . 35 . 37 serve the bias current generation depending on U2. The transistor 15 In this implementation, you can directly access the comparator and switch via transistor 27 the gate of transistor 10 ,

The transistors 32 to 37 have the same functionality with respect to the supply of U2.

In the embodiments shown were each provided two alternative voltage sources. Of course it is This concept can also be extended to more than two voltage sources. These are further means for conducting an additional connection Supply voltage connection with the common load connection provided.

1

first Supply voltage connection

2

second Supply voltage connection

3.4

medium for conducting a supply connection

supply voltage terminal with a common

men load connection

5

load

6

First voltage source

7

Second voltage source

8.9

comparators

10.11

switch

12

load connection

13.14

voltage sources

15,16,19,20

transistors

17.18

power sources

22 23

resistors

24 to 37

transistors

t1, t2, t3

timings

D1, D2

diodes

U1

tension at the first supply voltage

Enough

U2

tension at the second supply voltage

Enough

UL

Voltage at the load connection 12

UG10

Control voltage at the output of the comparator 8th

UG11

Control voltage at the output of the comparator 9

Claims (6)

Circuit arrangement for the alternative power supply of a load ( 5 ) from at least two with supply voltage terminals ( 1 . 2 ) connected voltage sources ( 6 . 7 ), each power supply connection ( 1 . 2 ) Medium ( 3 . 4 ) for conducting connection of the supply voltage connection ( 1 . 2 ) with a common load connection ( 12 ), characterized in that the means ( 3 . 4 ) are each adapted to establish a low-resistance connection when the difference between the voltage (U1, U2) at the supply voltage terminal ( 1 . 2 ) and the voltage (UL) at the load terminal ( 12 ) exceeds a threshold. Circuit arrangement according to Claim 1, characterized in that the means ( 3 . 4 ) a comparator ( 8th . 9 ) and a switching transistor ( 10 . 11 ), wherein the control terminal of the switching transistor ( 10 . 11 ) with an output of the comparator ( 8th . 9 ) connected is. Circuit arrangement according to Claim 2, characterized in that at one of the inputs of the comparator ( 8th . 9 ) Medium ( 13 . 14 ) are provided for generating a voltage offset, wherein the voltage offset to the maximum expected offset of the comparator ( 8th . 9 ) is tuned. Circuit arrangement according to claim 2, characterized in that with the control terminal of the switching transistor ( 10 . 11 ) Means are connected to the voltage (U2, U1) at another supply voltage terminal ( 11 . 10 ) are actuated for additional control of the control terminal when the difference between the voltages (U1, U2) at the supply voltage terminals ( 1 . 2 ) exceeds a threshold. Method for alternately connecting supply voltage connections ( 1 . 2 ) with a common load connection ( 12 ), comprising the steps of: a) connecting a supply voltage connection ( 1 . 2 ) with a load connection ( 12 ), if the Voltage at a supply voltage connection ( 1 . 2 ) is higher than the voltage (UL) at the load terminal ( 12 ), b) Disconnecting a previously with the load connection ( 12 ) supply voltage connection ( 2 . 1 ) from the load terminal ( 12 ) in response to the joining in step a). A method according to claim 5, characterized in that the disconnection in step b) in response to the increase of the voltage (UL) at the load terminal ( 12 ) is performed.