DE102004034864B4 - Products and methods for dynamically changing a clock signal - Google Patents

Abstract

System having the following features:
means (111) for performing an operation using a clock signal;
means (101) for supplying a variable operating voltage to the passing means; and
means (104) for dynamically changing the frequency of the clock signal in response to observed changes in the variable operating voltage,
wherein said means (104) for dynamically changing comprises:
means (107) for receiving a first phase of the clock signal and generating a delayed clock signal having a delay relative to the received first phase of the clock signal; and
means (109) for comparing the generated delayed clock signal with a second phase of the clock signal.

Description

Circuits such as integrated circuits (often referred to as "chips") are used in an ever-increasing number of applications For example, such chips as microprocessors are often not only implemented in personal computers (PCs) and laptops, but are typically in many Smaller (and more portable) devices, such as personal digital assistants (PDAs), cell phones, pagers, and various other types of devices, are becoming more of a concern, given the ever-increasing advances made in the performance of chips For example, power consumption becomes a serious performance limitation for high speed microprocessors A design goal for most microprocessor systems is to provide the highest possible peak performance for a computationally intensive code nd a power consumption of the microprocessor system is reduced. A reduction in power consumption (at least during periods of low performance) is desirable to maximize the battery life of the device, particularly when such microprocessor systems are to be implemented within portable electronic devices. A power consumption of a chip can be generally calculated using the following formula: P = C * V ² * F, where P represents power consumption, C represents a switching capacity, V represents an operating voltage, and F represents the clock frequency of the chip. In view of such an equation, a switching capacity (C), a voltage (V) and a frequency (F) are all factors in determining the power consumption (P) of a chip. In many cases, the clock frequency (F) of the processor is limited to keep the power consumption (P) of a chip below a certain level acceptable for use with a given system (e.g., within a desktop or portable device) is.

microprocessor chips were typically implemented with a fixed voltage and frequency, which are intended to prevent the chip from being more than one special size in performance consumed. When designing microprocessor chips, a developer checks typically generating the chip with software code a heavy computing load on the chip to the appropriate voltage and frequency to be determined for the chip can be implemented, such that the power consumption thereof does not exceed a specific size, if heavy invoice charges are encountered by the chip. If however, once implemented, become such heavy ones Arithmetic loads may be relatively rarely encountered, with for much of the Time little (or no) computing load placed on the microprocessor is. As a result, the worst case arithmetic loads dictate the voltage and frequency of the chip, thereby hindering the performance of the chip is (for example due to the reduced frequency, which is the least favorable Case required).

A Power saving technique tries only the clock frequency (F) during a non-compute-intensive activity. This reduces one Power, but does not affect the total energy, the process per is consumed. That is, one Reduction of a frequency (F) results in a linear reduction the power consumed, but also results in a linear Increase one Task execution time period, which causes the energy per task to remain constant. A reduction However, only the voltage (V) of the processor improves the Energy efficiency of the same, but affects the peak performance thereof.

It has been recognized that if a clock frequency (F) and supply voltage (V) are dynamically changed in response to computational load requirements, then the energy consumed per process can be reduced for periods of low computational power while maintaining peak performance, if necessary (ie for periods of high computing power). Design strategies attempting to use such a dynamic change of clock frequency (F) and supply voltage (V) based on computational loads are often referred to as dynamic voltage scaling (DVS). Examples of such DVS techniques include SpeedStep ^™ technology available from Intel Corporation and PowerNOW technology available from Advanced Micro Devices, Inc. Conventional implementations use DVS on a microprocessor under direct control of an operating system (OS). In such an implementation, the OS of a DVS system includes one or more voltage scheduling algorithms that are used to dynamically adjust processor speed and voltage at a microprocessor execution time. The voltage schedulers control the clock frequency (F) and supply voltage (V) of a microprocessor by writing a desired frequency (in MHz) to a coprocessor register. The voltage planners analyze the current and past state of the system to predict the processor's future workload. For example, individual applications provide a deadline and the voltage scheduler uses the previous implementation History of the applications to determine the number of processor cycles that are required and sets the clock frequency (F) accordingly.

DVS techniques use conventionally interval-based voltage planners that regularly analyze system utilization to control the frequency and the voltage. If the voltage planner z. B. determines that the previous time interval is more than 50 % active, it can set the frequency and voltage for the next time interval increase. Thus, the system attempts to dynamically adjust the clock frequency (F) to the minimum level determined by the current Active processes required by the OS are the size of performance to preserve that is consumed by a microprocessor. Around can set the clock frequency (F) to such a level the OS cause F to either increase or decrease. Around Increase F, elevated the OS first, the operating voltage (V) of the chip to a suitable Size to one Support the desired F and then F is raised and by F to a desired To reduce levels, F is first reduced to such a level and then the operating voltage of the chip is reduced to a size that to a support the reduced F is sufficient.

One such approach that uses the OS to the voltage and the However, dynamically controlling the frequency of a microprocessor is often problematic / undesirable. First, a change an OS of a system to implement such an approach, typically very time consuming and / or costly. system Administrators generally do not want to upgrade the OS of the same to the hardware of the same to improve. additionally the OS approach is not completely reliable because it is the same imperfect one Information about it shows how much power the chip actually consumes and what the computing needs are the same. Instead, the OS can just try to guess / guess, what's needed at the chip level becomes. Typically, there are data that are necessary for the OS the power consumption and / or computing needs of a smart chip can appreciate chip specific, resulting in a greater difficulty when implementing / upgrading of such an OS approach results (since the OS implementation must be tailored to a specific chip technology, the is implemented).

The US 5,153,535 US-A-5 011 031 relates to a power system for use with a computer, the power system having circuitry for automatically varying the supply voltage output to the computer system based on the level of current supplied to the computer by the power system. In particular, the computer system includes a variation frequency clock circuit whose frequency changes based on the supply voltage generated by the power system.

The US 5,585,748 describes a voltage / frequency conversion circuit with temperature compensation. In particular, a heater wire control circuit is described in which an integration output signal is compared with a threshold voltage, the comparison output signal being delayed to be compared as a delayed comparison signal with a separate temperature-dependent reference voltage.

It the object of the present invention is a system, a circuit, a voltage-to-frequency conversion circuit and a To provide methods with improved characteristics.

These The object is achieved by a system according to claim 1, a circuit according to claim 7, voltage-to-frequency conversion circuitry according to claim 21 and a method according to claim 28, claim 34 or 37 solved.

At least an embodiment For example, a system accommodates means for performing an operation Using a clock signal on. The system further comprises a device for Supplying a variable operating voltage to the feedthrough device and means for dynamically changing the frequency of the clock signal in response to observed changes at the variable operating voltage.

preferred embodiments The present invention will be described below with reference to FIG the enclosed drawings closer explained. Show it:

1 a portion of a system that includes an exemplary implementation of an embodiment for dynamically changing a clock signal of a chip;

2A to 2C exemplary scenarios that may be encountered when comparing a clock signal of a chip to a delayed clock signal, according to an embodiment of a voltage to frequency converter for managing the clock signal of the chip;

3 an exemplary implementation of a portion of the voltage-to-frequency converter of 1 according to an embodiment;

4 a graph showing the sensitivity of a delay caused by the exemplary Circuitry of 3 for various different tracking signal settings according to an embodiment;

5 an exemplary implementation of a delay element of the voltage-to-frequency converter of 3 according to an embodiment;

6 an exemplary operational flowchart for an embodiment;

7 another example operational flowchart according to one embodiment; and

8th 5 is an exemplary operational flow diagram for implementing on-chip clock management circuitry that is programmable, according to one embodiment.

With reference to 1 is a section of a system 100 5, which includes an exemplary implementation of an embodiment of circuitry for dynamically changing a clock signal. As shown, a power supply provides 101 a performance to a chip 103 , More specifically, a voltage signal and a ground through the power supply 101 typically delivered by certain parasitic housing effects 102 to the chip 103 is fed. Such parasitic hous seeffekte 102 Those skilled in the art are well-known to those skilled in the art of electronic circuitry and will not be described in detail herein. Thus, the resultant voltage signal V1 and the ground G1 are transmitted through the chip 103 receive. The chip 103 includes voltage-to-frequency conversion circuitry (which may be referred to herein as "clock optimization circuitry" or "clock management circuitry") that operates to control the clock CLK of the chip (referred to as the clock signal for the core chip circuitry 111 is dynamically changed in response to changes in the variable voltage supply V1 of the chip, as described below. The chip 103 may be any type of integrated circuit, without limitation including a microprocessor. The core chip circuit arrangement 111 may be any clocked circuit components of the chip 103 include, such as logic to execute instructions in a microprocessor, storage elements for information that the chip can use to perform operations, arithmetic processing logic, etc.

In this exemplary embodiment of 1 includes the voltage-to-frequency conversion circuitry 104 a voltage tracking controller 105 , Voltage switch 106 , a programmable delay line 107 , a delay control 108 , a phase comparator 109 and a clock control 110 which are described below. As shown, in this exemplary embodiment, timing control is provided 110 a chip clock CLK for use by a core chip circuit arrangement 111 out. The clock CLK is further controlled by the programmable delay line 107 and the phase comparator 109 receive. The programmable delay line 107 generates a delayed clock signal, shown as Delayed CLK, based on voltage V1. The phase comparator 109 compares the clock CLK with delayed CLK to determine if the clock control 110 should be instructed to change the frequency of the clock CLK (eg, either increase or decrease the frequency of the clock CLK). More specifically, the phase comparator gives 109 a clock control signal identifying the result of the comparison of the phase of the clock CLK with delayed CLK. Based on such a clock control signal, the clock controller determines 110 whether the frequency of the clock CLK should be changed.

Thus, the programmable delay line generates 107 Delayed-CLK having a delay relative to CLK which varies in a predetermined manner with the supply voltage V1 of the chip. As related to 3 below, in certain embodiments, the delay line is "programmable" such that its sensitivity to changes in supply voltage V1 can be increased or decreased (ie, programmed) to match the circuitry in production before a circuit is actually fabricated It is difficult to predict how such circuitry will behave with respect to different supply voltages. Once the circuitry is actually fabricated (eg, in silicon), certain embodiments allow the delay line 107 is programmed to accurately account for the characteristics of the fabricated circuitry (in silicon), such that the voltage-to-frequency conversion circuitry 104 the clock frequency CLK of the chip suitably changed in response to changes in the variable supply voltage V1. In an exemplary embodiment, such as this one, below in FIG 2A - 2C is described, the Delayed CLK signal is configured to be one clock cycle long. Thus, the clock signal CLK of the chip becomes the delay line circuitry 107 entered that Delay-type CLK that is expected to be exactly one clock cycle later. Thus, the delayed CLK may pass through the phase comparator with a next cycle of the clock CLK of the chip 109 are compared to determine if the frequency of CLK is proper given the operating voltage of the chip.

As it is in 1 is shown, in this embodiment, the received voltage signal V1 and the ground signal G1 both become the core chip circuit arrangement 111 and the voltage-to-frequency conversion circuitry 104 fed. In such an embodiment, the voltage-to-frequency conversion circuitry provides 104 the frequency of the clock CLK generated thereby is at least partially based on the value of the voltage V1. More specifically, V1 is a variable supply voltage (also referred to herein as "variable_supply") associated with the chip 103 is delivered, and the power supply 112 supplies a fixed voltage signal, V_fixed, to the chip 103 in the way that in 1 is shown. As shown, both the variable voltage supply V1 and the fixed voltage supply V_fixed become the voltage-to-frequency conversion circuitry 104 delivered and how to continue with 5 below, such V1 and V_fixed signals are represented by delay elements in the programmable delay line 107 used to manage the clock signal CLK of the chip.

The voltage switches 106 are switches that are programmed (eg via voltage tracking control) 105 ) to increase the sensitivity of the programmable delay line circuitry 107 to adjust for variations in the supply voltage V1 of the chip. Such voltage circuits 106 are actually an analog multiplexer ("MUX"). In operation, the voltage switches send 106 to the programmable delay line 107 either a fixed voltage V_fixed (such that the delay of the generated delayed CLK is insensitive to changes in the variable voltage supply V1 of the chip) or the variable voltage V1 of the chip. Thus, if the variable supply voltage V1 of the chip to the programmable delay line 107 is sent (e.g., to a transfer gate of a delay element of the delay line circuitry 107 is sent as below in connection with 5 is described) increases or decreases, when this supply voltage V1 changes, the delay of the generated delayed CLK. Thus, if a voltage drop is encountered, then the generated delayed CLK will take a little longer than exactly one clock cycle after the CLK signal. In this case, the phase comparator 109 detect that the deferred CLK lasted longer than one clock cycle of the CLK and become a signal to the clock control 110 send to reduce the frequency of CLK.

The above-described comparison of CLK with the delayed CLK by the phase comparator 109 and changing the frequency of CLK by the clock control 110 preferably occurs very rapidly (eg, in approximately 300 picoseconds). The amount by which the supply voltage of the chip can drift during this time (eg, in 300 picoseconds) is very, very small. Thus, the voltage-to-frequency conversion circuitry is eliminated 104 not that the chip encounters a condition in which it fails due to the supply voltage dropping faster than the clock frequency supported by such supply voltage is reduced. Instead, the voltage-to-frequency conversion circuitry recognizes 104 changes in the supply voltage V1 of the chip very quickly to allow the frequency of the clock CLK of the chip to be adjusted accordingly. That's why a very small protective tape for the chip 103 be implemented.

In other words, the supply voltage V1 of the chip moves very slowly compared to the speed at which the voltage-to-frequency conversion circuitry 104 Detects and responds to changes in the supply voltage V1 (eg by adjusting the frequency of CLK accordingly). Thus, the voltage-to-frequency conversion circuitry allows 104 that a safe operating range for the chip 103 is maintained by rapidly adjusting the frequency of CLK in response to changes in the supply voltage V1 of the chip to maintain the clock CLK at a frequency supported by the supply voltage V1 of the chip.

Consequently, the voltage-to-frequency conversion circuitry is 104 effective to dynamically adjust the frequency of the clock CLK based on the variable supply voltage V1. Changes in the supply voltage V1 may be encountered during operation of the chip as a result of a changing load (a parasitic drop) or, for example, a chip or a system controller. If z. For example, as the voltage V1 decreases, the frequency of CLK that is reduced by the voltage-to-frequency conversion circuitry decreases 104 is output (so that the clock frequency is assisted by the reduced supply voltage), and as the voltage V1 increases, the frequency of CLK increased by the Voltage-to-frequency conversion circuitry 104 is output (such that the clock frequency uses the increased supply voltage).

Consequently, the on-chip circuitry allows 104 this exemplary embodiment that the chip 103 regulates the power consumption of the same. It should be remembered that the power consumption of the chip 103 can be calculated using the equation P = C * V ² * F, where P represents power consumption, C represents a switching capacity, V represents an operating voltage (e.g., voltage V1), and F is the clock frequency of the chip 103 represents (eg the frequency of CLK). Thus, the chip may be replaced by the voltage-to-frequency conversion circuitry 104 the clock frequency of the chip 103 (ie, dynamically adjusts the frequency of CLK) in response to changes in the variable supply voltage V1, self-regulate the power consumption thereof.

In an operation of the exemplary embodiment of FIG 1 becomes the system clock (or "chip clock") CLK generated by the voltage-to-frequency conversion circuitry 104 (and in particular by the clock control 110 ) is output to the core chip circuit arrangement 111 entered and used for the clock operations performed by the same. In addition, the clock CLK becomes the voltage-to-frequency conversion circuit 104 entered. More specifically, the clock CLK becomes the programmable delay line 107 and to the phase comparator 109 entered. As related to below 3 - 5 For example, in certain embodiments, the programmable delay line 107 include delayable delay elements and the delay may be programmed to be the target period of the CLK at the target voltage V1. The nominal voltage and the clock frequency can, for. B. are obtained from chip specifications.

If the voltage V1 is in the setpoint and the clock period for the clock CLK is in the setpoint, the delayed clock passing through the delay line 107 is output and called "Delayed CLK" in 1 is shown to have a rising edge that matches that of the system clock CLK of the next clock cycle. The phase comparator 109 would therefore detect a match between the Delayed CLK and the next clock cycle of the clock CLK and the system clock control 110 would be instructed (by the clock control signal provided by the phase comparator 109 nothing is done (ie not to change the frequency of the clock CLK). If the variable supply voltage V1 is higher than the target, the delayed clock, delayed CLK, becomes the phase comparator 109 arrive before the next cycle of the system clock CLK and the clock control 110 will be signaled (by the clock control signal generated by the phase comparator 109 is output) to increase the frequency of the clock CLK. If the voltage V1 is lower than the target; the delayed clock, delayed CLK, is at the phase comparator 109 arrive after the next cycle of the system clock CLK and the clock control 110 will be signaled (by the clock control signal generated by the phase comparator 109 is output) to decrease the frequency of the clock CLK. Exemplary delay elements that may be programmed to alter the Delayed CLK in response to the observed operating voltage V1 are described below 3 - 5 described.

The voltage switches 106 allow the programmable delay line 107 has different responses to a voltage change. By effectively multiplexing a fixed supply, V_fixed, to some delay elements of the programmable delay line 107 , as it further in 3 and 5 below, the delay line becomes 107 less responsive to a voltage change. Using such voltage switch 106 can the size of a response of the delay line 107 to a change in the voltage V1 z. B. can be set to that of the critical path on the semiconductor chip (s) of the chip 103 match.

2A - 2C show exemplary scenarios by the phase comparator 109 can be encountered in a comparison of the clock CLK with delayed CLK. 2A shows z. For example, an example in which a phase, Delay 1, of Delayed CLK coincides with Phase 2 of clock CLK. The phase "clock 1" of the clock CLK is, for example, a first clock cycle that is triggered by the clock control 110 is output. Such a "clock 1" is through the programmable delay line 107 received, which outputs the phase delay 1 of Delayed-CLK. The clock control 110 Then outputs a second clock cycle "Clock 2" of the clock CLK The phase comparator 109 receives CLK and Delayed-CLK and compares the Phase Delay 1 phase of Delayed-CLK to Phase 2 of CLK. In the example of 2A gives the clock control signal that passes through the phase comparator 109 is output, that Delay CLK and CLK match, and thus determines the timing control 110 in that the system clock CLK is at the correct speed and does not change its frequency. That is, given the supply voltage V1 to the core circuit arrangement 111 of the chip determines that the clock CLK of the chip is effective at the correct (or "optimal") frequency.

2 B shows an example in which a phase, delay 1, of delayed CLK occurs after the phase clock 2 of the clock CLK. The clock cycle "Clock 1" of CLK becomes eg by the clock control 110 first issued. Such a "clock 1" is through the programmable delay line 107 received, which outputs the phase delay 1 of Delayed-CLK. The clock control 110 then outputs a second clock cycle "Clock 2" from CLK 109 receives CLK and Delayed-CLK and compares Delay 1 CLK phase delay 1 to the phase of CLK second clock cycle "Clock 2." In the example of FIG 2 B gives the clock control signal that passes through the phase comparator 109 is indicated that the phase of Delayed-CLK is behind the phase of CLK (ie, Delay-CLK Delay 1 phase occurs after CLK Phase 2), and thus timing control determines 110 in that the system clock CLK is too fast, and therefore can reduce its frequency.

2C shows an example in which one phase, delay 1, of delayed CLK occurs before the phase of a second clock cycle "clock 2" of CLK A first clock cycle "clock 1" of CLK is e.g. B. by the clock control 110 first issued. Such a "clock 1" is through the programmable delay line 107 received, which outputs the phase delay 1 of Delayed-CLK. The clock control 110 then outputs a second clock cycle "Clock 2" from CLK 109 receives CLK and Delayed-CLK and compares Delay 1 CLK phase delay 1 to the phase of CLK second clock cycle "Clock 2." In the example of FIG 2C gives the clock control signal that passes through the phase comparator 109 is output, the phase of Delayed-CLK is prior to the phase of CLK (ie, Delay-CLK Delay 1 phase occurs prior to CLK Phase 2), and thus clock control determines 110 in that the system clock CLK is too slow, and therefore can increase its frequency.

Given the above, the phase comparator 109 implemented to determine the following conditions: 1) if the rising edge of CLK is later than the rising edge of Delayed CLK plus a delta; 2) if the rising edge of Delayed CLK is later than the rising edge of CLK plus a delta; and 3) if none of the first two conditions is true (ie the rising edges of Delayed CLK and CLK match within the specified delta). If the first condition is met, the phase comparator gives 109 a signal to cause the clock control circuitry 110 CLK accelerates. If the second condition is satisfied, the phase comparator outputs 109 a signal to cause the clock control circuitry 110 CLK slows down. And if the third condition is detected (ie, none of the first two conditions is true), the phase comparator operates 109 not that the clock control circuitry 110 CLK ever changes.

As an exemplary implementation of the phase comparator 109 For example, it may include set-reset ("SR") latch circuitry used to determine whether the first condition identified above is true (ie, if the rising edge of CLK is later than the rising edge of Delayed CLK plus a delta.) In a similar manner, the phase comparator 109 SR latch circuitry used to determine whether the second condition identified above is true (ie, if the rising edge of Delayed CLK is later than the rising edge of CLK plus a delta). And the phase comparator 109 For example, a combination gate may comprise detecting the third condition identified above (ie, the rising edges of Delayed CLK and CLK coincide within the specified delta). Of course, any other circuitry now known or later developed may perform the above-described function of the phase comparator 109 in implementing the phase comparator 109 be used in alternative embodiments.

3 shows an exemplary implementation of a portion of the voltage-to-frequency converter 104 from 1 according to an embodiment. In this exemplary implementation, a plurality of delay elements are arranged around the programmable delay line 107 from 1 to build. In particular, in 3 delay elements 301 _AD . 302 _AD . 303 _AD and 305 _AD shown. In the example of 3 are also multiplexers (MUX) 304 and 306 contained by the delay control circuitry 108 are controlled by a coarse delay control signal and a fine delay control signal, respectively. This exemplary implementation has a first part 307 (referred to herein as a coarse delay stage) providing coarse control over the delayed clock signal to be generated and a second portion 308 (referred to herein as a fine delay stage) which provides fine control over the delayed clock signal to be generated. The delay elements 301 _AD . 302 _AD and 303 _AD form together with the mux 304 the coarse delay level 307 and the delay elements 305 _AD and the mux 306 educate the Fine delay stage 308 in this example of 3 ,

As it is further in 3 shows the voltage tracking control 105 an 8-bit tracking signal track [7: 0] in this example, with each bit being input to one or more of the delay elements. More specifically, track [7] (ie the most significant bit of the tracking signal) becomes the delay elements 301 _A . 302 _A and 303 _A the coarse delay level 307 entered; track [6] becomes the delay element 301 _B . 302 _B and 303 _B the coarse delay level 307 entered, track [5] becomes the delay elements 301 . 302 and 303 the coarse delay level 307 entered; and track [4] becomes the delay elements 301 _D . 302 _D and 303 _D the coarse delay level 307 entered. Track [3] becomes the delay element 305 _A the fine-delay level 307 entered; track [2] becomes the delay element 305 _B the fine-delay level 308 entered; track [1] becomes the delay element 305 the fine-delay level 308 entered; and track [0] (ie, the least significant bit of the tracking signal) becomes the delay element 305 _D the fine-delay level 308 entered.

How to continue with 5 is described below, if the tracking signal for a delay element is set high (to a logical 1), thus putting the delay element in a tracking mode, the amount of delay of a signal output by the delay element changes in response to the delay element variable voltage V1 of the chip. However, if the tracking signal for a delay element is set low (to a logical 0), the magnitude of the delay of a signal output by the delay element does not change in response to the variable voltage V1 of the chip. Consequently, the voltage tracking control can 105 output an appropriate value for each bit of the tracking signal to selectively set certain of the delay elements in a tracking mode to achieve a desired level of sensitivity of the delayed CLK signal of the variable voltage supply V1 of the chip.

As with the exemplary implementation of 3 is shown, the clock signal, CLK, of the chip becomes a first delay element 301 _A which contributes some amount of delay (ie gate delay) to the CLK signal in the resulting output thereof. That is, the first delay element 301 _A generates an output signal having some amount of delay relative to the CLK signal. The output signal of the first delay element 301 _A becomes a second delay element 301 _B which produces an output signal which is further delayed relative to the CLK signal. The output signal of the second delay element 301 _B becomes the third delay element 301 which produces an output which is further delayed relative to the CLK signal and the output of the third delay element 301 becomes the fourth delay element 301 _D which produces an output signal which is further delayed relative to the CLK signal. The output signal from the fourth delay element 301 _D is input to the MUX as a first input signal "A" 304 and the same becomes the delay element 302 _A entered. As a result, the CLK signal becomes a first series of delay elements, elements 301 _A - 301 _D , which generate a first output signal having a first delay relative to the CLK signal.

The output signal from the delay element 301 _D becomes a second series of delay elements 302 _A - 302 _D input a second output signal (from the delay element 302 _D ), which has a greater delay relative to the CLK signal than the output from the delay element 301 _D having. The output signal through the delay element 302 _D is generated as a second input signal "B" to the MUX 304 and the same becomes the delay element 303 _A entered.

The output signal from the delay element 302 _D becomes a third series of delay elements 303 _A - 303 _D input, which is a third output signal (from the delay element 303 _D ), which has a greater delay relative to the CLK signal than the output from the delay element 302 _D having. The output signal through the delay element 303 _D is generated as a "C" to the MUX 304 entered.

As a result, the CLK signal becomes a first series of delay elements, elements 301 _A - 301 _D , which generate a first output signal having a first delay relative to the CLK signal. The first output is referred to as an input A to the MUX 304 and also becomes a second series of delay elements, elements 302 _A - 302 _D , which generate a second output signal having a second delay relative to the CLK signal. The second output is referred to as an input B to the MUX 304 and also becomes a third series of delay elements, elements 303 _A - 303 _D input, which produce a third output signal, the one third delay relative to the CLK signal. The third output is referred to as an input signal C to the MUX 304 entered. By the coarse delay control signal, either the first, second or third output may be selected as the signal passing through the MUX 304 for the coarse-delay stage 307 should be issued.

The output signal from the coarse delay stage 307 becomes the fine-deceleration level 308 entered. More specifically, the output signal is from the MUX 304 the coarse delay level 307 to a first delay element 305 _A the fine-delay level 308 entered. The delay element 305 _A generates an output signal having some amount of delay relative to the CLK signal. The output signal of the delay element 305 _A is considered an input "D" to the MUX 306 and becomes a second delay element 305 _B the fine-delay level 308 entered. The delay element 305 _B produces an output signal having a further delay relative to the CLK signal and as an input signal "C" to the MUX 306 and further to a third delay element 305 the fine-delay level 308 is entered. The delay element 305 produces an output signal having a further delay relative to the CLK signal, and that as an input signal "B" to the MUX 306 and further to a fourth delay element 305 _D the fine-delay level 308 is entered. The delay element 305 _D produces an output signal having a further delay relative to the CLK signal, and that as an input signal "A" to the MUX 306 is entered. The fine delay control signal can be either the input signal A, B, C or D of the MUX 306 be selected as the signal passing through the mux 306 as the Delayed CLK signal is to be output.

While in this exemplary implementation, four delay elements in each row of the coarse delay stage 307 are shown and four delay elements in the fine-delay stage 308 For example, in other embodiments, any desired number of delay elements may be implemented to provide different amounts of delay at each stage. Further, while three rows of delay elements in the coarse delay stage 307 In some embodiments, any desired number of rows of delay elements may be used to provide different amounts of delay in such a coarse delay stage 307 be implemented.

Further, this embodiment enables the delayed CLK signal generated by the selected delay elements to be dynamically changed based on the operating voltage V1 of the chip. Take z. For example, assume that the output signal B from the MUX 304 is selected for output by the coarse delay control and the output A from the MUX 306 is selected for output by the fine delay control, then the delayed CLK signal has a delay resulting from twelve delay elements (ie, the delay elements 301 _AD . 302 _AD and 305 _AD ). In this exemplary case, the delay from the twelve delay elements is selected to match the phase of the desired clock cycle for CLK (eg, the phase of a 2 GHz clock signal). Such a delayed CLK signal output by the delay elements may be dynamically changed based on the operating voltage V1 of the chip. More specifically, a tracking signal generated by the voltage tracking control 105 is used to programmatically control for each delay element whether it is sensitive to changes in the operating voltage V1 of the chip. By programming a larger number of the delay elements involved in generating the Delayed CLK signal to be dynamically changeable in response to the operating voltage V1 of the chip, the sensitivity of the Delayed CLK signal to changes in the operating voltage of the chip Chips are controlled, as is the graph of 4 is shown below.

4 FIG. 10 is a graph illustrating the sensitivity of a delay caused by the exemplary circuitry of FIG 3 is generated for various different tracking signal settings, according to one embodiment. More specifically shows 4 five curves each corresponding to a different tracking signal setting. The curves carry the magnitude of a delay associated with the delayed CLK signal by the exemplary delay line circuitry of FIG 3 is generated across various different values of the operating voltage (V1) for five different tracking signal settings. In this example, V_fixed for the chip is 1.1 volts. Depending on the setting of the tracking signal setting, the magnitude of the delay generated for the Delayed CLK signal may change as the operating voltage V1 of the chip falls below or increases above the value V_fixed (1.1 volts in this example) , All of the curves provide the same delay when the operating voltage V1 of the chip is at 1.1 volts (V_fixed).

By selectively setting appropriate bits of the tracking signal, the amount of delay provided by the circuitry of FIG 3 is to be generated, tuned for a specific value of the operating voltage V1 of the chip. As it is z. By one of the curves in the graph of FIG 4 is shown, if the tracking signal has all of its bits set to 0 (ie, track [7: 0] = 00000000), a constant delay is provided for the Delayed CLK over the various different V1s. Thus, if a tracking mode for all of the delay elements of the circuit of 3 is disabled, such delay line circuitry is insensitive to changes in the operating voltage V1 of the chip and produces a constant delay for delayed CLK across the various operating voltages shown.

A second curve, shown in the graph of 4 2 is equal to the magnitude of a delay generated across different operating voltages when the tracking signal has its most significant bit set (ie, track [7: 0] = 10000000). In the circuit arrangement of 3 this activates a tracking mode for the delay elements 301 _A . 302 _A and 303 _A , In this case, the delay is somewhat sensitive to changes in the operating voltage of the chip, as indicated by the corresponding curve in 4 is shown.

A third curve, shown in the graph of 4 shown corresponds to the magnitude of a delay generated across different operating voltages when track [7: 0] = 11000000. In the circuit arrangement of 3 this activates a tracking mode for the delay elements 301 _A . 302 _A . 303 _A . 301 _B . 302 _B and 303 _B , In this case, the delay is more sensitive to changes in the operating voltage of the chip than when track [7: 0] = 10000000, as indicated by the corresponding curve in 4 is shown.

A fourth curve, which in the graph of 4 shown corresponds to the magnitude of a delay generated across different operating voltages when track [7: 0] = 11001000. In the circuit arrangement of 3 this activates a tracking mode for the delay elements 301 _A . 302 _A . 303 _A . 301 _B . 302 _B . 303 _B the coarse delay level 301 and it activates a tracking mode for the delay element 305 _A the fine-delay level 308 , In this case, the delay is more sensitive to changes in the operating voltage of the chip than when track [7: 0] = 11000000, as indicated by the corresponding curve in 4 is shown.

A fifth curve, which in the graph of 4 is equal to the magnitude of a delay generated across different operating voltages when all bits of the tracking signal are set to 1 (ie track [7: 0] = 11111111). In the circuit arrangement of 3 this activates a tracking mode for all of the delay elements 301 _AD . 302 _AD . 303 _AD and 305 _AD , In this case, the delay is very sensitive to changes in the operating voltage of the chip, as indicated by the corresponding curve in 4 is shown.

With reference now to 5 FIG. 10 is an exemplary implementation of a delay circuit, such as a single delay element of FIG 3 , shown according to one embodiment. More specifically shows 5 an exemplary implementation of the delay element 301 _A where each of the other delay elements 301 _BD . 302 _AD . 303 _AD . 305 _AD from 3 can be implemented in the same way. As described below, this includes an exemplary implementation of the delay element 301 _A inverter 501 and 504 , pFETs (p-type field effect transistors) 502 . 503 . 507 . 508 . 510 and 512 and nFETs (n-type field effect transistors) 506 . 509 . 511 and 513 , Such inverters, pFETs and nFETs are well known in the art. In general, in a FET, a current flows along a semiconductor path called the channel. At one end of the channel is an electrode called the Source. At the other end of the channel is an electrode called the drain. The physical diameter of the channel is fixed, but the effective electrical diameter thereof can be changed by applying a voltage to a control electrode called the gate. The conductivity of the FET depends at any given time on the electrical diameter of the channel. A small change in gate voltage can cause a large change in the current from the source to the drain. In other words, the resistance value of the FET can be changed by changing the voltage applied to the gate thereof.

The inverter 501 receives the "tracking" signal as an input and it outputs a signal "trackb". The "tracking" signal corresponds to the bit of the tracking signal associated with that delay element 301 _A is entered, as it is at 3 described above (ie track [7] is in this example as the delay element 301 _A entered described). As described above, the "trace" bit received by the delay element is used to activate the tracking mode of the delay element, if desired.

The inverter 504 receives a signal "input" which is the clock signal of the chip, CLK, as shown in FIG 3 is shown. That is, the "input" signal to the inverter 504 of the delay element 301 _A is the clock signal CLK of the chip. As it is in 3 Of course, the input to other delay elements is the output of a previous delay element. Such an inverter 504 of the delay element 301 _B in 3 would z. B. the "output" signal from the delay element 301 _A received (ie the signal that is for the delay element 301 _A in 5 labeled as "exit").

In addition, the pFETs provide 502 and 503 effectively provides an analog inverter that receives a signal "variable-supply" (also referred to herein as "V1") and outputs "variable-supply-inv." variable_supply (or "V1") is a variable voltage supply, which is supplied to the core circuitry of the chip, as described above with reference to FIG 1 is discussed. As shown, further, a fixed voltage supply, referred to herein as a reference supply, is provided 5 is shown as V_fixed to sections of the delay element 301 _A delivered. In an exemplary implementation, as with 4 described above, the voltage of V_fixed is 1.1 volts and the ground ("GND") is 0 volts and variable_supply can vary between 0.75 volts and 1.2 volts. Of course, in other implementations, the values of V_fixed and GND be set to any suitable values for the circuit arrangement 502 and the pFET 503 provides an analog inverter such that if z. Variable_supply 200 millivolts below the fixed supply V_fixed, variable-supply-inv 200 millivolts above GND. More specifically, the pFET acts 503 with grounded gate as a resistor and the pFET 502 acts like a regular pFET so that as the value of variable-supply goes away from V_fixed, variable-supply-inv goes away from GND. So put the pFETs 502 and 503 an analog inversion, wherein the change in the output signal, variable-supply-inv, is proportional to the change in the input signal, variable-supply.

The nFET 506 and the pFET 507 are further arranged to a transfer gate 505 to provide effective. As described below, the effective resistance value controls via the transfer gate 505 the magnitude of a delay that is transmitted to the output signal. The effective resistance value via the transfer gate 505 is through the inputs to the gates of the nFET 506 and the pFET 507 controlled.

As described below, the delay element is 301 _A in one of two different ways, depending on whether a tracking mode for such a delay element 301 _A is active (ie, depending on the value of the "tracking" signal bit input to the delay element.) In this example, if the track bit of the delay element is set low (ie to a logic 0), then a tracking mode is for such a delay element 301 _A inactive. In this case, V_fixed becomes the gate of the nFET 506 of the transfer gate 505 delivered and the ground (GND) becomes the gate of the pFET 507 of the transfer gate 505 delivered. However, if the tracking bit of the delay element is set high (ie to a logical 1), then a tracking mode is for such a delay element 301 _A active, with variable-supply to the gate of the nFET 506 of the transfer gate 505 and variable-supply-inv to the gate of the pFET 507 of the transfer gate 505 is delivered. The resistance across the pass gate 505 varies depending on the input signals to the gates of the nFET 506 and the pFET 507 , Thus, if a tracking mode is active, the variable_supply and variable-supply-inv signals control the resistance of the transfer gate 505 , thus controlling the magnitude of a delay of the output signal. More specifically, in this arrangement, the smaller the variable-supply signal is, the larger the amount by which the output signal is delayed. Otherwise, if a tracking mode is inactive, V_fixed and GND control the resistance of the transfer gate 505 such that it remains constant, thus delaying the output of such a delay element 301 _A not changed.

Further considering the operation of this exemplary implementation of the delay element 301 _A Assume further that the track bit of it is set low (ie to a logical 0), so that a track mode for this delay element 301 _A is inactive. In this case, the trackb signal is through the inverter 501 is high (ie a logical 1). The tracking bit signal, which is low, becomes the gate of the pFET 510 supplied, wherein such a pFET 510 is effectively turned on (or the switch thereof is closed), and the trackb signal becomes the gate of the pFET 508 supplied, wherein such a pFET 508 is turned off so effectively (or the switch of the same is opened). Consequently, V_fixed is via the pFET 510 to the gate of the nFET 506 of the transfer gate 505 delivered. In addition, the tracking bit signal becomes the gate of the nFET 509 supplied, whereby the current flow through such a nFET 509 is turned off, and the trackb signal becomes the gate of the nFET 511 supplied, whereby the current flow through such a pFET 511 is activated effectively. As a result, the ground ("GND") over the nFET 511 to the gate of the pFET 507 of the transfer gate 505 delivered. Therefore, if a tracking mode is inactive, V_fixed and GND control the resistance value of the transfer gate 505 such that it remains constant, thus delaying the output of the delay element 501 _A not changed.

Now assume that the tracking bit is set high (ie to a logical 1), such that a tracking mode for the delay element 301 _A is active. In this case, the trackb signal is through the inverter 501 is output low (ie a logical 0). The trace bit signal, which is high, becomes the gate of the pFET 510 supplied, whereby such a pFET 510 is effectively turned off and the trackb signal becomes the gate of the pFET 508 delivered, such a pFET 508 is activated effectively. Consequently, variable_supply will be via the pFET 508 to the gate of the nFET 506 of the transfer gate 505 delivered. In addition, the tracking bit signal becomes the gate of the nFET 509 supplied, such a nFET 509 is effectively turned on, and the trackb signal becomes the gate of the nFET 511 delivered, such a pFET 511 is switched off effectively. As a result, variable_supply-inv goes over the nFET 509 to the gate of the pFET 507 of the transfer gate 505 delivered. As mentioned above, with this arrangement, the delay caused by the transfer gate 505 is transmitted to the output signal, longer as variable-supply decreases. The lower the supply to the gate of the nFET 506 and the higher the negative (or ground) supply to the gate of the pFET 507 is, the slower data goes from an "input" to an "output" in the delay element 301 _A (ie the effective resistance value of the transfer gate 505 is increased).

This exemplary implementation further includes the pFET 512 and the nFET 513 that are effective to the output of the transfer gate 505 by driving against the output of the inverter 504 to delay further. If z. B. tracking for the delay element 301 _A is inactive, the trackb signal is high (ie logic 1), which is the nFET 511 turns on GND to the gate of the pFET 507 to deliver, as described above. This also causes GND via the nFET 511 to the gate of the nFET 513 what is the nFET 513 effectively turns off (or opens the switch thereof) such that it has no effect on the output signal. Further, if tracking is inactive, the tracking bit signal is low (ie, logic 0), which is the pFET 510 turns on to V_fixed to the gate of the nFET 506 to deliver, as described above. This also causes V_fixed via the pFET 510 to the gate of the pFET 512 what is the pFET 512 effectively turns off (or opens the switch thereof) such that it has no effect on the output signal.

If, however, tracking for the delay element 301 _A is active, the trackb signal is low (ie logic 0), which is the nFET 511 turns off (or opens its switch). The tracking bit signal is high, which is the nFET 509 turns on (or closes the switch thereof) to provide variable-supply-inv to the gate of the pFET 507 to deliver, as described above. This also causes variable_supply inv via the nFET 509 to the gate of the nFET 513 is delivered. As described above, when variable-supply is lower than V_fixed, variable-supply-inv is higher than GND, and such variable-supply-inv may cause the nFET 513 partially turns on when variable-supply-inv rises above GND. Because the tracking bit signal is high, in a similar manner the trackb signal is low, which is the pFET 508 turns on to variable_supply to the gate of the nFET 506 to deliver, as described above. This also causes variable_supply via the pFET 508 to the gate of the pFET 512 what is such a pFET 512 partially turns on. Thus, if tracking is active, the output signal from the transfer gate 505 through the pFET 512 and the nFET 513 delayed further, who fight against the same driver.

6 FIG. 12 shows an operational flow diagram for on-chip clock management circuitry, such as the voltage-to-frequency conversion circuitry 104 from 1 , according to an embodiment. At a service block 601 becomes a first phase of a clock signal CLK of a chip in the delay line circuit 107 received the chip. At a service block 602 generates at least one delay element, such as the delay element 301 _A from 3 and 5 the delay line circuit 107 a delayed clock signal, Delayed CLK, having a phase delayed relative to the first phase of the received CLK signal. At a service block 603 compares the comparison circuitry 109 of the chip generates the delayed CLK signal with a later phase of the CLK signal of the chip (ie, a phase of CLK which is later in time than the received first phase of such a CLK signal). At a service block 604 determines the clock control circuitry 110 the chip, whether the frequency of the CLK signal of the chip to be changed, at least partially based on the comparison of the generated delayed CLK signal with the later phase of the CLK signal of the chip.

7 FIG. 12 shows an operational flow diagram for on-chip circuitry, such as FIG example, the exemplary circuit of 3 operative to generate a delayed CLK signal having a magnitude of a delay relative to the CLK signal of the chip that may vary in response to changes in an observed operating voltage for the chip, in accordance with at least one embodiment. As further described herein, such a delayed signal may e.g. B. be used in a dynamic management of the frequency of the CLK signal of the chip. At a service block 701 the on-chip circuitry observes an operating voltage of the chip. As it is z. B. at 5 can be described, a delay element 301 _A receive the operating voltage of the chip. At a service block 702 the on-chip circuitry receives a clock signal. As it is z. B. also at 5 is described, the delay element 301 _A receive the CLK signal of the chip as an input signal. At a service block 703 For example, the on-chip circuitry generates a delayed clock signal having a delayed magnitude relative to the received clock signal, wherein the delayed magnitude is programmably selectable to vary in response to changes in the observed operating voltage. As it is z. B. at 5 can be programmatically set by a tracking signal supplied to such a delay element, whether the size of a delay caused by the delay element 301 _A is transmitted upon generation of the delayed CLK signal, should vary in response to changes in the observed operating voltage.

8th 12 shows an operational flow diagram for implementing a clock management circuitry on a chip, such that the clock management circuitry is tailored to the chip after fabrication of the chip, thus being able to provide the specific characteristics (e.g., electrical characteristics, etc.). ) of the chip as it is made. At a service block 801 For example, a chip is fabricated to include clock management circuitry, such as the exemplary circuit arrangement 104 from 1 for dynamically managing the clock signal of the chip in response to observed changes in the variable operating voltage supply of the chip. At a service block 802 is the clock management circuitry on the manufactured chip z. Using the tracking signal above 3 - 5 programmed to tailor its sensitivity to the observed changes in the chip's variable operating voltage. The tracking signal from 3 - 5 can z. B. can be used to tailor the clock management circuitry to be insensitive to observed changes in the variable operating voltage of the chip (by disabling a tracking mode for all of the delay elements), or such a tracking signal can be set to value the sensitivity of the Clock management circuitry to tailor the variable operating voltage of the chip to any desired size.

Embodiments described above provide a system and method for dynamically changing a clock signal. More specifically, certain embodiments provide a system and method in which the frequency of a clock signal of a circuit (eg, a chip) is dynamically changed in response to changes observed in the operating voltage of the circuit. In certain embodiments, delay line circuitry is provided that is operative to receive a clock signal and generate a delayed clock signal that is delayed from the clock signal by an amount based at least in part on the operating voltage of the circuit. A clock signal CLK of a chip is z. To the core circuitry 111 of the chip is supplied for use in performing clocking operations and a variable operating voltage V1 also becomes the core circuitry 111 delivered by the chip. The delay line circuitry 107 receives the clock signal CLK and may provide a delayed clock signal Delayed-CLK based at least in part on the observed operating voltage V1 of the core circuitry 111 of the chip. For example, the lower the variable operating voltage, the greater the magnitude of a delay in the delayed clock signal relative to the clock signal of the chip. The delayed clock signal may then be compared to the clock signal (eg, the phase of the delayed clock signal may be compared to the phase of the clock signal) to determine if the frequency of the clock signal of the chip is adjusted (eg, increased or decreased ) should be. Thus, the clock frequency of the chip can be dynamically changed based on the observed operating voltage.

As described above, certain embodiments implement programmable delay line circuitry 107 for a chip 103 such as a microprocessor. Such a programmable delay line circuit arrangement 107 may comprise a plurality of delay circuits (or "elements"), such as the delay element 301 _A that up in 3 and 5 each selectively transmitting a delay to the delayed clock signal based on the variable Be operating voltage V1 of the chip can be activated. Thus, the more delay elements that are selected to transmit a delay to the received clock signal, the greater the amount of delay that can be transferred to the resulting delayed clock signal. A control signal (or "tracking" signal) may be used to selectively control whether any one or more of the plurality of delay elements transmits a delay that varies in response to changes in the operating voltage V1 of the chip In order to vary the delay magnitude thereof in response to the operating voltage of the chip, it will be described herein as effective in a "tracking mode".

The Speed of digital circuitry depends on various factors, including the operating voltage supply of the same, an operating temperature and processing effects associated with the Production thereof occurred. For example, digital circuits are running in the Generally with an increasing supply voltage faster and run slower with a decreasing supply voltage. It may thus be desired be the frequency of a clock signal of a chip to any given time dynamically for to optimize the operating voltage of the chip. As described above is, make certain embodiments clock optimization circuitry (or "voltage to frequency conversion circuitry" or "clock management circuitry") on a chip for that very purpose, d. H. to a dynamic optimization the frequency of the clock signal of the chip for the operating voltage (or "variable Supply voltage ") of the chip being observed at any given time.

In certain embodiments, a programmable delay line is implemented to measure the speed of digital circuitry. As described above, in certain embodiments, such a programmable delay line may 107 within a clock optimization circuitry 104 contained on a chip for optimizing a clock speed of a chip based on the current operating voltage V1 of the chip. In an exemplary embodiment, the programmable delay line is 107 z. B. on a chip together with a phase comparator 109 and such circuitry is used to provide a signal to a system clock controller 110 to optimize the clock frequency of the chip for a given operating voltage V1 for the chip being observed. In various types of systems where measuring the speed of digital circuits may be desired, such a programmable delay line may be used 107 may be implemented on the same die as the digital circuitry for effectively measuring the speed of the digital circuitry and the results of such measurement may be e.g. B. can be used to dynamically change the speed (ie, clock frequency) of the digital circuitry in a desired manner (eg, in a manner that optimizes the clock frequency for power consumption control).

In one embodiment of the clock optimization circuitry, a programmable delay line is one embodiment 107 implemented on a chip to generate a delayed clock signal based, at least in part, on a variable operating voltage V1 that corresponds to the core circuitry 111 the chip is delivered. For example, a clock signal CLK is controlled by a clock control circuit 110 and such a clock signal CLK becomes the core circuit arrangement 111 of the chip for use in performing clocking operations thereof. The clock signal CLK also becomes the programmable delay line circuitry 107 and based on the variable operating voltage V1 of the chip (which is supplied to the core circuitry of the chip) generates the programmable delay line circuitry 107 a delayed clock signal, delayed CLK. The lower z. For example, as the operating voltage V1 is, the longer is the delay of the delayed clock signal generated by the programmable delay line circuitry 107 is produced.

A phase comparator 109 may be used to compare the generated delayed clock signal with a next phase of the clock signal to determine whether the frequency of the clock signal should be adjusted (e.g., increased or decreased) and the clock signal control 110 can adjust the frequency of the clock signal accordingly. Thus, generally, as the operating voltage V1 decreases, it may result in an increase in the delay of the delayed clock signal, which, when compared to the frequency of the clock signal of the chip, may indicate that the clock signal is too fast and thus should be reduced (FIG. such that the reduced operating voltage V1 can support the frequency of the clock signal). However, as the operating voltage V1 increases, it may result in a reduction in the delay of the delayed clock signal, which, when the same, is at the frequency of the clock nals of the chip, may indicate that the clock signal is too slow and thus should be increased (such that the clock of the chip is running at an optimal frequency supported by the increased operating voltage V1).

As mentioned above, in certain embodiments, the delay line circuitry 107 be programmable by using a "tracking" signal 3 - 5 described above, z. For example, a plurality of delay elements may be implemented and a tracking signal may be used to specify which, if any, such delay elements are to be active for a "tracking mode" operation more sensitive is the delay line circuitry 107 for changes in the variable operating voltage V1. If z. For example, if a tracking mode for a delay element is active, the delay of the delayed clock signal increases as the operating voltage V1 decreases, and if a tracking mode for two delay elements is active, the delay of the delayed clock signal is more sensitive to changes in the operating voltage V1 eg a greater increase in the delay of the delayed clock signal for a given reduction in the operating voltage V1). Consequently, such programmable delay line circuitry 107 be programmed after the chip 103 is made to the delay specific to such a chip 103 to tailor, taking into account the true characteristics of the chip. That is, the sensitivity of the chip's clock signal to changes in the operating voltage V1 of the chip may tailor such sensitivity to that specific chip 103 be programmed.

As with 5 As described above, in certain embodiments, each delay element implemented on a chip includes a transfer gate to which either a fixed supply voltage or the variable supply voltage (operating voltage) is supplied, depending on the value of the tracking signal. If z. For example, if the tracking signal associated with a delay element is set to 1 (for an active tracking mode), then the variable operating voltage is supplied to the transfer gate of that delay element and if the tracking signal is set to 0 (for a non-active tracking mode). , then the fixed supply voltage is supplied to the transfer gate of this delay element. The supply voltage provided to the transfer gate effectively controls the resistance of the transfer gate to control the magnitude of a delay of an input signal (eg, the clock signal of the chip) to produce a delayed clock signal. If z. For example, when the variable operating voltage is supplied to the transfer gate (ie, when a tracking mode for the delay element is active), the amount by which the input clock signal is delayed by this delay element increases as the operating voltage decreases, and vice versa.

Claims (40)

A system comprising: a device ( 111 ) for performing an operation using a clock signal; An institution ( 101 ) for supplying a variable operating voltage to the passing means; and a facility ( 104 ) for dynamically changing the frequency of the clock signal in response to observed changes in the variable operating voltage, the device ( 104 ) for dynamically changing comprises: a device ( 107 ) for receiving a first phase of the clock signal and generating a delayed clock signal having a delay relative to the received first phase of the clock signal; and a facility ( 109 ) for comparing the generated delayed clock signal with a second phase of the clock signal. System according to Claim 1, in which the execution device ( 111 ) and the facility ( 104 ) are included for dynamically changing the frequency of the clock signal on an integrated circuit. A system according to claim 1 or 2, further comprising: means ( 105 ) for programming a magnitude of a delay generated in the delayed clock signal for a value of the operating voltage. A system according to claim 3, wherein the implementing means, the device ( 104 ) for dynamically changing the frequency of the clock signal and the programmer ( 105 ) are included on an integrated circuit. A system according to any one of claims 1 or 2 to 4, further comprising means for controlling ( 110 ) of the clock signal based at least in part on the comparison device ( 109 ) having. System according to claim 5, in which the control device ( 110 ) increases the clock frequency, if that generated delayed clock signal before the second phase of the clock signal, and the control device ( 110 ) reduces the clock frequency if the generated delayed clock signal is behind the second phase of the clock signal. Circuit having the following features: at least a delay element, which is operative to receive a clock signal and a delayed clock signal produce that has a magnitude of delay, based on an observed value of an operating voltage the circuit changed. Circuit according to claim 7, further comprising: a timing control circuitry, which is effective to at least partially reduce the frequency of the clock signal based on the delayed Control clock signal dynamically. Circuit according to claim 7 or 8, further comprising: a comparator circuit arrangement for comparing a received clock signal with a generated one delayed Clock signal. Circuit according to claim 9, further comprising: a timing control circuitry, which is effective to at least partially reduce the frequency of the clock signal based on the comparison of the received clock signal with a generated delayed clock signal to control dynamically. Circuit according to a the claims 7 to 10, which has a plurality of delay elements and further comprises the following features: at least a first number the delay elements, the first one delayed Signal generate a first amount of delay relative to the received clock signal; and at least one second number of delay elements, the second delayed Signal generate a second amount of delay relative to the received clock signal; and a delay control circuitry, which is effective to receive either the first or the second delayed signal as the delayed one Select clock signal. Circuit according to claim 11, further comprising: a multiplexer, which as an input signal, the first delayed signal and the second delayed Receiving signal, wherein the delay control circuitry controls which of the first and second delayed signals are output by the multiplexer becomes. Circuit according to a the claims 7 to 12, further comprising: a core circuit arrangement, the clock signal being sent to the core circuitry for use at a synchronization of the operation of the core circuit arrangement is delivered. Circuit according to claim 13, in which the operating voltage is supplied to the core circuit arrangement becomes. Circuit according to a the claims 7 to 14, further comprising: a tracking control circuitry, the one tracking signal to each of the at least one delay element enters to control whether a size of a delay in a delayed signal, that through the respective delay element is output based on the observed value of the operating voltage changed. Circuit according to a the claims 7 to 14, further comprising: a majority of delay elements; and a tracking control circuitry that generates a tracking signal to each of the plurality of delay elements to control whether a magnitude of a delay in a delayed signal that through the respective delay element is output based on the observed value of the operating voltage changed. Circuit according to claim 16, wherein if the tracking signal is one of the plurality of delay elements is entered, a first value is this delay element the size of one delay in a delay signal, that outputs the same based on the observed value of the operating voltage changed and if the tracking signal associated with that delay element is entered, is a different value than the first value, this delay element a constant delay in a delay signal maintains, that gives the same thing. Circuit according to claim 17, in which, if the tracking signal, to the one of the plurality of delay elements is the first value, this delay element is the size of a delay in the delay signal, which outputs the same, responsive to a reduction in the observed value of the operating voltage increases and this delay element the Size one delay in the delay signal, which outputs the same in response to an increase in the observed value the operating voltage is reduced. Circuit according to one of claims 7 to 18, wherein the at least one delay element receiving the operating voltage and a fixed voltage and the at least one delay element receiving a tracking signal; and wherein the at least one delay element has a pass gate to which the fixed voltage is applied if the tracking signal is a first value, thereby maintaining a constant amount of delay in a delayed signal output by the at least one delay element, and the operating voltage is supplied to the pass gate if the tracking signal is a second value, whereby the magnitude of a delay in the delayed signal output by the at least one delay element is changed. Circuit according to a the claims 7 to 19, wherein the circuit is an integrated circuit. Voltage-to-frequency conversion circuitry, comprising: at least one delay element ( 301 _A ) receiving a clock signal and outputting a delayed clock signal having a magnitude of a delay relative to the received clock signal, the at least one delay element comprising a transfer gate (10). 505 ) to which either a fixed power supply (V-fixed) or a variable power supply is supplied based on the value of a tracking signal (TRACK), and if the variable power supply is supplied to the transfer gate, the transfer gate The amount of delay of the delayed clock signal is changed in response to changes in the variable voltage supply. Voltage-to-frequency conversion circuitry according to claim 21, further comprising: a comparator circuit arrangement for comparing the clock signal with the delayed clock signal. Voltage-to-frequency conversion circuitry according to claim 22, further comprising: a timing control circuitry, which is effective to at least partially reduce the frequency of the clock signal based on the comparison of the received clock signal with the delayed Control clock signal dynamically. A voltage-to-frequency conversion circuit according to any one of claims 21 to 23, further comprising: a plurality of delay elements (16); 301 _AD . 302 _AD . 303 _AD . 305 _AD ) each operative to transmit a delay to the received clock signal to produce the delayed clock signal. A voltage-to-frequency conversion circuit according to claim 24, further comprising: delay control circuitry ( 108 ) for selecting a desired number of the plurality of delay elements to be used in transmitting a delay to the received clock signal to generate the delayed clock signal. A voltage-to-frequency conversion circuitry according to claim 24 or 25, further comprising: tracking control circuitry (16); 105 ) for inputting a tracking signal to each of the plurality of delay elements to control whether the transfer gate of each delay element changes the magnitude of a delay transmitted by the delay element to the received clock signal in response to changes in the variable voltage supply. Voltage-to-frequency conversion circuitry according to one the claims 21 to 26 implemented on an integrated circuit, the integrated circuit being the variable voltage and the fixed one Voltage supplied becomes. A method comprising the steps of: receiving ( 601 ) a first phase of a clock signal of a chip in a delay line circuit of the chip; Produce ( 602 ) a delayed clock signal having a phase delayed relative to the first phase of the received clock signal with at least one delay element of the delay line circuit; To compare ( 603 ) the generated delayed clock signal having a later phase of the clock signal of the chip with a comparison circuit arrangement on the chip, wherein the later phase of the clock signal of the chip is later than the first phase of the clock signal of the chip; and determining ( 604 ), whether the frequency of the clock signal of the chip is to be changed, with a clock control circuitry on the chip, based at least in part on the comparison of the generated delayed clock signal with the later phase of the clock signal of the chip. The method of claim 28, wherein the plurality of delay elements are included in the delay line circuit, the method further comprising the step of: outputting a delay control signal for controlling which of the plurality of delay elements to transmit a delay to the received clock signal to generate the ver delayed clock signal should be used with a delay control circuitry on the chip. Method according to claim 28, in which a plurality of delay elements in the delay line circuit The method further comprises the step of: Output a tracking signal for controlling which of the plurality of delay elements the respective delay same, which transmit the same to the received clock signal, in response to observed changes dynamically change at a variable operating voltage of the chip, with on-chip tracking control circuitry. Method according to claim 30, in which: if the tracking signal has a first value has the size of a Delay, through a delay element is generated, which receives such a tracking signal, via a Range of different operating voltages changed, the for the Be observed chip; and if the tracking signal is a second value, the size of a Delay, through the delay element is generated, which receives such a tracking signal over the Range of under different operating voltages, for the chip observed, remains constant. Method according to one the claims 28 to 31, further comprising the step of: Program the at least one delay element in terms of whether a size of a delay, the at least one delay element to the received clock signal, for changes sensitive at a variable operating voltage of the chip. Method according to one the claims 28 to 32, further comprising the step of: Produce of the delayed Clock signal having the phase relative to the first phase of the received clock signal is delayed by an amount that is appealing changed to an observed operating voltage of the chip, with the at least one delay element. Method comprising the following steps: observing ( 701 ) an operating voltage of a chip with on-chip circuitry; and receiving ( 702 ) of a clock signal and generating ( 703 ) of a delayed clock signal having a delayed magnitude relative to the received clock signal with the on-chip circuitry, wherein the delayed magnitude is programmably selectable to vary in response to changes in the observed operating voltage. Method according to claim 34, in which the on-chip circuitry comprises at least one delay element, that to a transfer a delay to the received clock signal for generating the delayed clock signal and in which the on-chip circuitry includes tracking control circuitry which outputs a tracking signal for controlling whether a delay amount that transmitted through each of the at least one delay element will be responsive to the changes the observed operating voltage changed. Method according to claim 34 or 35, further comprising the steps of: Deliver the operating voltage to the chip; Delivering a fixed voltage to the chip; and selective control of whether a transfer gate, contained in the on-chip circuitry, the operating voltage or the fixed voltage is supplied, wherein if the transfer gate the operating voltage is supplied, the delayed magnitude of the delayed clock signal passing through the on-chip circuitry is generated, over a range of values for the operating voltage can be observed, changed, and wherein, if that Transfer gate the fixed voltage is supplied, the delayed magnitude of the delayed clock signal, generated by the on-chip circuitry over the Range of values used for the Operating voltage can be observed, remains constant. Method comprising the steps of: manufacturing ( 801 ) a chip comprising clock management circuitry for dynamically managing a clock signal of the chip in response to observed changes in a variable operating voltage of the chip; and programming ( 802 ) of the clock management circuitry on the fabricated chip to tailor its sensitivity to the observed changes in the variable operating voltage of the chip. Method according to claim 37, wherein the clock management circuitry at least one delay element wherein the at least one delay element is the clock signal of the chip and a size one Delay on transmits the received clock signal to generate a delayed clock signal. Method according to claim 38, further comprising the steps of: Compare the generated delayed Clock signal with the clock signal of the chip; and Determine if the frequency of the clock signal of the chip should be changed, at least partly based on the comparison. A method according to claim 38 or 39, wherein the programming ( 802 ), comprising the step of: selectively controlling whether the variable operating voltage or a fixed voltage is supplied to a transfer gate included in the at least one delay element, wherein if the variable operating voltage is supplied to the transfer gate, the delayed magnitude of the delayed clock signal is generated by the at least one delay element, changes over a range of values observed for the operating voltage, and wherein, if the fixed voltage is supplied to the transfer gate, the delayed magnitude of the delayed clock signal passing through the at least one delay element is kept constant over the range of values observed for the operating voltage.