DE102004031044A1 - Operational amplifier open loop gain electronic test circuit has resistor network connecting input voltage to amplifier terminals with fixed reference voltage on positive input - Google Patents

Abstract

An operational amplifier open loop gain electronic test circuit has equal resistors (R1-3) and one lower resistor (R/K) connecting the input voltage (Vin) through contacts (41-3) to the amplifier terminals with a fixed reference voltage (Vref) connected to the positive input. Independent claims are included for procedures using the test circuit and a load board incorporating it.

Description

The The invention relates to an electronic test circuit for measuring the Open-loop gain an operational amplifier and a method for determining this open loop gain.

It Electronic test circuits are known with which the idle gain or Open loop gain can be measured by such operational amplifiers where both inputs are freely connectable. Many semiconductor chips or electronic Circuits have one or several operational amplifiers, their positive input fixed with a non-variable reference voltage source connected is. The idling gain of such operational amplifiers can with the well-known electronic test circuits as well as with the known measuring methods have not yet been determined.

It is therefore an object of the present invention, an electronic Test circuit and provide a method by which the Open-loop gain an operational amplifier can be measured, whose positive input fix with a not changeable Reference voltage source is connected.

These The object is solved by the subject matter of the independent claims. advantageous Embodiments emerge from the respective subclaims.

With the inventive electronic Test circuit, the idle gain of an operational amplifier measured become. Therefore has the electronic test circuit via a voltage source as well as over a network of four ohmic resistors. The first three ohmschen Resistances are each same size. The fourth ohmic resistance is a voltage divider factor K smaller than the first three ohmic resistors. Of further features the electronic test circuit over three Terminals. The first connection contact is via the second and above the fourth ohmic resistance, the second terminal contact via the first and over the second ohmic resistance and the third terminal contact via the second and above the third ohmic resistor connected to the voltage source.

With The described electronic test circuit, the open-circuit voltage an operational amplifier be measured with a predictable output voltage, wherein the positive input of the operational amplifier is not switched, but fix with a non changeable Reference voltage is connected. This positive input of the operational amplifier points often an input offset which is characteristic of the operational amplifier and the skilled person is usually known.

According to advantageous Further developments of the invention are the first connection contact to Contacting a connected to the positive input of the op amp to be tested first external contact of a electronic circuit, the second terminal contact for contacting one connected to a negative input of the operational amplifier second external contact the electronic circuit determines and the third terminal contact is for contacting a connected to the output of the operational amplifier third external contact of the electronic circuit determined.

Consequently can through the voltage source of the electronic test circuit a defined voltage over the first and second ohmic resistance to the negative input of the operational amplifier be created and in dependence this voltage as well as in dependence the voltage applied to the positive input of the operational amplifier reference voltage from the operational amplifier generated output voltage can be measured, for example. By means of a voltmeter.

According to one aspect of the invention, the open loop gain Gain of the operational amplifier can be calculated according to the equation (1)

This presupposes that in each case two voltage _values V _IN1 and V _{IN2 are generated} by the voltage source of the electronic test circuit and applied via the first and the second ohmic resistance to the negative input of the operational amplifier, and that the two in response to these input voltages V _IN1 and V _IN2 output voltages V _OUT1 and V _OUT2 generated by the operational amplifier are measured. The factor K in the equation (1) is due to the selection of the fourth ohmic Resistance known.

As from the equation (1), the resistance values of the ohmic resistances does not affect the calculation of the idling gain of the Operational amplifier. For the However, it is the dimensioning of the ohmic resistors in practice advisable, the output load factor or fan-out of the operational amplifier and to take into account the voltage applied to its positive input reference voltage.

The Invention is based on the recognition that it is difficult to Apply voltage directly to the input of an operational amplifier, without him to saturation to bring and connect the output to a power supply connection especially since many operational amplifiers have an open-loop gain of 10,000 Have V / V or more. additionally have many operational amplifiers input-dependent Offsets that are in the range of several millivolts. Therefore, it is difficult to predict which input voltage a unsaturated Output voltage level causes.

Especially precise results for the idling gain receives one, if the factor K has a value of K = 100, if the first three ohmic resistances each a resistance value in the range of 10 kΩ to 100 kΩ, in particular a value of 100 kΩ as well have a tolerance of 0.1%.

The invention also relates to an integrated circuit having an operational amplifier to be tested, whose positive input is fixedly connected to a non-variable on-chip reference voltage source. In this integrated circuit according to the invention in addition to the other elements of this circuit, an electronic test circuit described above in the Operationsver monolithically integrated more. In this case, the terminal contacts of the electronic test circuit and the respective associated contacts of the integrated circuit are each in the form of connecting lines. With such a space-saving on-chip solution, precise calculation or measurement results for the open-circuit voltage of the operational amplifier can be achieved, wherein only the voltage values V _IN generated by the voltage source of the electronic test circuit and the output voltage values V _OUT generated by the operational amplifier are tapped in a suitable manner and according to FIG of equation (1) must be evaluated by any arithmetic unit. For such a reliable built-in self test BIST, only the voltage source V _IN and the resistor network with the four ohmic resistors need to be arranged at the operational amplifier to be tested.

The invention further relates to a load board for receiving a probe card for testing integrated circuits and / or with one or more test sockets for testing integrated circuits and / or for connecting a handler to a measuring device for testing integrated circuits, the test circuit described above having. With such a loadboard, the open-circuit voltage of an operational amplifier can be reliably measured, wherein the respective external and terminal contacts must be connected to each other during measurement and in addition the output voltage V _OUT generated by operational amplifier must be tapped in a suitable manner from the tested integrated circuit.

The invention also relates to a method for determining the open-loop gain of an operational amplifier of an electronic circuit. In this case, an electronic circuit is initially provided which has a first external contact connected to the positive input of an operational amplifier, a second external contact connected to the negative input of the operational amplifier and a third external contact connected to the output of the operational amplifier. In this case, the positive input of the operational amplifier is permanently connected to an on-chip reference voltage source and is constantly fed by it with a reference voltage V _REF . Furthermore, an above-described electronic test circuit is provided whose external contacts are connected to the corresponding terminal contacts of the electronic circuit or are already in the case of an on-chip solution.

Then, a first voltage V _{IN1 is applied} via the second external contact to the negative input of the operational amplifier by the voltage source V _IN and the first output voltage V _{OUT1 of} the operational amplifier applied to the third external contact is measured by means of a voltmeter, for example. Subsequently, a second voltage V _{IN2 is} applied and the second output voltage V _{OUT2 of} the operational amplifier is measured at the third external contact. When applying the voltage V _IN1 and V _IN2 by the voltage source of the electronic test circuit, it should be noted that a suitable voltage is selected for measuring the output voltage of the operational amplifier, which is, for example, in the value range between -4 V and +4 V.

Then you can the idling gain Gain of the operational amplifier by calculating the equation (1). During the Calculation of the idling gain Gain it is advisable to check that the denominator of equation (1) does not become zero and that no negative denominator is located in the equation.

According to one Another basic idea of the invention can be described by the described Method the open-loop gain Gain of an operational amplifier any electronic circuit already on the basis of two Precise measurements determine.

If the voltage applied by the voltage source second voltage to the first applied voltage preferably by an amount of 1V elevated or lowered, results are already accurate results for the open circuit voltage of the operational amplifier.

Because of the still unknown open loop gain of the operational amplifier at the beginning of the method according to the invention, the voltages V _IN1 and V _IN2 applied by the voltage source of the electronic test circuit can be _selected so that the expected output voltages V _OUT1 and V _{OUT2 are} ≤ _7V . This makes it possible to determine particularly accurate results for the no-load voltage.

The inventive method can be carried out with an above-described, monolithically integrated on an integrated circuit electronic test circuit. In this case, the voltage _values V _IN1 and V _{IN2 are applied} by the on-chip voltage source. It should be noted here that the voltage _values V _IN1 and V _{IN2 of} the on-chip voltage source as well as the output voltage values V _OUT1 and V _{OUT2 need} only be suitably tapped and forwarded to an evaluation unit.

The inventive method can also be carried out with a loadboard described above, on which an electronic test circuit is applied such that their external contacts are in communication with the associated terminal contacts of the loadboard. In such a test arrangement, the voltage _values V _IN1 V _IN2 , V _OUT1 and V _{OUT2 are applied} and _measured on the loadboard.

The The invention is illustrated in more detail in the drawings by means of exemplary embodiments.

1 shows a schematic representation of a first measuring arrangement with an operational amplifier,

2 shows a schematic representation of a second measuring arrangement with a semiconductor chip and with a loadboard,

3 shows a tabular and an associated graphical measurement result representation.

1 shows a schematic representation of a first measuring arrangement 1 ,

The first measuring arrangement 1 has an operational amplifier OP with a positive operational amplifier input OP _{IN +} , with a negative operational amplifier input OP _IN- and with an operational amplifier output OP _OUT , via a reference voltage source V _REF , which is connected via an input voltage offset V _off to the positive operational amplifier input OP _{IN +} , and via an electronic test circuit.

The input voltage offset V _off forms a characteristic quantity for the operational amplifier OP. The electronic test circuit can also be used without the input voltage offset V _off .

The electronic test circuit is composed of a voltage source V _IN and of a resistance network with a first ohmic resistance R ₁ , with a second ohmic resistance R ₂ , with a third ohmic resistance R ₃ and with a fourth ohmic resistance R / K. The ohmic resistances R ₁ , R ₂ and R ₃ are the same size and have the same resistance R = 100 kΩ in the present embodiment. The fourth ohmic resistor R / K is designed to be smaller by a freely selectable voltage divider K than the ohmic resistors R ₁ , R ₂ and R ₃ . In the present exemplary embodiment, the voltage divider K is K = 100, so that the fourth ohmic resistance R / K has the resistance value R = 1 kΩ. The tolerance of the ohmic resistors R ₁ , R ₂ , R ₃ and R / K is in the present embodiment in each case +/- 0.1%.

Between the reference voltage source V _REF and the input voltage offset V _off is a first node K ₁ , from which an electrical line branches to the voltage source V _{IN of} the electronic test circuit and on the successively the fourth ohmic resistance R / K, the first ohmic resistance R ₁ and the second ohmic resistor R ₂ are arranged.

Between the fourth ohmic resistor R / K and the first ohmic resistor R ₁ there is a second node K ₂ , from which an electrical connection line branches off to the negative operational amplifier _input OP _IN- .

At the output OP _{OUT of} the operational amplifier OP is an output voltage V _OUT . After the output OP _OUT of a third node K _3, an electrical connection line is returned, on which the third ohmic resistor R ₃ is located, namely to a located between the first ohmic resistor R ₁ and the second resistor R ₂ fourth node K ₄ .

The operational amplifier OP is supplied with a supply voltage VDD. The operational amplifier OP, the reference voltage source V _REF , the voltage source V _IN and the operational amplifier output OP _OUT are each provided with a ground GND. Furthermore, in 1 nor the voltage drop across the fourth ohmic resistor R / K marked with the reference numeral V _d .

In the first loop located between the reference voltage source U _REF and the voltage source V _IN , on which the fourth ohmic resistor R / K, the first ohmic resistor R ₁ and the second ohmic resistor R ₂ are located, a first current intensity I _{1 flows} . In the mesh, which attaches to the third node K ₃ and extends to the voltage source V _IN and on which the second ohmic resistor R ₂ and the third ohmic resistor R ₃ are arranged, a second current I _{2 flows} .

For the calculation of the output voltage V _OUT , the following equations can be established.

For the first Mesh results in the following equation (I).

In this case, the first current I _{1 flows} through the fourth ohmic resistor R / K, through the first ohmic resistor R ₁ and through the second ohmic resistor R ₂ . The second current I ₂ additionally flows through the second ohmic resistor R ₂ . The voltage source V _IN has a different sign than the reference voltage source V _REF .

For the voltage drop V _d at the fourth ohmic resistance R / K, equation (II) results.

The reference voltage source V _REF ensures the internal power supply.

For the second stitch, the following equation (III) can be established. V OUT -V IN = 2R · I 2 + R · I 1 (III)

Equation (IV) results from the fact that the output voltage V _{OUT of} the operational amplifier OP is equal to its input voltage V _IN multiplied by its gain Gain. V OUT = (V d + V off ) · Gain (IV)

By solving the equations (I), (II), (III) and (IV), the following equation (V) is obtained, with which the output voltage V _{OUT of} the operational amplifier OP is calculated to:

Under Use of the definition of the gain gain known to the person skilled in the art of the operational amplifier OP receives the following equation (1), with which the idling gain Gain of the operational amplifier OP can be calculated.

In this equation (1), two applied in succession from the voltage source V _IN to the negative op-amp input OP _IN input voltages V contained _IN1 and V _IN2 and two in dependence of these input voltages V _IN1 and V _IN2 generated by the operational amplifier OP output voltages V _OUT1 and V _OUT2 , Accordingly, equation (1) assumes that a voltage difference, namely first a first input voltage value V _IN1 and then a second input voltage value V _IN2 , is generated and applied by the voltage source V _IN .

In equations (V) and (1), it is noticeable that the resistance values R have dropped out and therefore they have no influence on the output voltage V _OUT and on the open-loop gain Gain.

2 shows a schematic representation of a second measuring arrangement 2 with a semiconductor chip 3 and with a loadboard 4 ,

The second measuring arrangement 2 is correct with regard to its construction with the first measuring arrangement 1 wherein the reference voltage source V _REF and the operational amplifier OP with its input voltage offset V _off on the semiconductor chip 3 and the voltage source V _IN with the resistor network on the loadboard 4 are formed. The reference voltage source V _REF ensures the internal voltage supply of the semiconductor chip 3 , Both on the semiconductor chip 3 as well as on the loadboard 4 Further elements are provided which are not shown here for reasons of better illustration.

The semiconductor chip 3 has a first external contact arranged immediately after the first node K ₁ 31 , a second external contact connected to the negative operational amplifier _input OP _IN- 32 and a third external contact connected to the third node K ₃ 33 on.

On the loadboard are a first connection contact 41 directly after the fourth ohmic resistor R / K, a second connection contact 42 after the second node K ₂ and arranged after the third resistor R ₃ third terminal contact 43 intended.

In the second measuring arrangement 2 are the first external contact 31 and the first connection contact 41 , the second external contact 32 and the second terminal contact 42 as well as the third external contact 33 and the third terminal contact 43 each electrically connected.

3 shows a measurement result representation 5 , which is in a tabular measurement result representation 51 and in an associated graphical measurement result representation 52 divided.

The measurement result representation 5 FIG. 3 illustrates the measured output voltage values V _OUT and the open-loop gain Gain calculated for them according to equation (1) for three different operational amplifiers OP.

In the first column of the tabular measurement result representation 51 15 in succession from the voltage source V _IN generated input voltages V _IN are generally listed in the second column of the respective constant voltage value of 2.5 V, the reference voltage source V _REF, and in the third column of each constant value of K = 100 for the voltage divider K contain.

The measured output voltage values V _{OUT of} the first operational amplifier OP are in the fourth column of the tabulated measurement result representation 51 and by the darkest line in the graphic Measurement of results 52 shown. The measured output voltage values V _OUT for the second and for the third operational amplifier are in the fifth and sixth column of the tabulated measurement result representation 51 and through the middle and the brightest line in the graphical measurement result representation 52 shown.

The measurement results 51 and 52 show the results of fifteen measurements each for the three operational amplifiers OP. In this case, the input voltage V _IN, starting with a value of 3.0 V, was successively lowered by 0.5 V in each case until the input voltage value of -4.0 V was reached. Depending on the input voltage V _IN , the reference voltage V _REF and the voltage divider T, as well as the measured output voltage V _OUT , a corresponding value for the open-loop gain Gain of the three operational amplifiers OP could be calculated for all measured values using equation (1) demonstrates a high reproducibility, repeatability and stability of the calculation according to the invention, which is given even at high open-loop gains.

The measurement results are in the graphical measurement result representation 52 visualized, wherein on the horizontal axis, the input voltage values V _IN in the range of -4 to 3 volts and on the vertical axis, the output voltage V _OUT in the range of 0 to 10 is plotted.

In front the calculation of the idling gain must be checked each time that there are no negative denominators in equation (1) and that the denominator is not zero.

For the measurement of the output voltages V _OUT was in each case an operational amplifier OP of a semiconductor chip 3 with his external contacts 31 . 32 and 33 , as in 2 shown with the connection contacts 41 . 42 and 43 a loadboard 4 connected. Then successively those in the column 1 the tabular measurement result representation 51 input voltage values V _IN contained generated by the voltage source V _IN and the output voltages V _OUT in each case produced from the operational amplifier OP by means of a in the 1 to 3 not shown voltmeters measured. From this, by means of an evaluation unit, also not shown, using Equation (1), the open-loop gain values Gain were calculated, all in a small spread of less than 1% around the open loop gain value Gain = 60 dB for the first operational amplifier, around the open loop gain value Gain = 70 dB for the second operational amplifier and around the open loop gain value Gain = 80 dB for the third operational amplifier.

A particularly accurate determination of the open-loop gain Gain of the operational amplifiers results when the output voltage V _{OUT reaches} a value which is only slightly smaller than 7 V.

With the method according to the invention it is also possible the output voltage of operational amplifiers for different open loop gain values and for to determine different input voltage offsets.

1

first measuring arrangement

operating room

operational amplifiers

OP _{IN +}

positive Operational amplifier input

OP _IN

negative Operational amplifier input

OP _OUT

Operational amplifier output

V _REF

Reference voltage source

V _IN

voltage source

V _off

Input voltage offset

R ₁

first ohmic resistance

R ₂

second ohmic resistance

R ₃

third ohmic resistance

R / K

fourth ohmic resistance

K ₁

first node

K ₂

second node

K ₃

third node

K ₄

fourth node

V _d

voltage drop

I ₁

first amperage

I ₂

second amperage

GRD

grounding

VDD

Operational amplifier supply voltage

V _OUT

Operational amplifier output voltage

2

second measuring arrangement

3

Semiconductor chip

31

first outside Contact

32

second outside Contact

33

third outside Contact

4

Load Board

41

first connection contact

42

second connection contact

43

third connection contact

5

Measurement of results

51

tabular Measurement of results

52

graphic Measurement of results

Claims (14)

An electronic test circuit for measuring the open-loop gain of an operational amplifier, the electronic test circuit comprising the following features: a voltage source (V _IN ), a first ohmic resistance (R ₁ ), a second ohmic resistance (R ₂ ) and a third ohmic resistance ( R ₃ ), which are each the same size, - a fourth ohmic resistance (R / K) which is smaller by a factor K than the first ohmic resistance (R ₁ ), as the second ohmic resistance (R ₂ ) and as the third ohmic resistance (R ₃ ), - a first terminal contact ( 41 ), which is connected to the voltage source (V _IN ) via the first ohmic resistance (R ₁ ), via the second ohmic resistance (R ₂ ) and via the fourth ohmic resistance (R / K), - a second terminal contact ( 42 ), which is connected to the voltage source (V _IN ) via the first ohmic resistor (R ₁ ) and via the second ohmic resistor (R ₂ ), - a third terminal contact ( 43 ), which is connected via the second ohmic resistor (R ₂ ) and via the third ohmic resistor (R ₃ ) to the voltage source (V _IN ). Electronic test circuit according to claim 1, characterized in that the first connection contact ( 41 ) for contacting a first external contact connected to the positive input (OP _{IN +} ) of an operational amplifier (OP) ( 31 ) of an electronic circuit ( 3 ), wherein the positive input (OP _{IN +} ) of the operational amplifier (OP) is fixedly connected to a reference _voltage source (V _REF ). Electronic test circuit according to claim 1 or 2, characterized in that the second connection contact ( 42 ) for contacting a second external contact connected to a negative input (OP _IN- ) of the operational amplifier (OP) ( 32 ) of an electronic circuit ( 3 ) is determined. Electronic test circuit according to one of claims 1 to 3, characterized in that the third terminal contact ( 43 ) for contacting a third external contact connected to an output of the operational amplifier (OP _OUT ) ( 33 ) of an electronic circuit ( 3 ) is determined. Electronic test circuit according to one of claims 1 to 4, characterized in that the factor K is a value of K = 100 has. Electronic test circuit according to one of claims 1 to 5, characterized in that the first ohmic resistance (R ₁ ), the second ohmic resistance (R ₂ ) and the third ohmic resistance (R ₃ ) each have a value in the range of 10 kΩ to 100 kΩ, in particular of 100 kΩ. Electronic test circuit according to one of claims 1 to 6, characterized in that the first ohmic resistance (R ₁ ), the second ohmic resistance (R ₂ ) and the third ohmic resistance (R ₃ ) each have a tolerance of +/- 0.1 % exhibit. Integrated circuit with at least one operational amplifier whose positive input (OP _{IN +} ) fixed is connected to a reference voltage (V _REF ), wherein on the integrated circuit ( 3 ) an electronic test circuit according to one of claims 1 to 7 monolithically integrated, wherein the first terminal contact ( 41 ) as well as the first external contact ( 31 ) as the first connection line, the second connection contact ( 42 ) as well as the second external contact ( 32 ) as the second connection line and the third connection contact ( 43 ) as well as the third external contact ( 33 ) are formed as a third connection line. Load board for receiving a probe card for testing integrated circuits and / or with one or more test sockets for testing integrated circuits and / or for connecting a handler to a measuring device for testing integrated circuits, wherein the loadboard ( 4 ) has an electronic test circuit according to one of claims 1 to 7. Method for determining the open-loop gain of an operational amplifier of an electronic circuit, comprising the following steps: a) providing an electronic circuit ( 3 ), which has a first external contact connected to the positive input (OP _{IN +} ) of an operational amplifier (OP) ( 31 ) connected to the negative input (OP _IN- ) of the operational amplifier (OP) second external contact ( 32 ) and a third external contact connected to the output (OP _OUT ) of the operational amplifier (OP) ( 33 ), wherein the positive input (OP _{IN +} ) of the operational amplifier (OP) is fixedly connected to a reference voltage source (V _REF ), b) providing an electronic test circuit according to one of claims 1 to 7, c) connecting the first terminal ( 41 ) with the first external contact ( 31 ), the second terminal ( 42 ) with the second external contact ( 32 ) and the third terminal ( 43 ) with the third external contact ( 33 ), d) applying a first voltage V _IN1 to the voltage source (V _IN ) of the electronic test circuit, (VREF is already there, coming from the inside) e) measuring the voltage at the third external contact ( 33 ) Adjacent the first output voltage V _OUT1 of the operational amplifier (OP) (by means of a voltmeter), f) applying a second voltage V _IN2 to the voltage source (V _IN) of the electronic test circuit, g) measuring the third to the external contact ( 33 h) determining the open- _loop gain Gain of the operational amplifier (OP) by calculating the equation:

Method according to Claim 10, characterized in that the second voltage V _IN2 applied in step f) by the voltage source (V _IN ) of the electronic test _{circuit is higher} than the first voltage V _IN1 applied by the voltage source (V _IN ) of the electronic test circuit in step d) preferably increased or decreased by an amount of 1V. Method according to claim 10 or 11, characterized in that the voltages V _IN1 and V _IN2 applied in steps d) and f) by the voltage source (V _IN ) of the electronic test _circuit are selected such that the output voltages V _OUT1 and V _OUT2 ≤ 7V are. Method according to one of claims 10 to 12, characterized in that the electronic test circuit provided in step b) according to claim 8 on the electronic circuit ( 3 ) is monolithically integrated and that the application of the voltage _values V _IN1 and V _IN2 in steps d) and f) on the electronic circuit ( 3 ) and that the voltage _values V _IN1 , V _IN2 , V _OUT1 and V _{OUT2 are} suitably tapped in steps d) to g). Method according to one of claims 10 to 12, characterized in that provided in step b) electronic test circuit according to claim 9 on the loadboard ( 4 ) and that applying and measuring the voltage values in steps d) to g) on the loadboard ( 4 ) he follows.