DE10160507A1 - Generating clock in data processing system with multiple independent non-synchronies digital data channels by using respective delay-locked-loops - Google Patents

Abstract

The method involves obtaining a reference clock (RT), and supplying it to the data channel (101-10n). A respective delay-locked-loop (DLL) circuit (30-3n) is used to equalize the differences in clock frequency between the reference clock and the data channels. The reference clock may be obtained from the data or a clock supplied on a reference channel, using a phase-locked-loop (PLL) circuit (1). An Independent claim is included for an apparatus for generating a clock in a data processing system.

Description

The invention relates to a method and an arrangement for Generation of a clock in a data processing system with a variety of data channels according to the generic terms of Claims 1 and 6.

In data processing systems with a variety of independent data channels, especially in integrated Circuits (ICs) has the problem that it Transmission of data on the various data channels due to different clock frequencies to differences in the data rates of the individual channels can come. In the ent speaking standards is usually a maximum deviation two hundred ppm of the different data rates or Clock frequencies allowed. The problem described leads to that in a data processing system several independent Channels without additional measures, not only with simultaneously can be processed in one bar.

To solve the stated problem, an arrangement according to FIG. 2 is known, in which the required system clock for each data channel 101 , 102 , 10 n is based on a phase-locked loop (PLL) circuit 111 , 112 , 11 n from the data of the respective one Data channel or a supplied clock is obtained. A PLL circuit has a voltage-controlled oscillator (VCO - Voltage Controlled Oscillator), which provides the desired clock. PLL circuits are known in the prior art, so that they will not be discussed further.

The disadvantage of the arrangement of FIG. 2 is that a PLL circuit is required to implement a signal sampling of several independent channels with different data rates for each data channel to be sampled. This disadvantageously requires the use of a large number of voltage-controlled oscillators (VCO). In addition to the associated costs, there is also the risk that the voltage-controlled oscillators or PLL circuits interfere with one another through coupling processes and in this way generate undesirable jitter in the system.

Next is in the prior art as an alternative to that Using a PLL circuit using a delay Locked Loop (DLL) circuit known to have an output signal generates a predetermined delay against one Has input reference signal. DLL circuits are for example in the documents US-A-5 614 855, EP-A2-0 349,715 and US-A-5,317,288. In the article by T.H. Lee, K.S. Donnelly, J.T.C. Ho, J. Zerbe, M.G. Johnson, C. Eshikawa: "A 2.5 V CMOS Delay-Locked Loop for 18 Mbit, 500 Megabytes of DRAM ", IEEE Journal of Solid State Sircoits, Vol. 29, No. 12, December 1994, pages 1491 to 1496, is one DLL circuit described that has an infinite delay area or modulation area. This means, that the DLL circuit has an output signal in its phase can delay arbitrarily. This can cause the phase difference be continuously adjusted between two channels.

The present invention is based on the object Method and arrangement for generating a clock in a data processing system with a variety independent, non-synchronous digital data channels for To provide the need for use avoid a variety of PLL circuits and the im System generate reduce jitter as much as possible.

This object is achieved by a method with the features of claim 1 and an arrangement with the Features of claim 6 solved. Preferred and advantageous  Embodiments of the invention are in the subclaims specified.

According to the invention, a reference clock is provided win and this reference clock all data channels supply. Then for each data channel takes place under Using a Delay Locked Loop (DLL) circuit Compensate for the difference in clock frequency between the Reference clock and the respective data channel. The DLL circuit has an infinite delay range and a bandwidth that is greater than the difference between the frequency of the reference clock and the frequency of the respective data channel.

In the solution according to the invention, therefore, only one Reference clock won and this reference clock for everyone other channels through a DLL circuit each way adjusted and adjusted that both channels are the same Frequency and the same phase position, so that the Data can be scanned correctly. The related The advantage is that not one for each data channel PLL circuit is required.

Because of the use of only one clock source are above it in addition, interference or coupling between the individual Data channels excluded so that the one generated in the system Jitter is reduced.

It should be noted that the invention is independent of the type of data transmission realized on the data channels can be. In particular, the data can be considered electrical or optical signals are transmitted, with opto electronic interfaces, if necessary, suitable opto electronic converters are to be used.

The reference clock is preferred from the data or a supplied clock of a serving as reference channel  Data channel using a phase locked loop (PLL) circuit won. Any data channel can be used as Reference channel can be used. The PLL circuit provides one with its voltage-controlled oscillator (VCO) Clock source for all data channels available, so that the number of PLL circuits required to one is reduced.

However, it is also within the scope of the invention that the Reference clock by an independent clock generator, e.g. B. a quartz oscillator is obtained.

In a preferred embodiment of the Ver driving for each data channel using the respective DLL Switching the phase of the reference clock continuously to the Adjusted phase of the data channel, d. H. the delay between The reference clock and data channel are continuously adapted. The Differences between the clock frequency or data rate of the Reference clock and the respective data channel are thus by continuously adjusting the phase of the reference clock balanced. This makes it possible to have only one Reference clock to use for all data channels, though they are not synchronized.

In an advantageous development of the invention Procedures are adapted for each data channel using the Reference clock the data of the data channel sampled. The Ab keying frequency is identical to the data frequency of each current data channel. By using the DLL circuit it is ensured that between the reference clock and the Data channel the same phase position and the same frequency are present so that reliable scanning can take place.

However, it should be noted that others Applications of signal matching between the reference clock and the data channels are within the scope of the invention. For example, it can be provided that the respective in their  Clock frequency and phase position matched to each other Reference clock and data channel signals to control others Function groups can be used.

The arrangement according to the invention according to claim 6 also has Means for generating a reference clock a variety of Signal sampling blocks, each one data channel are assigned and to which the generated reference clock is supplied becomes. Each signal sampling block realizes one DLL circuit to compensate for the differences in the Clock frequency between the reference clock and the respective Da tenkanal.

The means for generating a reference clock include preferably a phase-locked loop circuit for extraction a reference clock from the data or a supplied one Clock of a data channel serving as a reference channel.

In the arrangement according to the invention, the individual Da channels and the respective assigned signal sampling blocks preferably constructed identically. This ensures that the individual data channels are identical Have transmission behavior.

The individual data channels are preferably with one receiver component, in particular a demultiplexer, or a transmission Building block, in particular a multiplexer connected. A ent speaking multiplexer or demultiplexer can basically implemented for any number of channels become.

The invention is described below with reference to the Figures of the drawing closer to an embodiment explained. Show it:

Figure 1 is a schematic representation of an inventive arrangement for generating a clock with a plurality of non-synchronous data channels.

Fig. 2 shows an arrangement according to the prior art;

Fig. 3 shows an embodiment of the arrangement according to the invention for a 4-Ka channel demultiplexer module, and

FIG. 4 shows the functional assemblies of a signal sampling block according to FIG. 3.

An arrangement according to the prior art, in which the necessary system clock is obtained separately for each channel using a phase-locked loop (PLL) circuit, was initially explained with reference to FIG. 2.

The arrangement according to the invention in FIG. 1 has a multiplicity of data channels 101 , 102,. , , 10 n, each of which a signal sampling block 20 , 21 ,. , , 2 n is assigned. The signal sampling blocks 20 , 21 ,. , , 2 n serve to receive data DI1, DI2,... On the respective data channels 101 , 102 , 10 n. , , DIN (DI - Data In) and the sampled data as data DO1, DO2,. , , Output DOn (DO - Data Out). The individual data channels 101 , 102,. , , 10 n are independent and not synchronized, so that the data rates on the different data channels can differ from one another.

To implement signal sampling, it is necessary to assign a reference clock to each signal sampling block. This is done in that any one of the data channels is selected as the reference channel (in FIG. 1 the data channel 101 ) and by means of the PLL circuit 1 a reference clock RT is obtained in a manner known per se from the data of the reference channel 101 or a clock supplied , The reference clock is made available to the PLL circuit by a voltage-controlled oscillator VCO (not shown).

The reference clock RT generated by the PLL circuit is supplied via a connecting line 2 to the individual signal sampling blocks 20 , 21 , 2 n. The individual signal sampling blocks 20 , 21 ,. , , 2 n each have a delay-locked loop (DLL) circuit 30 , 31 , 3 n. The DLL circuit determines the phase difference between the reference clock and the data signal of the respective data channel 101 , 102 ,. , , 10 n and adjusts the reference clock with respect to the data signal such that the data DI1, DI2,. , , D be scanned correctly.

The difference in clock frequency between the reference clock and the DLL circuit resembles the respective data channel by continuously adjusting the delay between the reference clock and data signal.

It is pointed out that a separate DLL circuit is also dispensed with for the reference channel and the clock generated by the PLL circuit 1 can be used directly. In this case, the PLL circuit 1 must generate the correct timing for the reference channel 101 . If the reference channel 101 also contains a DLL circuit, as in FIG. 1, the only task of the PLL circuit is to provide an independent reference clock for all signal sampling blocks 20 , 21 ,. , , To generate 2 n. Through the DLL circuits 30 , 31,. , , 3 n , the same phase and frequency of the reference clock and the respective data channel are then set for each data channel.

This is further explained below using the exemplary embodiment in FIGS. 3 and 4. Fig. 3 shows an arrangement for generating a clock for a 1: 2 demultiplexer module 4 for four data channels are Here, the number of four data channels only be understood as exemplary and the arrangement can in principle be realized, any other number of channels..

The individual data channels 101 , 102 , 103 , 104 and signal sampling blocks 20 , 21 , 22 , 23 are constructed in accordance with FIG. 1. The data channel 101 is again used as an example as the reference channel. The reference clock RT for signal sampling for all signal sampling blocks 20 , 21 , 22 , 23 is provided by the PLL circuit 1 .

The signal sampling blocks 20-23 each have two signal outputs, an output for the sampled, outgoing data DO1-DO4 and an output for a clock signal CO1-CO4 (CO = Clock Out). The clock signal CO1-C04 has a different clock than the reference clock RT, which is provided by the PLL circuit 1 . The clock signal CO1-CO4 is a clock pulse that is added or subtracted from the reference clock pulse RT with an additional frequency, as will be explained below.

The output signals of the individual signal sampling blocks 20-23 are fed to a 1: 2 demultiplexer 4 which converts the data DO1-DO4 into two data streams DO1a, DO1b,. , , DO4a, DO4b divides.

The functional components of a signal sampling block 2 n are shown schematically in FIG. 4. According to this, a DLL circuit has a phase detector PD 5 (phase detector), a charge pump CP 6 (charge pump) and a delay line or a phase shifter DL 7 (delay line).

The phase detector PD5 has as inputs the data signal DIn of the data channel 10 n under consideration and the phase-changed reference clock pulse COn which is fed back from the phase shifter DL7. The reference clock is the signal that is to be aligned to the data of the data channel 10 n using the DLL circuit. Depending on the phase difference, the phase detector PD5 generates a signal which it passes on to the charge pump CP 6 . The charge pump CP 6 essentially integrates the output signal of the phase detector 5 over time. The charge rag CP 6 controls the phase shifter DL 7 , which, in accordance with the "charge" of the charge pump CP 6, adapts the phase of the incoming reference clock RT at the phase shifter 7 . A state is set via the feedback loop in which the reference clock phase-delayed by the phase shifter 7 corresponds to the clock frequency of the data channel 10 n.

The differences in the clock frequency of reference clock and Data channel are thus continuously adjusted by the Phase of the reference clock balanced. This is possible because the frequency the derivation of the phase over time is: by the continuous change of the phase over time by means of the DLL circuit becomes an additional reference clock Frequency Δϕ / Δt added, so that the difference between the frequency of the reference clock and the data rate of the respective channel is balanced.

It is important that the delay line or phase shifter DL 7 of the DLL circuit has an infinite modulation range, ie the DLL circuit delays of ϕ = x + n.2π with x element from [0; 2π [and n element from N can generate. In addition, it is necessary that the bandwidth of the DLL circuit is greater than the difference between the clock frequency of the reference clock and the clock frequency of the data channel, ie Δω <Δϕ / Δt. For example, if the reference clock has a frequency of 100 MHz and the data channel has a frequency of 101 MHz, the bandwidth Δω of the DLL circuit must be at least 1 MHz.

Corresponding DLL circuits are, albeit in different Context, in detail in the above Publications, in particular US-A-5614855, EP-A2-0 349 715  and the article by T.H. Lee, K.S. Donnelly, J.T.C. Ho, J. Zerbe, M.G. Johnson and C. Eshikawa described on which is expressly referred to in this respect.

According to the article by T.H. Lee, K.S. Donnelly, J.T.C. Ho, J. Zerbe, M.G. Johnson and C. Eshikawa essentially become 4th Cycles with the phases 0 °, 90% 180 ° and 270 ° using two Mixers and a controller mixed so that all phases can be covered. It is always done by one Quadrants switched to the next so that one infinite phase shift can be achieved.

The bandwidth of the DLL circuit can be set almost arbitrarily by means of the dimensioning of the charge pump CP 6 , which represents a loop filter. The CP 6 charge pump consists of a switched current source and an integration capacitor. This achieves the function of an integrator which, together with the remaining loop gain, gives the bandwidth of the control loop.

At the output of the signal sampling block 2 n there is the reference clock COn, which is adapted in its phase and thus also in its frequency, as well as the output data DOn of the data channel 10 n sampled with the clock COn.

It should be noted that the example of a Demulti plexer module is only to be understood as an example. That he principle according to the invention can also be used for transmitting modules, e.g. B. Use multiplexers.

In alternative exemplary embodiments, the reference clock RT is not generated from the data by means of a PLL circuit or a clock supplied with a data channel, but instead is provided by an independent clock generator, in particular a high-precision quartz oscillator, which is connected to the connecting line 2 . The described method and the described arrangement are otherwise unchanged.

The invention is not limited in its application the embodiments shown above. Essential the only thing for the invention is that by means of a PLL circuit a reference clock is obtained from a data channel Reference clock is passed to the other data channels and a Compensating the differences in the clock frequency between the Reference clock and the other data channels using a DLL circuit.  

LIST OF REFERENCE NUMBERS

1

PLL

2

connecting line

2

n signal sampling blocks

3

n DLL circuit

4

Demultiplexer module

5

phase detector

6

charge pump

7

phase shifter

101

reference channel

10

n data channels

11

n PLL circuit
RT reference clock
DIn input data of the nth signal sampling block
DOn output data of the nth signal sampling block
COn output clock of the nth signal sampling block

Claims (11)

1. Method for generating a clock in a data processing system with a large number of independent, non-synchronous digital data channels, characterized by the steps:

• - obtaining a reference clock (RT),
• - Feeding the obtained reference clock (RT) to the data channels ( 101-10 n), and
• - Compensation of the differences in the clock frequency between the reference clock (RT) and the data channels ( 101-10 n) each by means of a delay-locked loop (DLL) circuit ( 30-3 n).

2. The method according to claim 1, characterized in that the reference clock from the data or a supplied clock of a data channel ( 101 ) serving as a reference channel is obtained by means of a phase-locked loop (PLL) circuit ( 1 ). 3. The method according to claim 1, characterized characterized in that the reference clock by a independent clock generator, especially a quartz Oscillator is won. 4. The method according to at least one of claims 1 to 3, characterized in that for each data channel ( 101-10 n) by means of the respective delay-locked loop (DLL) circuit ( 30-3 n), the phase of the reference clock (RT) is continuously adapted to the phase of the data channel. 5. The method according to at least one of claims 1 to 4, characterized in that for each data channel ( 101-10 n) by means of the adapted reference clock (COn), the data of the data channel are sampled. 6. Arrangement for generating a clock in a data processing system with a large number of independent, non-synchronous digital data channels, characterized by
Means ( 1 ) for generating a reference clock (RT),
a plurality of signal sampling blocks ( 20-2 n), each associated with a data channel ( 101-10 n) and to which the generated reference clock is fed, whereby
each signal sampling block ( 20-2 n) has a delay-locked loop (DLL) circuit ( 30-3 n) for compensating for the differences in the clock frequency between the reference clock (RT) and the respective data channel, which has an infinite delay range and a Bandwidth that is greater than the difference between the frequency of the reference clock (RT) and the frequency of the respective data channel ( 101-10 n). 7. Arrangement according to claim 6, characterized in that the means for generating a reference clock (RT) a phase-locked loop (PLL) circuit ( 1 ) for obtaining a reference clock (RT) from the data or a supplied clock as a reference channel serving data channel ( 101 ). 8. Arrangement according to claim 6, characterized characterized in that the means for generating a Reference clock (RT) a clock generator, especially one Quartz oscillator include.   9. Arrangement according to at least one of claims 6 to 8, characterized in that the delay-look-loop (DLL) circuit ( 30-3 n) each have a phase detector ( 5 ), a charge pump ( 6 ) and a phase shifter ( 7 ) having. 10. The arrangement according to at least one of claims 6 to 9, characterized in that the individual data channels ( 101-10 n) and the associated signal sampling blocks ( 20-2 n) are each constructed identically. 11. The arrangement according to at least one of claims 6 to 10, characterized in that the data channels ( 101-10 n) with a receiver module ( 4 ), in particular a demultiplexer, or a transmission module, in particular a multiplexer, are connected.