DE10145765A1 - Semiconducting structure for controling current has channel region with channel conduction region of first conductivity type and higher than basic doping level of channel region - Google Patents

Abstract

The arrangement has at least a first semiconductor region (2) of a first conductivity type at least partly containing a current path and a channel region (22) forming part of the first region with a basic doping level and current influenced by at least one depletion zone (23,24). The channel region has a channel conduction region (225) for guiding a current that is of the first conductivity type with higher than the basic doping level. AN Independent claim is also included for the following: a method of manufacturing a semiconducting structure for controling a current.

Description

The invention relates to a semiconductor structure for control a current, the semiconductor structure being at least one first semiconductor region of a first conductivity type (n or p), one at least partially within the first Semiconductor area trending current path and a channel area that part of the first semiconductor region, which is a basic doping has, and within which the current by means of at least a depletion zone can be influenced. Such a Semiconductor structure is for example from US 6,034,385 known. The invention also relates to a method for Manufacture of a semiconductor structure.

To supply an electrical consumer with a The nominal electrical current is usually exceeded by the consumer a switching device to an electrical supply network connected. When switching on and also in the event of a Short circuit occurs an overcurrent that is significantly higher than that Rated current is. To protect the electrical consumer that must be between the consumer and the electrical network switched switching device limit this overcurrent and also can switch off. Furthermore there is for example in the Converter technology Applications in which the consumer in Also safe in the event of reverse voltage to be separated from the supply network. For the Functions described are current-limiting switches in the form of a Semiconductor structure known.

Thus, in US 6,034,385 and also in WO 00/16403 A1 describes a semiconductor structure in which a current flow controlled between a first and a second electrode becomes. In particular, the current can be switched on and off or can be limited to a maximum value. The active part of the Semiconductor structure consists of a first semiconductor region a given line type, especially the n-conductivity type. The type of line is determined by the type of Charge carriers with which the semiconductor region is doped. to Current control is within the first semiconductor area at least one lateral channel area is provided. Under laterally or horizontally, a direction becomes parallel to a main surface of the first semiconductor region Roger that. In contrast, vertical becomes perpendicular to Main surface called direction. The lateral Channel area is characterized by at least one p-n junction, in particular through the depletion zone (zone with depletion on Charge carriers and thus high electrical resistance; Space charge zone) of this p-n transition, limited in the vertical direction. The vertical extent of this depletion zone can be under other can be set by a control voltage. The p-n Transition is between the first semiconductor region and one buried p-type island area formed. The buried The island area is used to shield the first electrode against the high electric field in the reverse direction or when switched off. In special embodiments the channel area can also be crossed by another depletion zone be limited in the vertical direction. This one more Depletion zone is, for example, by another p-n junction between a second p-type semiconductor region and the first n-type semiconductor region. Also the second p-type semiconductor region can be formed using a Control electrode to be connected to a control voltage. The channel area relevant for current control is arranged within an epitaxial layer. In the preparation of this epitaxial layer can cause variations in thickness and the dopant concentration. This affects directly on the current controlling properties of the Canal area. It is therefore possible that the semiconductor structure on End of the manufacturing process due to the tolerances of the Epitaxial layer is not what is required Current control behavior, for example a certain pinch-off voltage, having. This reduces the yield that can be achieved.

A similar semiconductor structure is described in DE 196 29 088 A2 described. Consequently, this can also happen Semiconductor structure at a similar low technology-related yield come in the making.

Furthermore, US 5,543,637 is a semiconductor structure discloses a first semiconductor region of a first Line type with a buried island area one to the first opposite conductivity type as well as two electrodes and a control electrode. The through the control electrode and the buried island area evoked each Depletion zones again form a channel area in which a Controlled current flowing between the two electrodes becomes. The control electrode is either a Schottky contact or designed as a MOS contact. As a semiconductor material 3C, 6H or 4H silicon carbide (SiC) used. Here too the channel region is arranged in an epitaxial layer, the Thickness and dopant concentration are subject to fluctuations are.

Furthermore, DE 198 33 214 C1 in particular in SiC realized semiconductor structure known in which Current control one of two p-type semiconductor areas limited n-type lateral channel region is provided. Again the canal area is in one Epitaxial layer, so that here too from the above Reduced yield in production is possible for reasons.

The invention is based on the object, one Semiconductor structure of the type specified at the beginning, which at manufacturing insensitive to technology-related Fluctuations and a high yield is possible. Moreover is supposed to be a manufacturing process for such Semiconductor structure can be specified.

To solve the problem related to the semiconductor structure a semiconductor structure according to the features of independent claim 1 specified.

In the semiconductor structure according to the invention for control a current is a semiconductor structure of the type described at the outset, which is characterized in that the canal area is intended to carry electricity Channel line area that compared the first line type and one has higher doping with the basic doping.

The invention is based on the knowledge that through an additional zone provided in the channel area with a compared to the rest of the channel area higher Dopant concentration the sensitivity of the semiconductor structure against technology-related fluctuations in Manufacturing significantly reduced, if not completely can be eliminated. The additional zone provided here is referred to as a sewer line area, with Dopants of the same charge carrier type (n or p) as that Channel area endowed. It essentially determines that electrical properties of the channel area. So the current in the Pass-through operation due to the higher doping and thus accompanying higher conductivity preferred in the Channel line area led. The rest of the canal area remains on the other hand largely free of electricity, so that any existing here Fluctuations in the basic funding or the thickness then none or only play a subordinate role. The Channel line area can, for example, by means of a Ion implantation with very high accuracy and little fluctuation manufactured in the dopant concentration and the thickness become. With this new independence compared to the technology-related fluctuations increased yield in the manufacturing process of Semiconductor structure.

Advantageous embodiments of the semiconductor structure according to the Invention result from those dependent on claim 1 Claims.

In a favorable embodiment, this contains Channel area at least 80% of the total in the channel area existing total charge of the first line type. With that at most only the remaining 20% of the total load that located outside the sewer area in the sewer area are subject to technology-related fluctuations. This positive effect can be further increased by even at least 90% of those within the canal area Total charge of the first line type in the sewer line area are provided.

A so-called vertical semiconductor structure is favorable which the current passes through essentially in the vertical direction the semiconductor structure is performed. This embodiment is capable of a particularly high reverse voltage in the event of blocking to wear.

The current is controlled preferably by means of a lateral canal area. In this embodiment, both the current to be carried safely switched on and off as also a high reverse voltage is absorbed by the semiconductor structure become.

In a further preferred variant, the Semiconductor structure in the form of a field effect transistor, in particular in the form of a junction field effect transistor (JFET). This type of transistor is particularly suitable for the Desired in connection with the present invention Current control.

In an advantageous embodiment, the Semiconductor structure partially or completely from one Semiconductor material that has a band gap of at least 2 eV.

Suitable semiconductor materials are, for example, diamond, Gallium nitrite (GaN), indium phosphite (InP) or preferably Silicon carbide (SiC). Because of the extremely low intrinsic charge carrier concentration (= Charge carrier concentration without doping) and the very low transmission loss are the semiconductor materials mentioned, in particular SiC, very advantageous. The semiconductor materials mentioned have also compared to the "universal semiconductor" silicon a significantly higher breakdown strength, so that the Semiconductor structure can be used at a higher voltage can. The preferred semiconductor material is silicon carbide, in particular monocrystalline silicon carbide of 3C or 4H or 6H or 15R poly type.

A variant is also possible in which the Semiconductor structure at least within the first semiconductor region partially buried island area. This island area has a second compared to the first line type (n or p) opposite line type (p or n). The island area forms a p-n junction with the first semiconductor region, its depletion zone to control the channel area and so that the current flow can also be used.

In another advantageous embodiment is inside of the sewer line area at least one Channel compensation area arranged. Preferably, the duct line area contains several of these channel compensation areas. The Channel compensation area has in particular a doping with second versus first line type (n or p) opposite line type (p or n). The in the Channel compensation areas compensate for existing charge when it is present Reverse control voltage that existing in the sewer line area Charge so that the dopant concentration of the first Charge carrier types in the sewer line area can be further increased can. Thanks to the compensation, this does not lead to one Deterioration of the electrical behavior of the Semiconductor structure, especially not to an undesirable increase in necessary for the complete restriction of the canal area Control voltage (= pinch-off voltage). This offers in particular then advantages if a small pinch-off tension for example, below 15 V is required. From an increase in Dopant concentration of the first conductivity type in the Channel area by at least a factor of 2 compared to the Embodiment without channel compensation areas is the by the compensation areas caused loss of area due to then significantly increased conductivity in the Sewer area at least made up for, if not overcompensated.

It is advantageous if the at least one Channel compensation area or, in the case of multiple channel compensation areas, the individual channel compensation areas each have a higher one Has dopant concentration as the channel conduction area or to have. The area share of the sewer pipe area is then larger than that of all channel compensation areas. This is favorable because the electricity is within the sewer area should be carried out and therefore as large as possible Share of the sewer line area should be available for this. At the same time, the described advantageous remains receive a compensating effect in the event of a lock.

An embodiment is preferred in which the Channel line area total existing total charge of the first Line type is approximately the same size as that in all Channel compensation areas existing total charge of the second Conductivity type. Then a very good compensation effect reached.

In another advantageous variant, the channel area arranged within an epitaxial layer. The technology-related fluctuations in dopant concentration and Thickness within the epitaxial layer play due to the additionally existing sewer line area from the above reasons mentioned do not matter. It is also possible that the first semiconductor region has a second epitaxial layer has, in particular as one in the event of a lock essential part of the applied reverse voltage receiving drift zone is trained. Meet the two epitaxial layers different tasks each. One serves the Current control, the other of reverse voltage consumption. Conveniently, both epitaxial layers can still with one Another variant has essentially the same basic funding exhibit. Thanks to the power control behavior significantly determining channel line area, the basic doping of Epitaxial layer in which the channel region is arranged after other points of view. It is cheap namely if it's at the interface between the two Epitaxial layers come to no doping jump. The Semiconductor structures can then carry a higher reverse voltage.

There is also a variant in which the first Semiconductor region is arranged on a substrate that the to first line type has opposite line type. Then are both types of charge carriers on the power supply - Electrons and holes - involved. Because of the bipolar modulation there is a very favorable power line behavior. In addition, the additional p-n transition between the suitability for the first semiconductor region and the substrate a high reverse voltage.

To solve the problem relating to the procedure, a Method according to the features of claim 17 specified. In the manufacturing method according to the invention a semiconductor structure for controlling a current is a procedure in which at least one Semiconductor substrate is provided, an epitaxial layer with a Basic doping is applied to the semiconductor substrate, wherein the epitaxial layer is a channel area within which the current can be influenced, includes, and one for Conducting specific channel line area with compared to the Basic doping of higher doping at least in the area of Channel area is implanted in the epitaxial layer.

This method is particularly advantageous because usually only one using an epitaxial procedure Basic funding with a relatively high fluctuation range for example of about ± 15%. By means of a Ion implantation used to manufacture the Doping can be used in the channel line area set much more precisely. The sewer pipe area, which for the current control is decisive, then has only one little fluctuation in its dopant concentration.

Refinements of the method are advantageous accordingly the claims dependent on claim 17.

A method variant in which another epitaxial layer on the semiconductor substrate is applied. The two epitaxial layers are preferably successively and one above the other on the semiconductor substrate applied. It is also beneficial if the two Epitaxial layers have essentially the same basic doping exhibit. The ion implantation of the duct area takes place after completion of the epitaxial process steps to Application of the two epitaxial layers instead. This method enables the production of a high yield Current control certain semiconductor structure, the particular has the advantages mentioned above.

Preferred but not limiting Embodiments of the invention will now be described with reference to the drawing explained in more detail. The drawing is not for clarification run to scale, and certain features are represented schematically. Show in detail:

Fig. 1 and Fig. 2 shows a semiconductor structure having an inside of a channel region arranged highly doped channel conduction region, and

Fig. 3 of the doping profile in the semiconductor structure of FIG. 1 and 2 provided for channel conduction region,

Fig. 4 shows a further semiconductor structure with channel conduction region and channel compensation areas,

Fig. 5 shows a cross section through the channel conduction region and the channel compensation regions of the semiconductor structure of FIG. 4 and

Fig. 6 to Fig. 8 shows a further semiconductor structure with channel conduction region.

Corresponding parts are provided with the same reference numerals in FIGS. 1 to 8.

In Fig. 1, a semiconductor construction 100 is illustrated a vertical junction field effect transistor (JFET) for controlling a current I in the form. The semiconductor structure shown in FIG. 1 is only a half cell. A complete cell is obtained by mirroring on the right edge of the half cell. A multi-cell structure accordingly results from multiple mirroring.

The active part, in which the current control essentially takes place, is contained in an n-type (electron line) first semiconductor region 2 . A p-type (hole line) buried island region 3 is arranged within the first semiconductor region 2 . The first semiconductor region 2 has a first surface 20 , the buried island region 3 has a second surface 80 . Both surfaces 20 and 80 run essentially parallel to one another. In the exemplary embodiment of FIG. 1, the first semiconductor region 2 is composed of a semiconductor substrate 27 and two epitaxially grown semiconductor layers 261 and 262 arranged thereon. The first surface 20 belongs to the second epitaxial layer 262 and the second surface 80 belongs to the first epitaxial layer 261 . The two epitaxial layers 261 and 262 have essentially the same basic doping. They are less doped (n ^- ) than the semiconductor substrate 27 (n ⁺ ).

An n-type contact area 5 embedded within the island area 3 is provided on the second surface 80 . It is highly endowed (n ⁺ ). The island area 3 extends in all directions parallel to the first surface 20 further than the contact area 5 .

100 silicon carbide (SiC) is used as the semiconductor material in the semiconductor structure. It is particularly well suited for high voltages due to its specific material properties. Preferred dopants are boron and aluminum for p-doping and nitrogen and phosphorus for n-doping. The dopant concentration of the contact region 5 is typically between 1 × 10 ¹⁹ cm ^-3 and 1 × 10 ²⁰ cm ^-3 and that of the two epitaxial layers 261 and 262 is typically at most 5 × 10 ¹⁶ cm ^-3 . The character "x" is used here as a multiplication symbol. The doping of the first epitaxial layer 261 depends, in particular, on the blocking voltage to be absorbed by the semiconductor structure 100 in the event of blocking. The higher the reverse voltage, the lower this doping. The epitaxial layer 261 essentially has to carry the electric field to be blocked. In the example shown, both epitaxial layers 261 and 262 have a basic doping of approximately between 5 × 10 ¹⁵ cm ^-3 and 7 × 10 ¹⁵ cm ^-3 . The reverse voltage is then at least 1200 V.

The buried island region 3 and the contact region 5 embedded therein are preferably produced after the application of the first epitaxial layer 261 . In particular, the self-adjusting masking technique described in US Pat. No. 6,204,135 B1 can be used. The island region 3 and the contact region 5 are accordingly generated by means of two masking steps and an ion implantation of p- or n-dopant particles into the second surface 80 . The second epitaxial layer 262 is then applied in a second epitaxial growth step.

A contact hole 70 is provided within the second epitaxial layer 262 and extends in the vertical direction up to the second surface 80 . The contact hole 70 exposes both part of the buried island region 3 and part of the contact region 5 , so that both regions 3 and 5 can be contacted ohmically by means of a first electrode 50 made of an electrically conductive material. The contact area 5 and the island area 3 are briefly closed by the first electrode 50 . Polysilicon or a metal, preferably nickel, aluminum, tantalum, titanium or tungsten, can be used as the material for the first electrode 50 . The contact hole 70 is produced, for example, by means of a dry etching process. In order to compensate for fluctuations in the etching depth, a plurality of contact holes 70 , which then each have a smaller diameter, can also be provided in accordance with an embodiment which is not shown.

A second electrode 60 is provided on a side of the first semiconductor region 2 facing away from the first surface 20 . The current I flowing through the semiconductor structure 100 is fed in and out by means of the two electrodes 50 and 60 . Because of the essentially vertical current path, that is to say perpendicular to the first surface 20 , the semiconductor structure 100 is also referred to as vertical.

A first depletion zone 24 , which is adjacent to the first surface 20 and is located within the first semiconductor region 2, is arranged laterally (= laterally) next to the contact hole 70 . Furthermore, there is a pn junction between the first semiconductor region 2 and the buried island region 3 , the depletion zone of which is referred to here as the second depletion zone 23 . The second depletion zone 23 surrounds the entire buried island area 3 . Insofar as the two depletion zones 23 and 24 extend within the first semiconductor region 2 , they are shown in broken lines in FIG. 1. The first and second depletion zones 24 and 23 delimit in the vertical direction a lateral channel region 22 which lies within the first semiconductor region 2 and is part of the current path between the first and second electrodes 50 and 60 . The first depletion zone 24 and the buried island area 3 are arranged such that the two depletion zones 23 and 24 overlap at their lateral edges in a projection onto the first surface 20 . The lateral channel area 22 is located precisely within this overlap area.

In the lateral direction, the lateral channel region 22 is delimited by an edge 221 on the side facing the contact hole 70 . This edge 221 is formed by a projection of the contact region 5 into the first semiconductor region 2 perpendicular to the first or second surface 20 or 80 . The second depletion zone 23 serving as the lower vertical boundary no longer extends into the first semiconductor region 2 from the point at which the heavily n-doped contact region 5 is arranged within the island region 3 . The pn junction relevant for such a depletion zone runs from this point between the n-type contact area 5 and the p-type island area 3 . The lateral edge 221 is thus determined by the position of the contact area 5 within the island area 3 . The second lateral edge of the lateral channel region 22 , which is not shown in more detail in FIG. 1, is determined by the lateral dimension of the island region 3 . These geometry parameters can be set very precisely by the structuring method described in US Pat. No. 6,204,135 B1.

The first depletion zone 24 and the contact area 5 are arranged in relation to one another such that they overlap by 1 to 2 μm in a common plane at their lateral edges in a projection made perpendicular to the first or second surface 20 or 80 . This last-mentioned overlap ensures that the lateral edge 221 reaches as far as the contact area 5 .

The length (= lateral extent) of the lateral channel region 22 is typically between 1 μm and 5 μm in the case of a semiconductor structure 100 produced from silicon carbide. The lateral channel region 22 is preferably as short as possible. Then there is a very compact overall structure with a small footprint. The vertical expansion is typically between 0.5 µm and 2 µm in the voltage and current-free state. The depletion zones 23 and 24 are characterized by severe depletion of charge carriers and thus have a significantly higher electrical resistance than the lateral channel region 22 which they delimit in the vertical direction. The spatial extent of the two depletion zones 23 and 24 , in particular in the vertical direction, varies depending on the current and voltage conditions.

The lateral channel region 22 thus decisively determines the (control) behavior of the entire semiconductor structure 100 . In the case of a design as a current limiter, the behavior when an operating voltage is applied in the forward direction (= forward direction) depends on the electrical current I flowing between the two electrodes 50 and 60 through the semiconductor structure 100 . As the current strength increases, the forward voltage drop between electrodes 50 and 60 increases due to the path resistance. This leads to an enlargement of the depletion zones 23 and 24 and consequently to a reduction in the current-carrying cross-sectional area in the lateral channel region 22 associated with a corresponding increase in resistance. When a certain critical current value (= saturation current) is reached, the two depletion zones 23 and 24 touch and completely seal off the lateral channel region 22 .

Such a channel restriction can also be achieved by applying a control voltage to the semiconductor structure 100, in particular in such a way that the first depletion zone 24 is enlarged in the vertical direction. The control voltage that must be applied between the first and second electrodes 50 and 60 when the voltage disappears in order to achieve a channel pinch-off is also called a pinch-off voltage.

The current path between the first and second electrodes 50 and 60 includes the contact region 5 in the forward direction, the lateral channel region 22, a vertical channel region 21 arranged in the first semiconductor region 2 , and a subsequent drift zone, which results from the remaining part of the first epitaxial layer 261 and composed of the substrate 27 .

When an operating voltage is applied in the reverse direction, on the other hand, the current flows essentially via a reverse diode 90 , which is formed by the buried island region 3 and the part of the first semiconductor region 2 lying underneath.

The behavior of the lateral channel region 22 , which is decisive for the current control, is determined in particular by the second epitaxial layer 262 . The properties of the second epitaxial layer 262 influence in particular the pinch-off voltage, a voltage applied to control the first depletion zone 24 , from which a current flows between the depletion zone 24 and the buried island region 3 (= penetration voltage), the maximum between the two electrodes 50 and 60 flowing current I (= saturation current), the electrical resistance in the channel region 22 and also to a certain extent the maximum permissible reverse voltage. However, the properties of the second epitaxial layer 262 can now have fluctuations due to technology. The dopant concentration in the grown second epitaxial layer 262 fluctuates. These fluctuations in the doping can account for up to ± 15% of the basic doping. Even higher deviations are also possible. In addition, the thickness of epitaxial layer 262 may vary over the cross section of semiconductor device 100 . These technology-related fluctuations may have a negative effect on the desired behavior of the lateral channel region 22 .

In order to eliminate this influence, an n-conducting channel line region 225 is arranged in the second epitaxial layer 262 , which also extends into the channel region 22 and which in particular has a higher doping than the basic doping of the second epitaxial layer 262 and the rest of the channel region 22 . As a result, the channel line region 225 has a significantly higher electrical conductivity than the rest of the channel region 22 . In the forward mode, the current I is carried essentially within the channel line region 225 . Consequently, the channel line region 225 largely determines the current control behavior of the semiconductor structure 100 .

The channel conduction region 225 is formed by implanting n-type dopant particles into the second epitaxy region 262 . The doping of the channel line region 225 can thus be set very precisely. In particular, in contrast to an epitaxially produced layer, there are no comparable fluctuations in the doping and the thickness. The main portion, ie in particular at least 80%, of the total doping of n-type charge carriers present within the channel region 22 is located in the channel line region 225 . In the example shown, the implanted dopant concentration in the channel line region 225 is selected such that an average dopant concentration of approximately 2 × 10 ¹⁶ cm ^-3 is present in the entire channel region 22 . This corresponds to a common dopant concentration, which is present evenly distributed within the channel region 22 in a semiconductor structure (not shown) without a channel line region 225 . However, in this embodiment, which is not shown, the epitaxial fluctuations in the dopant concentration significantly influence the behavior of the channel region 22 , the fluctuations in the second epitaxial layer 262, which is now provided with a basic doping of approximately 7 × 10 ¹⁵ cm ^-3 , has practically no influence on the current control behavior of the semiconductor structure 100 , The main part of the total charge present in the channel region 22 is located in the channel line region 225 which is produced practically without doping fluctuations.

A further advantage of the semiconductor structure 100 compared to the embodiment not shown without a channel line region 225 is that the channel line region 225 at least largely or even completely prevents an otherwise possible field penetration into the channel region 22 and the associated shifting of the pinch-off voltage in the event of a blockage.

Due to the ion-implanted channel line region 225 , the semiconductor structure 100 can be produced reproducibly with a very high yield and very precisely defined electrical properties (e.g. pinch-off voltage, loop-through voltage, channel resistance, saturation current, reverse voltage). If, as usual, a semiconductor wafer is used in production in order to be able to produce many semiconductor structures 100 at the same time, a very high homogeneity of the doping in all channel line regions 225 is achieved due to the ion implantation used across the entire semiconductor wafer.

The depletion zone 24 , which also influences the channel region 22 , can be created in various ways within the first semiconductor region 2 . Embodiments known from WO 00/16403 A1 for this purpose include a Schottky contact or MOS (Metal Oxide Semiconductor) contact arranged on the first surface 20 .

Furthermore, as in the case of a semiconductor structure 101 shown in FIG. 2, a second semiconductor region 4 can also be arranged on the first surface 20 within the first semiconductor region 2 . The semiconductor region 4 has the opposite conduction type to the first conduction type of the first semiconductor region 2 , that is to say the p-conduction type in the exemplary embodiment shown. It is preferably produced by ion implantation. The second semiconductor region 4 is in particular heavily p-doped (p ⁺ ). A pn junction is present between the first semiconductor region 2 and the second semiconductor region 4 , the depletion zone of which forms the depletion zone 24 shown in FIG. 1. For reasons of better clarity, no depletion zones are entered in the semiconductor structure 101 from FIG. 2. The second semiconductor region 4 is in ohmic contact with a control electrode 40 , so that the extent of the depletion zone 24 and thus the current flow in the channel region 22 and in the channel line region 252 can be influenced via an external control voltage.

The semiconductor structure 101 is an active arrangement, since the current flow within the semiconductor structure 101 can be influenced by an external measure (control voltage). However, for example from WO 00/16403 A1, other embodiments not shown here are also known which lead to passive current control and which in principle can likewise be combined with the advantageous channel line area 225 for current routing and control.

In Fig. 3, a typical doping profile is shown for a channel conduction region 225. In the diagram, a dopant concentration ND is plotted over a depth T of the channel region 22, which is also entered in FIG. 2. The basic doping of the second epitaxial layer 262 and also the additional doping introduced into the channel line region 225 by ion implantation can be seen.

The channel line region 225 provides an additional degree of freedom in the design of the semiconductor structure 100 or 101 . The current carrying behavior is mainly determined by the doping within the channel line region 225 , whereas the basic doping of the remaining channel region 22 and the second epitaxial layer 262 is of secondary importance in this regard. This means that the basic funding can be selected based on other criteria. In particular, it is favorable if the basic doping of the second epitaxial layer 262 is equal to the doping of the first epitaxial layer 261, which is essentially determined by the blocking voltage to be carried. Then there is no doping jump at the interface 80 between the two epitaxial layers 261 and 262 . Such a jump in doping could otherwise lead to undesired field distortions in the boundary region of the two epitaxial layers 261 and 262 , which could result in a restriction of the maximum usable blocking field strength or the maximum achievable blocking voltage.

FIG. 4 shows a particularly favorable semiconductor structure 102 in which the high concentration of n-type charge carriers in the channel line region 225 is at least partially compensated for by p-type channel compensation regions 226 . In order to achieve the best possible current conductivity in the channel line region 225 , the highest possible charge carrier concentration is desirable. On the other hand, an excessively high charge carrier concentration leads to an increase in the pinch-off voltage to be applied to the control electrode 40 , which is required in order to completely pinch off the channel region 22 . Because of the channel compensation areas 226 embedded in the channel line area 225 , there is no undesirable increase in the pinch-off voltage, even if a very high dopant concentration is provided within the channel line area 225 . The total charge on p-type charge carriers, which are located within all channel compensation regions 226 , is advantageously approximately the same size as the total charge on all n-type charge carriers in the channel line region 225 . To achieve this, the dopant concentration in the p-type channel compensation regions 226 is higher than in the n-type channel line region 225 . The reason for this lies in the larger base area of the channel line area 225 compared to the base area of all channel compensation areas 226 .

These area ratios can be clearly seen from the cross-sectional illustration of the duct line region 225 and the duct compensation regions 226 shown in FIG. 5. The course of the current I within the channel line region 225 is also shown in FIG. 5. The cross-sectional area of the channel compensation areas 226 can take on other shapes besides the round geometry shown, for example a square or a strip shape.

The advantageous effect of the channel region 225 can also advantageously be used in other fundamentally possible embodiments of the semiconductor structure, for example in a semiconductor structure 103 according to FIG. 6 or in a semiconductor structure 104 according to FIG. 7. Apart from the channel line region 225 , the semiconductor structure 103 is known from WO 00/16403 A1 and the semiconductor structure 104 from DE 198 33 214 C1. Just like the semiconductor structures 100 , 101 and 102 disclosed in the previous figures, the semiconductor structures 103 and 104 are each also a junction field-effect transistor, which are implemented in particular in the semiconductor material SiC.

In addition to the semiconductor structures 100 to 104 shown in FIGS. 1, 2, 4, 6 and 7, there are also embodiments in which a p-type substrate 28 is used instead of the n-type substrate 27 . Such a semiconductor structure 105 is shown by way of example in FIG. 8. It is a vertical JFET with a rear bipolar emitter (= BiFET). The first semiconductor region 2 is then composed only of the two n-type epitaxial layers 261 and 262 and forms a pn junction with the p-type substrate 28 . This additional pn transition is particularly advantageous when used at a high voltage, which is, for example, at least of the order of a few kV.

It is furthermore favorable that 60 holes are injected into the semiconductor structure 105 via the contact and 50 electrons via the contact in the forward mode. This leads to a sharp increase in the charge carrier concentration. This bipolar modulation of the charge carrier concentration leads to particularly good current conduction behavior.

In order to prevent the p-type island region 3 from directly sucking off the holes injected from the electrode 60 and, as a result, the concentration of the charge carriers available for current transport, in particular below the channel line region 225, to decrease, a strong n-type shielding region is preferably used 31 is provided between the first semiconductor region 2 and the island region 3 . The shielding region 31 represents an effective barrier against a direct outflow of the injected holes into the island region 3. As a result, a favorable, high bipolar charge carrier concentration is maintained below the channel line region 225 .

The dopant concentration of the shielding region 31 is typically one to two orders of magnitude above that of the first epitaxial layer 261 . In the example shown, it is approximately 10 ¹⁷ cm ^-3 . The shielding region 31 surrounds the island region 3 in particular on the sides facing the substrate 28 and the vertical channel region 21 . However, this complete shielding is not absolutely necessary. The shielding area 31 can also be provided only in regions below the island area 3 .

The channel line region 225 also has a similarly positive shielding effect as the shielding region 31 . It prevents the holes from flowing into the p-type second semiconductor region 4 . In addition to the improved modulation of the charge carrier concentration, the leakage current through the control electrode 40 is thereby reduced.

The line types provided in the respective regions in all of the semiconductor structures 100 to 105 shown can, in alternative embodiments, also take the opposite line type.

In each embodiment, the channel line region 225 has a favorable effect on the current control behavior and in particular leads to a manufacturing process that is largely independent of technology-related fluctuations. In this way, a very high yield can be achieved in the production.

Claims (18)

1. A semiconductor structure for controlling a current (I) comprising at least: a) a first semiconductor region ( 2 ) of a first conductivity type, b) a current path running at least partially within the first semiconductor region ( 2 ) and c) a channel area ( 22 ), 1. is part of the first semiconductor region ( 2 ), 2. which has a basic funding, and 3. within which the current (I) can be influenced by means of at least one depletion zone ( 23 , 24 ), characterized in that 1. the channel area ( 22 ) comprises a channel line area ( 225 ) intended for current conduction, which has the first line type and a higher doping compared to the basic doping. 2. The semiconductor structure according to claim 1, wherein the current path in runs essentially in the vertical direction. 3. Semiconductor structure according to claim 1 or 2, in which the channel region ( 22 ) is designed as a lateral channel region. 4. Semiconductor structure according to one of the preceding claims, which as a field effect transistor, especially as a junction Field effect transistor is formed. 5. Semiconductor structure according to one of the preceding claims, in which silicon carbide is provided as the semiconductor material. 6. Semiconductor structure according to one of the preceding claims, in which an island region ( 3 ), which is at least partially buried within the first semiconductor region ( 2 ), of a second line type opposite to the first line type is arranged. 7. Semiconductor structure according to one of the preceding claims, in which the total discharge of the first conduction type present within the channel region ( 22 ) is at least 80%, in particular at least 90%, within the channel conduction region ( 225 ). 8. Semiconductor structure according to one of the preceding claims, in which at least one channel compensation area ( 226 ) is arranged within the channel line region ( 225 ). 9. The semiconductor structure according to claim 8, wherein the at least one channel compensation region ( 226 ) has a second conduction type opposite to the first conduction type. 10. The semiconductor structure according to claim 8 or 9, wherein the at least one channel compensation region ( 226 ) has a higher dopant concentration than the channel line region ( 225 ). Semiconductor structure according to one of Claims 8 to 10, in which the total charge of the first conduction type introduced into the channel line region ( 225 ) is approximately the same as that into the one channel compensation region ( 226 ) or, in the case of a plurality of channel compensation regions ( 226 ), into all channel compensation regions ( 226 ) introduced total charge of the second conduction type. 12. Semiconductor structure according to one of the preceding claims, in which the channel region ( 22 ) is arranged in an epitaxial layer ( 262 ). 13. The semiconductor structure according to claim 12, wherein the doping of the epitaxial layer ( 262 ) is equal to the basic doping. 14. Semiconductor structure according to one of the preceding claims, in which the first semiconductor region ( 2 ) comprises two epitaxial layers ( 261 , 262 ) with essentially the same doping. 15. Semiconductor structure according to one of the preceding claims, in which the first semiconductor region ( 2 ) is arranged on a substrate ( 28 ) of a second conductivity type opposite to the first conductivity type and the current path also runs through the substrate ( 28 ). 16. The semiconductor structure as claimed in claim 15, in which an island region ( 3 ) of the second conduction type which is at least partially buried within the first semiconductor region ( 2 ) is arranged and a shielding region ( 31 ) is arranged on at least one side of the island region ( 3 ) facing the substrate ( 28 ). of the first conductivity type is arranged between the island region ( 3 ) and the first semiconductor region ( 2 ). 17. A method for producing a semiconductor structure for controlling a current (I), in which at least: a) a semiconductor substrate ( 27 ) is provided, b) an epitaxial layer ( 262 ) with a basic doping is applied to the semiconductor substrate ( 27 ), the epitaxial layer ( 262 ) including a channel region ( 22 ) within which the current (I) can be influenced, and c) a channel line region ( 225 ) intended for carrying current is implanted with at least in the region of the channel region ( 22 ) in the epitaxial layer ( 262 ) with higher doping compared to the basic doping. 18. The method according to claim 17, in which a further essentially the basic doping epitaxial layer ( 261 ) is applied to the semiconductor substrate ( 27 ), the further epitaxial layer ( 261 ) between the semiconductor substrate ( 27 ) and the epitaxial layer ( 262 ) the channel line region ( 225 ) contains, is arranged and the two epitaxial layers ( 261 , 262 ) are applied successively and one above the other to the semiconductor substrate ( 27 ).