DE10136716A1 - Manufacturing method for dynamic random-access memory element with formation of memory cell field and control and evalaution circuit in vertically overlapping surface regions - Google Patents

Abstract

The manufacturing method uses semiconductor technology for provision of at least one capacitor and transistor for a memory cell of a memory cell field (31), together with a control and evaluation circuit (21), positioned vertically above the memory cells of the memory cell field. The memory cell field and the control and evaluation circuit are incorporated in respective overlapping surface regions (2,3) which are at least partially coupled together. An Independent claim for a dynamic random-access memory element is also included.

Description

The invention relates to a DRAM memory device and a Method of manufacturing a DRAM memory device.

Modern electronic devices such as Televisions, phones, radios, and computers are generally out Solid state components built. As solid-state components they are therefore preferred in electronic devices used because they are very small and relatively cheap. Of other solid-state components are very reliable because they have no moving parts themselves, but theirs Functioning based on the principle of the charge carrier movement.

Solid-state components are, for example, transistors, Capacitors, resistors and other semiconductor devices. Typically, such components are on substrates manufactured and electrically connected to each other Memory cells, logic structures, timers and other components to form an integrated circuit. One guy for one Memory chip is a dynamic random access memory (DRAM), of the memory cells in which information can be saved temporarily. Because the information is short can be saved is a refresh of the Storage charging at certain intervals in a so-called refresh Cycle required. Despite this limitation, DRAMS are widespread because it has a low cost per Bit ratio and on the other hand have a high component density.

To further downsize DRAM memory devices, generally aspired to always have a DRAM cell array to produce a higher packing density. In EP 0 852 396 there is one DRAM cell arrangement described in order to increase the Packing density of a transistor over a memory cell Storage capacitor of the memory cell is arranged. active Areas of the memory cells are each one insulating structure surrounded, arranged in a substrate is. There is a recess in the substrate for each memory cell generated, in the lower area of a storage node Storage capacitor and a gate in the upper region Electrode of the transistor are arranged. An upper source / Drain area, a channel area and a lower source / drain The area of the transistor is one above the other in the substrate arranged.

In the known device, the one above the other Placing the transistor of the memory cell over the Memory capacitor of the memory cell only the DRAM Cell arrangement can be reduced. A disadvantage of the known DRAM memory devices is the horizontal one Arrangement of the control and evaluation of Memory cell necessary circuit. The space requirement of the circuit is almost equal to the memory cell. The Downsizing of the DRAM memory device is therefore considerable Set limits.

Furthermore, from US Pat. No. 6,201,302 B1 known that semiconductor devices in a semiconductor package are arranged such that the components are stacked on a Substrate to be glued on. The semiconductor components can thereby as integrated circuits or microprocessors or Chips are executed. Furthermore, the are stacked Semiconductor components each considered as independent, independently functioning units. The semiconductor devices are through contact wires with the Substrate connected. In addition, the semiconductor package a heat sink and one covering the components Protective cover, which is arranged on the top of the substrate. In addition, those components that are replaced by a The opening in the substrate protrude through a second protective cover the underside of the substrate is covered.

The known semiconductor package has a very complex Building on. Despite the stacking of the components, this shows Housing therefore has a relatively large structure and is for the Downsizing of DRAM memory devices unsuitable.

Furthermore, miniaturization of the DRAM is required Memory device in structure sizes below 100 µm always more special process techniques. So for the process steps Manufacture of DRAM memory cell array others Requirements as to the process steps for the production of the DRAM Peripherals used to control and evaluate the Serves cell field. Both with simultaneous processing of the DRAM cell array and the DRAM periphery as well a separate processing of these two DRAN areas the process costs add up and increase for both Process approaches in almost identical ways.

The object of the invention is a DRAM memory device and a method of manufacturing a DRAM memory device to create, with almost constant complexity the process steps a downsizing of the DRAM Storage device is reached.

This task is accomplished by a procedure that the Has steps according to claim 1, and a DRAM Memory component having the features of claim 9 has, solved.

A DRAM memory component has a memory cell array at least one memory cell. The memory cell points a transistor and a capacitance that is electrical are interconnected. Furthermore, the DRAM Memory component on a control and evaluation circuit, with which the memory cell is controlled and the contained therein Information is evaluated.

According to the invention is a first unit in or on which the Control and evaluation circuit is included, vertically above a second unit, in or on which the memory cell included is arranged. At least part of a total area of a bottom of the first unit is over a surface of an upper side of the second unit. The two superimposed surface areas are at least partially directly connected and the Memory cell has an electrical connection with the control and Evaluation circuit on.

This can ensure that the space required for the necessary for the functioning of the DRAM memory component interdependent units of the memory cell of the Memory cell array and the control and evaluation circuit can be reduced. As in known DRAM memory devices the memory cell array with the memory cells horizontally Control and evaluation circuit is arranged by the DRAM memory device according to the invention almost one Halving the area of the DRAM memory device can be achieved since the area required for the control and evaluation circuit is almost as large as the area for that Memory cell array with the memory cells. Furthermore, this can be achieved that the memory cell array is not a horizontal Interruption by the control and evaluation circuit has and therefore no filling structures, for example "Dummy trenchs" in trench technology, through which one better utilization of the wafer with the well-known DRAM Memory devices allows needed. Farther can be achieved in fixed assemblies Memory components can be installed, almost double Memory capacity compared to known DRAM Have memory devices.

Advantageous embodiments of the invention are in the Subclaims specified.

It can be provided that both the memory cell as well as the control and evaluation circuit each on one own unit to be processed and the two Units are then bonded. Bonding the two Units can be connected via a via or a pad be performed.

Furthermore, it can be provided that the memory cell on the first unit is processed. Independently of the control and evaluation circuit on the second unit partially processed. Then the two Units bonded or glued together and the second, partially processed unit is finished by processing in this Unit contact holes are etched through the electrical Contacts of the first unit.

It can be achieved that the overall processes as well the process steps for the DRAM memory cell, as well as for the Control and evaluation circuit of the DRAM memory component are independent of each other and no longer mutually influence. Furthermore, the bond pads for the Contact size is larger, as there is now more space for Available. In addition, the yield of DRAM This increases memory components in chip-by-chip bonding that both the DRAM memory cell array and the Control and evaluation circuit of the DRAM memory component can be tested.

Another advantage is that so-called "Fuses" on the location of the bond pads or can be produced via electrical fuses.

Furthermore, it can be achieved that different bonds or forms of tax and Evaluation circuit different memory sizes and memory types (for example EDO, SDRAM) can be realized.

Exemplary embodiments of the invention are described below the schematic drawings explained in more detail. Show it:

FIG. 1a top view of a schematic representation of a DRAM memory device according to the invention,

FIG. 1b shows a section through the DRAM memory device of FIG. 1a taken along the line AA ',

FIG. 2a is a schematic representation of a finished processed memory cell array having at least one memory cell,

Fig. 2b is a schematic representation of a memory cell according to Fig. 2a with deposited polysilicon layer,

Fig. 2c is a schematic representation of a memory cell with a deposited polysilicon layer of FIG. 2b, with a processed to the polysilicon layer control and evaluation circuit

Fig. 3a shows a sectional view of a partially completed prozessiertes DRAM memory device,

FIG. 3d shows a section through a completely processed DRAM memory component according to FIG. 3a.

A top view of a DRAM memory component 1 is shown in FIG. 1a. The DRAM memory component 1 has a first unit 2 which has the control and evaluation circuit 21 . Furthermore, the DRAM memory component 1 has a second unit 3 which has a memory cell matrix 31 with a plurality of memory cells. The DRAM memory cell matrix 31 , that is to say a memory cell arrangement with dynamic, random access, is currently used almost exclusively as a so-called single-transistor memory cell which comprises a transistor, for example a MOS transistor, and a capacitor. The information of a memory cell of the memory cell matrix 31 is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor so that when the transistor is driven by the control and evaluation circuit 21 via a word line, the charge of the capacitor can be read out via a bit line by the control and evaluation circuit 21 .

The first unit 2 is arranged on the second unit 3 such that the entire surface of the underside of the first unit 2 is arranged completely above the surface of the top of the second unit 3 . In the exemplary embodiment, the first unit 2 and the second unit 3 are arranged symmetrically to the axis of symmetry I. However, the first unit 2 can also be arranged anywhere on the surface of the second unit 2 .

In Fig. 1b is a sectional view of the DRAM memory device 1 along the line AA '(Fig. 1a) is shown. The second unit 2 with the control and evaluation circuit 21 is arranged completely with the entire area of the underside of the unit 2 on the surface of the second unit 3 , which has the memory cell array 31 with a plurality of memory cells. The control and evaluation circuit 21 is connected to the memory cell array 31 by bond pads 4 , 5 and 6 .

The control and evaluation circuit 21 and the memory cell array 31 shown in the two FIGS. 1a and 1b are produced independently of one another on two separate wafers. Due to the miniaturization of the DRAM memory component 1 , special process steps are necessary both for the manufacture of the control and evaluation circuit 21 and for the manufacture of the memory cell array 31 . By producing the memory cell array 31 independently of the control and evaluation circuit 21 , it can be prevented that process steps which are necessary for the production of the memory cell array 31 have a negative influence on the production of the control and evaluation circuit 21 and vice versa. Both the memory cell array 31 and the control and evaluation circuit 21 are finished processed on or in the unit 3 or on or in the unit 2 . The control and evaluation circuit 21 in unit 2 is then bonded to the memory cell array 31 in unit 3 . These method steps for producing the DRAM memory component 1 can be carried out for memory cells in the memory cell array 31 which have a trench structure, but also for memory cells in the memory cell array 31 which have a stacked structure.

If you consider a unit cell with the area 8 × F × F, where F is about 100 µm and corresponds to the minimum structure size that can be produced in the technology used, then you need, for example, an area of A = 2 × 10 for a 2 Mbit module ⁶ × 8 × 0.1 × 0.1 µm ² = 16 × 10 ⁴ µm ² . As is known from the prior art, bond pads can be implemented on a chip-by-chip basis in an area of 2 × 2 μm ² . Therefore, an area of about 16 µm ^{2 is} required for a bond pad with the corresponding space requirement. This means that 10,000 bond pads can be implemented on a 2 Mbit module. As is known, a 2 Mbit module can be implemented as a 4 k × 512 or as a 1 k × 1 k module. Therefore less than 5000 contacts are required to address this 2 Mbit module. During vertical positioning Thus, the control and evaluation circuit 21 and 31 a sufficient area available to the control and evaluation circuit 21 with the memory cell array 31 to be bonded in accordance with the memory cell array. The realization of the required number of bond pads and the required size of the bond pads is a necessary prerequisite for the vertical arrangement of the memory cell field 31 and the control and evaluation circuit 21 . The arrangement of the contacts or the bond pads can be designed depending on the arrangement of the control and evaluation circuit 21 on the memory cell array 31 .

In addition, contacts by means of which the DRAM memory component can be controlled by an external device can also be arranged and processed on the memory cell array 31 together with the bond pads for the control and evaluation circuit 21 . The process steps for producing the memory cell array 31 are carried out in such a way that the memory cell array 31 is processed up to a bit line not shown in FIGS . 1a and 1b and a word line not shown in FIGS . 1a and 1b. The bonds are then processed and implemented as via connections and / or pad connections.

Another embodiment of the DRAM memory device according to the invention is shown in FIGS. 2a and 2b. In the same way as in the first exemplary embodiment, the memory cell array 31 is completely processed by corresponding process steps and is contained in or on the unit 3 . An insulation layer (not shown) is then deposited on the finished processed unit 3 , onto which a polysilicon layer 7 is in turn deposited, with which the basis for logic processes is laid ( FIG. 2b). The control and evaluation circuit 21 , which is contained in or on the unit 2 , is then processed on the polysilicon layer 7 by corresponding process steps. The performance data for the control and evaluation circuit 21 and the logic processes carried out thereby are limited by grain boundaries of the doped polysilicon layer 7 . For example, by passing via connections through the polysilicon layer 7 and the insulation layer, an electrical connection between the unit 2 and the unit 3 can be established.

According to FIG. 2 b of the second exemplary embodiment, the surface of the unit 3 is of the same size as the surface of the underside of the unit 2 . However, provision can also be made for the unit 2 to be made smaller or larger by corresponding process steps.

In a third exemplary embodiment, the memory cell array 31 ( FIG. 3a) is processed on or into the unit 3 by means of corresponding process steps. A non-finished processed unit 8 , which has a control and evaluation circuit 81 , is bonded to the surface of the finished processed unit 3 . The unit 8 is connected to the unit 3 by a bond pad 9 and a bond pad 10 . Furthermore, as in the first exemplary embodiment, the entire surface of the underside of the unit 8 lies on the surface of the unit 3 , and the two surfaces are connected directly to one another. Contact holes 11 , 12 and 13 ( FIG. 3b) are then etched into the unit 8 . Electrical contacts (not shown) of the unit 3 are guided through these contact holes 11 , 12 and 13 . In the exemplary embodiment, three contact holes were chosen, but any other number of contact holes can also be etched into the unit 8 . It is also possible to glue the unit 8 onto the unit 3 .

In all exemplary embodiments, the first unit 2 , 8 can be a substrate or a chip or an integrated circuit or a microprocessor. Likewise, in all exemplary embodiments, the second unit 3 can be a substrate or a chip or an integrated circuit or a microprocessor.

In the case of the DRAM memory component according to the invention and the method for producing this DRAM memory component, the first unit 2 , 8 , which has the control and evaluation circuit 21 , 81 , is arranged vertically above the second unit 3 , which has the memory cell array 31 with the memory cell and the entire area of the underside of the first unit 2 , 8 is arranged completely above the at least the same area of the upper side of the second unit 3 , and the two areas are at least partially directly connected to one another so that the area required for the DRAM Memory device can be almost halved compared to known DRAM memory devices.

Among the process steps of semiconductor technology, which for Manufacture of a DRAM memory device is carried out, for example, etching, cutting off Understood layers or lithography with masks. A possible process sequence for the production of a DRAM Memory component is, for example, from D. Widmann et al. "Technology of highly integrated circuits", pp. 335-348, 2. Edition, Springer Verlag, 1996, known and hereby fully included in the disclosure content.

Furthermore, in the cited prior art of D. Widmann et al. in section 8.4.2 both Embodiment of a memory cell designed in a stacked structure of the DRAM memory device and one in a trench structure executed memory cell of the DRAM memory component shown and hereby fully in the disclosure content added.

Claims (15)

1. A method for producing a DRAM memory component ( 1 ), in which at least one capacitance and one transistor of a memory cell of a memory cell array ( 31 ) and a control and evaluation circuit ( 21 ) are generated by process steps of semiconductor technology, characterized in that the control and evaluation circuit ( 21 ) is arranged vertically above the memory cell of the memory cell array ( 31 ) and a first unit ( 2 ) into or onto which the control and evaluation circuit ( 21 ) is processed, at least with a partial area of an entire area of an underside thereof the first unit ( 2 ) is arranged above a surface of an upper side of a second unit ( 3 ), into or onto which the memory cell of the memory cell array ( 31 ) is processed, and the two superimposed surface areas are at least partially connected directly to one another. 2. The method according to claim 1, characterized in that both the memory cell of the memory cell array ( 31 ) and the control and evaluation circuit ( 21 ) are each independently processed to a separate unit ( 3 , 2 ) and the two units ( 3 , 2 ) are then bonded. 3. The method according to claim 2, characterized, that bonding through a via or pad connection is carried out. 4. The method according to claim 1, characterized in that the memory cell of the memory cell array ( 31 ) is finished processed on a first unit ( 3 ), the control and evaluation circuit ( 81 ) independently of the first unit ( 3 ) on a second unit ( 8 ) is partially processed, the two units ( 3 , 8 ) are bonded or glued together and the second, partially processed unit ( 8 ) is finished by etching contact holes in the unit ( 8 ) through the electrical contacts of the first unit ( 3 ) be performed. 5. The method according to claim 1, characterized in that a polysilicon layer is deposited on the first unit ( 3 ), into which the memory cell of the memory cell array ( 31 ) is processed, on which the second unit ( 2 ), which the control and evaluation circuit ( 21 ) is processed. 6. The method according to any one of the preceding claims, characterized, that the memory cell on or in a substrate unit or a chip unit or an IC unit or a Microprocessor unit is processed or integrated. 7. The method according to any one of the preceding claims, characterized in that the control and evaluation circuit ( 21 , 81 ) is processed or integrated on or in a substrate unit or a chip unit or an IC unit or a microprocessor unit. 8. The method according to any one of the preceding claims, characterized, that the memory cell is in a trench structure or Stacked structure is manufactured. 9. DRAM memory component ( 1 ), which has a transistor and a capacitance in a memory cell of a memory cell array ( 31 ) and a control and evaluation circuit ( 21 , 81 ), characterized in that a first unit ( 2 , 8 ) which controls - And evaluation circuit ( 21 , 81 ), arranged vertically above a second unit ( 3 ), which has the memory cell of the memory cell array ( 31 ), at least with a partial area of an entire surface of an underside of the first unit ( 2 , 8 ) A surface of an upper side of the second unit ( 3 ) is arranged, the two superimposed surface areas are at least partially directly connected to one another and the memory cell is electrically connected to the control and evaluation circuit ( 21 , 81 ). 10. DRAM memory component ( 1 ) according to claim 9, characterized in that the first unit ( 2 , 8 ) is a substrate or a chip or an integrated circuit (IC) or a microprocessor. 11. DRAM memory component ( 1 ) according to claim 9, characterized in that the second unit ( 3 ) is a substrate or a chip or an integrated circuit (IC) or a microprocessor. 12. DRAM memory component ( 1 ) according to one of claims 9 to 11, characterized in that the first unit ( 2 , 8 ) and the second unit are bonded or glued together. 13. DRAM memory component ( 1 ) according to claim 12, characterized in that the bonds are designed as bond pads ( 4 , 5 , 6 , 9 , 10 ) or as via connections. 14. DRAM memory component ( 1 ) according to one of claims 9 to 11, characterized in that a polysilicon layer is arranged between the first unit ( 2 ) and the second unit ( 3 ). 15. DRAM memory component ( 1 ) according to one of claims 9 to 14, characterized in that the memory cell of the memory cell array ( 31 ) is designed in a trench or a stacked structure.