DE10136548B4 - Method for testing internal control signals in semiconductor devices - Google Patents

Abstract

Method for testing at least one internal control line in a semiconductor device with regard to sufficient reserve of a control signal over critical operating states in which this control signal is delayed on the control line, wherein in a first unit (E1) an internal control signal is generated in an operating mode to a second unit (E2) via a first signal path (SP1), in which:
(A) in a test mode, the internal control signal is passed to the second unit depending on a test control signal (T) via a second signal path (SP2) delayed from the first signal path, wherein the internal control signal is additionally delayed in a defined manner so as to test the semiconductor device to simulate the delaying effect of a critical operating condition on the internal control signal, and
(B) the semiconductor device is checked with the delayed internal control signal.

Description

The The invention relates to a method for testing at least one internal one Control line in a semiconductor device with respect to a sufficient time against Operating conditions, which delay a control signal on the control line.

A clock signal distribution circuit having delay circuits for synchronizing a plurality of clock signals is disclosed in USP US 5,204,559 described. A controllable delay circuit for the adjustment of clock and test signals is in the DE 195 34 735 A1 described. A switching device for selecting a delayed or undelayed control signal by a multiplexer or a logic gate is approximately in Tietze, U .; Schenk, Ch .: Semiconductor Circuit Technology, 8th revised. Edition, Springer-Verlag Berlin 1986 described.

The Timing behavior of an internal generated in a semiconductor device Control signal varies on the one hand as a result of deviations in the Production of semiconductor device to semiconductor device, for others, it is preceded by within the same semiconductor device Control sequences or internal operating conditions influenced.

If unfavorable add up the production-related and operational delays such that it is due to the excessively delayed internal control signal leads to malfunction in the semiconductor device.

critical operating conditions or control sequences can not be easily predicted. Therefore, one requires as possible safe examination of a Such semiconductor device testing with many, always different Control sequences if possible all conceivable internal operating states. Such a kind of exam is complicated and expensive.

A known possibility the testing effort without To reduce loss of test severity, is in while The examination to vary internal voltages to the semiconductor device below tightened unfavorable Conditions to check. However, the behavior of components of the semiconductor device, in particular of switching devices located in it very much generally affected, which is not application-relevant failure mechanisms can set in motion and subsequently leads to yield losses.

It is therefore an object of the invention to provide a method in the internal control signal to sufficient reserves in the time behavior against critical operating conditions or control sequences checked without provoking non-application-relevant failures become.

The solving this task Method is specified in claim 1. Advantageous developments The invention will become apparent from the dependent claims.

By the inventive method is the internal control signal during The examination the semiconductor device in addition defined delayed and at random selected internal operating conditions checked.

With this additional Signal delay is the delaying Effect of a critical operating condition or a critical one Control sequence simulated to the internal control signal.

is in a semiconductor device, the manufacturing delay of the internal control signal so big that in certain internal operating states or control sequences, which in turn leads to a delay lead the internal control signal, Malfunction triggers, then malfunctions occur at uncritical operating conditions or after uncritical control sequences, if the internal control signal while The examination additionally delayed becomes.

To is the control line on which the internal control signal is transmitted is, from an output of a unit, the internal control signal to generate on the input of a controllable delay device guided and its output to an input of the at least one unit, which is controlled by the internal control signal. Additionally points the delay device a control input to which a test control signal is applied.

In the controllable delay device is the control line branches into two signal paths, the signal being in the first signal path undelayed, in second by a delay device delayed is guided in each case a switching device. Dependent on from the test control signal is in a test mode, the switching device in the delayed Signal path, otherwise the switching device in undelayed signal path closed and accordingly the delayed or the undelayed internal Control signal switched to the output of the delay device.

The test control signal can be used as input to the Be guided semiconductor device to the outside and be controlled during the test directly by a tester. In semiconductor devices which already include a test unit, the test unit will preferably generate the test control signal for the delay device.

In the embodiment described above the internal control signal always at the input of the delay device also in the non-test mode (in the following operating mode). The delay device takes power even in operating mode.

In a particular embodiment the delay device switches the test control signal through an upstream one Logic switching device only corresponding to the operating mode Signal path to, the other from.

When delay means to carry out the method according to the invention is preferably a chain of an even number provided in series inverter.

In a further preferred embodiment the method according to the invention can be the number of in the delay device effective inverter and thus the delay over one Test mode registers of the internal test unit are selected. This will become the a way to Analysis of causes of failure created, on the other hand could delay means with regard to an ongoing Further development of the semiconductor device for several product cycles in the core unchanged stay.

Semiconductor devices, the for the method described are particularly suitable are Semiconductor memory devices or those, the semiconductor memory devices include, in particular DRAMs or semiconductor devices, the DRAMs contain.

The usual with the latter Signals for write control, for redundancy query, as well as the COLUMN SELECT signals are internal control signals from DRAMs with critical runtime paths and preferably as during The examination to be delayed Provide signals.

following The invention will be explained in more detail with reference to a drawing, in the single figure Scheme of implementation the method according to the invention used device in a particularly preferred embodiment is shown.

1 shows a delay device V with an input E, an output A and a control input T. The input E is connected to an output of a unit E1 in the semiconductor device which is capable of generating an internal control signal. The output A is connected to the input of at least one unit E2 in the semiconductor device which is controlled by the internal control signal. At the control input T is a test control signal, which can be generated by an internal test unit TE in the semiconductor device.

Within the delay device is the test control signal at one of the two inputs one AND gate AND2 at the beginning of a delayed signal path SP2 and inverted at one of the two inputs of a second AND gate AND1 at the beginning of an undelayed Signal path SP1 on. At the respective second inputs of the two AND gates AND1 and AND2 are the internal control signal.

in the Test mode switches the test control signal to logic 1 level the gate AND2 the present at the input E internal control signal to the input of the delay device VE and blocked over the gate AND1 the undelayed Signal path SP1.

in the Operating mode blocks the test control signal at logic 0 level the delayed one Signal path SP2 and turns on the undelayed signal path SP1.

in the delayed Signal path is the output of the gate AND2 with the input of a delay means VE connected. To simplify the illustration, the delay device shown as consisting of four inverters connected in series.

Of the Output of the delay device VE is connected to the switching input of a switching device SE2. Im undelayed Signal path SP1 is the output of gate AND1 directly to the switching input a second switching device SE1 out.

The switching outputs the two switching devices SE1 and SE2 are connected to the output A of the delay device connected. The test control signal is at the control input of the switching device SE2 and inverted at the control input of the switching device SE1.

in the Test mode opens the test control signal the switching device SE1 and separates it the undelayed internal control signal from the output A, closes the switching device SE2 and turns off the delayed internal control signal to the output A by.

in the Operating mode closes the test control signal the switching device SE1 and thus switches the instantaneous Control signal to the output A through, opens the switching device SE2 and separates the output of the delay device VE from the output A of the delay device V.

E1

first unit

E2

second unit

TE

Test controller

V

delay means

T

control input the delay device

e

entrance the delay device

A

output the delay device

AND1

AND gate

AND2

AND gate

VE

delay means

SE1

switching device

SE2

switching device

SP1

signal path 1

SP2

signal path 2

Claims (7)

Method for checking at least one internal Control line in a semiconductor device with respect to a sufficient reserve of a control signal in the time behavior compared to critical Operating conditions, in which this control signal is delayed on the control line, wherein an internal control signal is generated in a first unit (E1), in an operating mode to a second unit (E2) via a first signal path (SP1), in which: (a) in one Test mode, the internal control signal depending on a test control signal (T) over one opposite delayed the first signal path second signal path (SP2) is passed to the second unit, wherein the internal control signal in addition defined delayed is going to be that way during The examination the semiconductor device, the retarding effect of a critical Operating state to simulate the internal control signal, and (B) the semiconductor device with the delayed internal control signal checked becomes. Method according to claim 1, characterized in that in that the test control signal is from one in the semiconductor device located test unit (TE) is generated. Method according to one of claims 1 or 2, characterized that the control signal on the second signal path (SP2) by a delay means (VE) delayed which consists of at least one pair of inverters. Method according to one of claims 1 to 3, characterized that the control signal on the second signal path (SP2) by a delay means (VE) delayed which consists of at least two levels and at least one further test control signal the number of times for the delay of the internal control lines effective levels selectable is. Method according to one of claims 1 to 4, characterized in that the semiconductor devices include semiconductor memory devices or semiconductor memory devices. Method according to one of claims 1 to 5, characterized the semiconductor devices are DRAMs or contain DRAMs. Method according to Claim 6, characterized that the internal control signals COLUMN_SELECT signals, write control signals and Redundancy query signals on DRAMs or eDRAMs.