DE10135573A1 - Transistor arrangement as sense amplifier has at least one second double row of paired transistors of first or second type; rows are offset and gaps of at least one row are left - Google Patents

Abstract

The arrangement has first and second active regions with double rows (7,8) of paired transistors of first and second types respectively and gate electrodes (4) and source/drain contacts (6) connected together and to bit lines (BL) and complementary bit lines in a manner suitable for a sense amplifier. At least one second double row of transistors of the first or second type is provided. The rows are offset and gaps of at least one row are left.

Description

The present invention relates to a transistor arrangement of a sense amplifier, which will be used especially in future DRAM Technologies can be used.

In semiconductor memories, especially in DRAMs (Dynamic Ran dom access memories) are the memory cells in the memory cell lenfeld connected to bit lines to turn one off or on to transfer the data value to be imported. By activating ei A word line becomes an access transistor of the memory cell switched on and the ge in a storage capacitor stored charge state applied to the bit line. Such a stored as a logical zero or one in a memory cell The bit is read out via a bit line, the one complementary bit line is assigned. The bit line and the complementary bit lines are initially on the same bottom held potential. The potential changes when reading out the bit line to which the memory cell is connected. The potential of the complementary bit line remains for the time being unchanged. As a result of the readout process there is therefore a the lines on something higher, the other on something lower potential, and this imbalance can each logical memory values to be read are clearly assigned.

The weak signals are ver through a sense amplifier strengthens. The sense amplifier compares the potential of the bits line and the associated complementary bit line and increases the difference until full signal level is reached become. The difference between the bit line (TRUE) and the complementary bit line (COMPLEMENT) is with what polarity the information in the memory cell ge is written. With the TRUE bit line, the logical One as high potential in the connected SpeI cell saved; in the COMPLEMENT bit line, the  logical one interpreted by a zero potential. At the Reading process, both bit lines are connected to sense amplifiers closed to the capacities and disruptions at both A the node of the sense amplifier is the same or similar to hal th.

In the accompanying Fig. 1 is an arrangement of several superimposed signal amplifier SAP with the bit lines BL, BL 'and the complementary bit lines BL ^- , BL' ^- Darge, which are led from both sides to the signal amplifier. The channels of the sense amplifier have first been brought into a balanced state and amplify the different complementary signals of a bit line and its complementary bit line after a read operation.

The control of a single SAP circuit via the word lines WL1, WL2, WL3, WL4 etc. is shown in FIG. 2 Darge. The signal amplifier, which is shown in the diagram in FIG. 3, usually comprises on both sides a number of switches between the complementary bit lines in order to short-circuit the potentials with one another and with a reference potential V _ref and thus keep them constant can (Equalize circuits). By means of multiplexers MUX provided on both sides, the actual sense amplifier SA arranged between them is connected on one side to the bit lines. Such a sense amplifier, which is inserted in an arrangement of memory cells and bit lines, is referred to as a sense amplifier. In principle, this is known.

In FIG. 4, a basic circuit diagram of the eigentli chen sense amplifier is shown. Between a respective bit line BL and the associated complementary bit line BL ^- two inverters I1, I2 are connected, which are supplied with the supply voltages NCS, PCS.

Fig. 5 shows how these inverters are realized with field effect transistors. A first n-channel MOSFET M2 and a first p-channel MOSFET M3 form the first inverter I1; a second n-channel MOSFET M1 and a second p-channel MOSFET M4 form the second inverter I2. At the point in time when the memory cell is read out, the potential of the two associated bit lines is the same, for example a predetermined equalization _potential V _BLeq pretty much midway between the supply voltages, for example a positive internal supply voltage V _int and ground GND, and is also driven weakly by the compensation _potential V _BLeq . When reading out the connected memory cell, the potential on one of the two complementary bit lines is changed in one or the other direction by a few mV. In order to amplify the signal levels, the NCS voltage shown in FIGS . 4 and 5 is driven strongly at GND and the PCS voltage is strongly driven at V _int .

In FIG. 6, a scheme is shown as belonging to the sense Amplifiern transistors are arranged in a practical realization of a semiconductor memory in principle. There is a first active region 1 with the transistors of a first type and a second active region 2 with the transistors of a complementary second type. The transistors of successive pairs of bit line and complementary bit line are arranged in double rows of transistors assigned to one another in pairs, these pairs each belonging to a sense amplifier; There is a double row for each of the two transistor types. The transistors belonging to the same sense amplifier are arranged along the bit lines.

In Fig. 6 gate electrodes 3 , 4 of these transistors are shown with the rounded rectangles, the z. B. are formed from structured polysilicon. There are also source / drain contacts 5 , 6 of the transistors. The gate electrodes 3 , 4 and the source / drain contacts 5 , 6 of the same transistor are each connected to a bit line and the associated complementary bit line. The respective other source or drain connection of the transistors is connected to the connection of the supply voltages provided, preferably via NCS connection contacts or PCS connection contacts on the top and interconnected doped regions within the semiconductor chip. This is known per se and is not shown in detail in FIG. 6. The arrangement shown in the diagram in FIG. 6 gives a sensor amplifier corresponding to the transistor circuit shown in FIG. 5 due to the connection of the transistors for each pair of bit line and complementary bit line.

The arrangement of FIG. 6 corresponds to a currently verwend cash layout of a sense amplifier in 140 nm technology. Because of the conditions existing during the manufacture and operation of the semiconductor memory, this arrangement according to FIG. 6 cannot be easily transferred to the dimensions of a 100 nm technology.

The object of the present invention is a transistor arrangement as a sense amplifier for narrow bit line grids to admit.

This task is performed with the transistor arrangement with the Merk paint the claim 1 solved. Refinements arise from the dependent claims.

In the transistor arrangement according to the invention, the n- Channel transistors and the p-channel transistors as above wrote in double rows of pairs assigned to each other Transistors arranged, these pairs each to one Belong to sense amplifier. The transistors of a sense Amplifiers are along the associated bit lines and com complementary bit lines arranged. Unlike that known arrangement are at least two double rows each  Transistor types exist. The transistors each have a dop row are the bit lines and the associated complemen tary bit lines in one according to a consecutive number ration of successive bit lines predetermined Ab omitted at least one bit line each assigns. If there are N double rows of each transistor type are, for example, in the nth double row the transistors of the sense amplifiers of the nth, (n + N) th, (n + 2N) -th etc. pair of bit line and complementary bit line available.

In a preferred embodiment, in which two dop p-series of n-channel transistors and p-channel transistors are present, those transi are in the double rows interfere successively arranged across the bit lines net that to the sense amplifiers each in the sequence of bits lines of the second pair of bit line and complementary Bit line belong. In the double rows of transistors are so always the transistors of every second sense amplifier arranged and the transistors of the remaining sense amplifiers omitted. The other transistors are located in another double row that is essentially parallel is arranged to the first double row.

In a preferred embodiment, a first one is active Area and a second active area with the transistors complementary types together for the Double rows of transistors of the same type are provided. If There are two double rows for each type, the Tran sistors of a double row each in a continuous Number even consecutive bit lines or odd-numbered bit lines and the associated comple assigned to mental bit lines. The double rows are like this arranged to each other that the transistors of a Dop row in the active area concerned with respect to the Alignment of the bit lines laterally against the transistors the other double row or double rows are offset. The  Transistors are so ver with the relevant bit lines switches that respective sense amplifiers are formed.

The following is a more detailed description of examples of the transistor arrangement according to the invention with reference to FIGS . 7 to 9.

Figs. 1 to 6 are according to the above explanatory notes are schematic representations of the prior art.

FIG. 7 shows a schematic representation corresponding to FIG. 6 for the arrangement according to the invention.

Fig. 8 shows a layout of an example of an OF INVENTION to the invention transistor arrangement in plan view.

FIG. 9 shows a diagram corresponding to FIG. 7 for an alternative embodiment.

In the schematic representation of FIG. 7 it can be seen that the transistors of the first active region, for. B. the n-channel MOSFETs are arranged in two double rows 7 and also the transistors of the second active region, for. B. the complementary p-channel MOSFETs, are arranged in two double rows 8 . The gate electrodes 3 , 4 each one of these double rows in the two active areas are preferably formed as self-contained conductor tracks, in particular ring-shaped or loop-shaped, and represented in FIG. 7 by rounded rectangles. In addition to these gate electrodes, the gate electrodes 9 , 11 belonging to the second double row of the two active regions are added. The top-side source / drain contacts 5 , 6 are here also preferably brought up in the area enclosed by the gate electrodes 3 , 4 on the semiconductor material. The source / drain contacts 10 , 12 of the further double rows are preferably also applied to the semiconductor material in the area enclosed by the relevant gate electrodes 9 , 11 .

As this structured gate electrodes 3, 4, 9, 11 can be seen directly from the arrangement, the transistors of the two respective double rows with respect to the direction of the bit lines BL and complementary bit lines BL ^- displaced against each other since Lich arranged. In this way, the transistors which follow one another in a double row are successively assigned to the next-but-one bit lines and complementary bit lines. This ensures that the number of successive structural elements, that is to say contacts, electrodes, conductor tracks and connection areas in the dimensions required for the electrical connections, is halved compared to conventional arrangements in the direction running transverse to the bit lines. Therefore, the bit lines can be arranged closer together.

In the example shown in FIG. 7, the gate electrodes are arranged uniformly and symmetrically. This is ei ne preferred because easy to manufacture design; however, an asymmetrical or irregular arrangement of the transistors is also suitable. The transistors of the two respective double rows need not be exactly offset by half a length. The spacing of the transistors can also vary. For example, the distances can alternately increase and decrease.

In FIG. 8, a layout for the active region of the n-channel MOSFET is shown as an example of a possible implementation in plan view. The bit lines BL and complementary bit lines BL ^- run here via gate electrodes 4 , which are designed as rectangular loops made of polysilicon. The reference numerals are drawn in corresponding to the components according to FIG. 7. The gate electrodes of the left double row of transistors are provided with the reference number 11 . The bit lines and the complementary bit lines are via source / drain contacts 6 , 12 , which are attached here directly below the relevant bit lines and are drawn as hidden contours with dashed boxes, with the respective connections provided for the source and drain of the transistors connected. The electrically conductive connections between the bit lines or complementary bit lines and the gate electrodes structured from polysilicon also take place here via contacts 14 , 15 , which are each arranged on a widened connection region of the gate electrode.

For the supply of the supply voltage NCS to the other transistor connections, lines are arranged between the gate electrodes, which are connected via contacts 13 to the respective connections of the transistors. The essentially parallel bit lines run between the two double rows so that the supply lines of the supply voltage can be arranged between the bit lines in both double rows. This arrangement of the feed lines has the essential advantage that it simultaneously effects effective shielding of the neighboring sense amplifiers from one another. Therefore, each line is preferably, as indicated in Fig. 8, provided with egg ner row of contacts 13 , as this improves said shielding.

The arrangement according to FIG. 8 has the advantage over the conventional arrangement of the transistors of the sense amplifier that it can be implemented in 110 nm technology. The number of lines of the supply voltage is significantly reduced. A preferred symmetrical structure can be maintained. Due to the special arrangement of the contacts 14 of the gate electrodes of the left double rows and the contacts 15 of the gate electrodes of the right double row, there is only a point symmetry about points in the embodiment of FIG. 8, each between the double rows and between one in consecutive numbering of successive bit lines, even bit line and the closest odd complementary bit line. However, it is also possible to select the arrangement such that it has point symmetry about a point that lies between the double rows and between a bit line and a closest complementary bit line that is assigned to an adjacent bit line.

The at least partially symmetrical arrangement of the gate Electrodes, the connections and the conductor tracks is not necessary. In principle, the bit lines can also be on egg ne connected in such a way that no symmetry can be seen becomes. The arrangement of the n-channel transistors and the p-channel Transistors can be designed differently. The doubles series of transistors of a type that the in the order are assigned to second sense amplifiers not to be located in the same active area. It can so there must also be a sequence of double rows starting from alternating transistors of one or the other type ent hold. The orders of the transistor types of the double rows can therefore instead of the order described n-n-p-p of left to right also p-p-n-n, n-p-n-p, p-n-p-n, p-n-n-p or be n-p-p-n.

An alternative arrangement of the transistors is shown in the diagram of FIG. 9 as a further exemplary embodiment. It is also indicated there that the mutual displacement of the transistors of the different double rows need not be the same or symmetrical. In this example, the double rows are arranged from left to right in the order npnp of the transistor types. The n-channel MOSFETs are arranged in the double rows 7 and the p-channel MOSFETs in the double rows 8 , which are interleaved with one another. The pairs of bit line and complementary bit line are each connected to the transistors of two adjacent double rows. Instead, the sense amplifiers can also be formed by the transistors of the two inner double rows or the transistors of the two outer double rows.

From the examples described, the idea according to the invention becomes clear that the transistors of the sense amplifiers of adjacent pairs of bit line and complementary bit line of the same type do not all follow one another in a row, but in at least two rows which are run next to one another and in which the transistors of the sense Amplifiers are offset from one another at least to such an extent that the bit lines are aligned in a sufficiently straight line and, at the same time, can be contacted with the transistor connections in the manner envisaged. In particular, it should be taken into account that the contacts 14 , 15 of the gate electrodes 4 , 11 are attached to somewhat enlarged connection areas, the positions of which likewise restrict the routing of the bit lines. In addition, the bit lines and associated complementary bit lines are to be connected to the source / drain contacts of the transistors in the area enclosed by the gate electrodes. The arrangement according to the invention makes it possible, despite the narrow position of the bit lines, to conduct the bit lines in a central region of the loop-shaped gate electrodes, which mark the position of the transistors, via the transistors of the sense amplifier.

LIST OF REFERENCE NUMBERS

1

first active area

2

second active area

3

Gate electrode

4

Gate electrode

5

Source / drain contact

6

Source / drain contact

7

double row

8th

double row

9

Gate electrode

10

Source / drain contact

11

Gate electrode

12

Source / drain contact

13

Contact

14

Contact of the gate electrode

15

Contact of the gate electrode
BL bit line
BL ^-

complementary bit line
NCS supply voltage
PCS supply voltage
WL1 word line

Claims (9)

1. transistor arrangement as a sense amplifier in which
a first active region ( 1 ) with a double row of a pair of transistors of a first type and associated with one another
a second active region ( 2 ) with a double row of transistors assigned to one another in pairs of a complementary second type and
There are gate electrodes ( 4 ) and source / drain contacts ( 6 ) which are connected to one another and to bit lines (BL) and complementary bit lines (BL ^- ) in a manner provided for a sense amplifier,
characterized in that
at least one second double row ( 7 , 8 ) of transistors of the first type assigned to one another or of transistors of the second type assigned to one another is provided,
the transistors are each assigned to a double row of the bit lines and the associated complementary bit lines at a predetermined spacing according to a consecutive numbering of successive bit lines, omitting at least one bit line and
the transistors of each one double row are laterally offset with respect to the alignment of the bit lines against the transistors of the at least second double row. 2. Transistor arrangement according to claim 1, wherein
A second double row ( 7 , 8 ) each consisting of transistors of the first type arranged in pairs or of transistors of the second type assigned in pairs is provided,
the transistors of a double row are each assigned to the ge numbered or odd numbered bit lines in a sequential numbering of successive bit lines and the associated complementary bit lines and
the transistors of one double row are laterally offset from the transistors of the other double row with respect to the alignment of the bit lines. 3. Transistor arrangement according to claim 1 or 2, wherein
each transistor is provided with a gate electrode ( 4 ) formed as a self-contained conductor path and
the gate electrodes and the source / drain contacts ( 6 ) of the transistors assigned to one another in pairs are connected crosswise to a respective bit line and the complementary bit line. 4. A transistor arrangement according to claim 3, wherein the source / drain contacts ( 6 ) are each arranged in a region enclosed by the gate electrode ( 4 ). 5. Transistor arrangement according to one of claims 1 to 4, in which between the gate electrodes ( 4 ), which belong to paired transistors of a double row, and the subsequent gate electrodes, which belong to the next pair of transistors of this double row belong, in each case a feed line (NCS) is arranged, which is connected in an electrically conductive manner to at least one contact ( 13 ) to a region forming a further connection of the transistors. 6. Transistor arrangement according to one of claims 1 to 5, at the the double rows of transis assigned to each other in pairs gates of the first type or in pairs assigned transistors of the second type in each case Most or second active area of the transistors of the concerned fenden type are arranged. 7. Transistor arrangement according to one of claims 1 to 5, in which
for the transistors of the first type and / or the transistors of the second type provided for the formation of sense amplifiers, at least two separate active areas are present and
the active areas are interleaved with one another such that at least one double row of transistors of a first type is arranged between double rows of transistors of a second type. 8. Transistor arrangement according to one of claims 1 to 7, in which
In each active area, the arrangement of the transistors, the gate electrodes, the source / drain contacts and the bit lines and complementary bit lines that cross the area
has a translation symmetry in the direction of the double rows formed by the transistors and
each has a point symmetry around a point which is between the double rows and between a bit line and a closest complementary bit line which is assigned to a neighboring bit line. 9. Transistor arrangement according to one of claims 1 to 8, in which
In each active area, the arrangement of the transistors, the gate electrodes, the source / drain contacts and the bit lines and complementary bit lines that cross the area
a translation symmetry in the direction of the double rows formed by the transistors and
each has a point lying between the double rows and between an even-numbered bit line in a consecutive numbering of successive bit lines and the closest odd-numbered complementary bit line.