DE10132641A1 - Semiconductor arrangement comprises a substrate with an electrically active region, an insulating region, an electrically conducting region, an electrically conducting supply lead, an auxiliary strip conductor and a highly doped region - Google Patents

Abstract

Semiconductor arrangement comprises a substrate (101) with an electrically active region; an insulating region (105) made from a dielectric arranged on the electrically active region; an electrically conducting region arranged on the insulating region; an electrically conducting supply lead connected to the electrically conducting region; an auxiliary strip conductor arranged next to the supply lead; and a highly doped region with doping atoms of a first conductivity connected to the strip conductor. An Independent claim is also included for the production of a semiconductor arrangement. Preferably the device also comprises a source region (102) of a field effect element; and a drain region (103) of a field effect region. An active region is arranged between the source and drain regions and forms a channel region (104). The electrically conducting region forms a gate region of a field effect element.

Description

The invention relates to a semiconductor device, a Semiconductor test structure and a method for manufacturing a semiconductor device.

Such a semiconductor test structure is known from [1].

In the manufacture of highly integrated circuits, the for example a large number of MOS transistors (metal Oxide semiconductor transistors) are in the frame of the manufacturing process often plasma process steps provided d. H. Process steps in which plasma is in the frame the processing or manufacture of the device or in Frame of the wiring is used. That in one Plasma process step used plasma can be an electrical conductive supply line (connecting line) to a gate Area of a field effect transistor and the gate area charge electrically. The electrical charge that affects the Supply lines and accumulated in the gate area overflow the isolation area under the gate area from a dielectric and can damage it or even destroy if the plasma process during the Manufacturing not appropriately optimized has been. Leakage current paths in particular can be generated in this way which are in the fully processed transistor Injuries and to a reduced lifespan or can lead to a complete failure.

This damage to the insulation area, that is Degradation and / or the unintentional introduction of Leakage current paths in the dielectric is also considered Plasma process-related damage from charging (plasma Induced Damage (PID) and is, for example is shown in [2], depending on the ratio (Antenna Ratio, AR) of those brought into contact with the plasma Surface of the leads to the active dielectric surface of the field effect transistor, that is to the surface of the Dielectric on which the gate area is applied.

The ratio of the areas of the supply lines, which with the Plasma can be brought into contact with the active Dielectric area changes during the Manufacturing process ongoing, d. H. is the antenna ratio not constant (see [2]).

The maximum lifespan and reliability of the chips and the field effect transistors located in it due to various levels of damage caused by plasma processes be significantly affected during manufacture, the damage can be considerably higher than it was planned in the layout of the chip.

To the reliability of the used in a chip Components, in particular the field effect transistors (or also capacitors), for example with regard to degradation of "hot" load carriers (hot carriers) or more mobile To be able to estimate ions (mobile ions), it is desirable the influence of the damage caused by the plasma process if possible not to measure with.

For this reason, the influence of the Plasma process-related damage caused by charging using the Protective structure, that is, by means of the semiconductor Protective structure, minimized or excluded as far as possible become. It is also to be as quantitative as possible Statement about the degree of damage caused by the plasma process get by charging, of significant importance, corresponding semiconductor PID test structures with an exact defined ratio of the in contact with the plasma brought area of the electrically conductive lead to the Design the gate area to the active dielectric area.

In the semiconductor test structures described in [1] and [2] it is intended in opposite to the transistor process levels later regarding the manufacturing process and thus higher process levels to provide protective diodes to the charges induced on the supply lines due to the plasma to reduce, that is, to let it flow off. An alternative is the use of so-called cable bridges described to supply lines and thus the charging too minimize.

Under a process level is within the scope of this description for example a wiring level in a semiconductor To understand manufacturing process, generally a level in the Semiconductor device, which during at least one Process step is manufactured or processed.

The disadvantage of using a protective diode is in particular that only one type of electrical Charge carriers can flow away at all. Furthermore is a Disadvantage that the protective diode's performance (Performance) of the respective device, d. H. of the device, influenced and the protective diode only from the first Metallization level is connectable.

Thus, the invention is based on the problem, the influence damage caused by the plasma process due to charging to reduce an electronic component.

The problem is compounded by the semiconductor device Semiconductor test structure and by the method for Manufacture of a semiconductor device with the features solved according to the independent claims.

A semiconductor device, for example a chip a wafer, has a substrate. In or on the substrate an electrically active area is arranged. The electric active area can be an electrode of a capacitor, preferably an MIS capacitor (Metal Insulator Semiconductor capacitor), or one for example Channel area of a field effect transistor.

There is an electric on the electrically active area insulating isolation area made of a dielectric arranged. On the insulation area is a electrically conductive area, for example another Electrode or a gate region of a field effect transistor, applied.

The electrically conductive area is electrically conductive lead electrically coupled, that is these connected.

Furthermore, one is to the electrically conductive feed line Adjacent electrically conductive auxiliary conductor track provided with at least one with doping atoms a first conductivity type of highly doped region of the Substrate or the tub, for example in the substrate, is electrically coupled.

In this connection it should be noted that the invention not on an MIS capacitor or on one Field effect transistor is limited, but for each Stack structure is suitable in the case of an electrical active area, that means for example also one electrically conductive area, an isolation area, preferably from a dielectric, and on again electrically conductive area, which with an electrically conductive supply line is coupled, applicable, for example on a MIM capacitor (Metal Insulator Metal Capacitor), a polysilicon Polysilicon capacitor, a memory cell, a thyristor or other power semiconductor components with the corresponding structure.

Under an auxiliary trace is one in the sense of Functionality of the semiconductor device in the context of circuit components provided in the semiconductor device functionless conductor track to understand which only to serves during a plasma process, especially during a plasma etching process, accumulations of Charge carriers on the electrically conductive feed line and the electrically conductive area on the insulation area in the highly doped area, which Trace is connected via the auxiliary trace to derive in this way during a Damage to the dielectric occurring in the plasma etching process to reduce, mostly even to minimize.

The invention can clearly be seen in that during a plasma etching process, generally during a Plasma process, on an electrically conductive lead accumulating charge carriers via an electrical conductive auxiliary conductor track, for example in one or several highly endowed areas, are derived and only on At the end of the plasma etching step, the electrically conductive Process line and the auxiliary conductor track be electrically decoupled.

In the semiconductor device, a source region of a Field effect element can be provided, as well as a drain area of a field effect element. In this case it is the active one Area between the source area and the drain area arranged and forms a channel area of the field effect Element. The electrically conductive area forms in this Fall the gate area of a field effect element, for example a field effect transistor.

The electrically active area can be a first electrode of a Form capacitor and the electrically conductive area a second electrode of the capacitor.

According to one embodiment of the invention, at least one highly doped with doping atom of a second conductivity type second area is provided to the electrically conductive Auxiliary trace is connected.

The highly doped regions in the substrate are preferred arranged and serve to derive charge carriers in the Base material, that is, for example, in the substrate. One of the two highly doped areas or both high doped areas are preferably in a tub in the Substrate housed. According to a further embodiment the invention provides that two highly doped Areas in the tub and one or two more high doped areas outside the well in the substrate to be arranged and also electrically with the auxiliary conductor track to couple.

The electrically conductive area and the electrically Conductive supply lines can be in different Processing levels of the semiconductor device arranged be, preferably the electrically conductive feed line is arranged above the electrically conductive region.

The term "above" is used in this context understand that one is above another layer layer in the course of the manufacturing process of a Semiconductor device in one versus the manufacture of the another layer, subsequent process step is formed.

The electrically conductive supply line and the electrically In this case, conductive auxiliary conductor tracks are in the same Processing level of the semiconductor device arranged.

In this context it should be noted that during the Manufacture of the semiconductor device before each Plasma etching step on the electrically conductive lead and the auxiliary trace is applied, these two Structures are still electrically coupled to each other as they only after structuring a metal layer be formed.

Because of the plasma etching step, they become electrical conductive supply line and the electrically conductive auxiliary Conductor preferably only towards the end of Electrically decoupled from the plasma etching step means only towards the end of the actual plasma etching process will really emerge at the electrically conductive supply line accumulating charge carriers to the gate area, i.e. generally to the electrical area conductive area, and can do that Dielectric damage the performance of the chip (Chip performance) reduce or measurement results in the frame of permissibility tests on transistors, for example with regard to the degradation of "hot" charge carriers or falsify mobile ions.

During most of the process time of the However, the plasma etching process step is electrical conductive supply line and the electrically conductive auxiliary Conductor electrically coupled to each other so that the on the two structures accumulating charge carriers over the areas electrically doped with doping atoms can drain off.

According to one embodiment of the invention, the is electrical conductive region formed from highly doped polysilicon.

• - Aluminium, und/oder
• - Kupfer, und/oder
• - Gold, und/oder
• - eine Legierung zumindest eines der oben genannten Metalle.

The electrically conductive feed line and / or the auxiliary conductor track can contain metal or a metal alloy or can be formed from these. The electrically conductive feed line and / or the auxiliary conductor track preferably contains or is formed from at least one of the following metals:

• - aluminum, and / or
• - copper, and / or
• - gold, and / or
• an alloy of at least one of the metals mentioned above.

• - Polysilizium,
• - Silizid.

The electrically conductive feed line and / or the auxiliary conductor track can generally contain or be formed from any suitable electrically conductive material, for example

• - polysilicon,
• - silicide.

• - Monoelementares Halbleitermaterial der IV. chemischen Hauptgruppe, vorzugsweise Silizium,
• - Verbindungen mehrerer monoelementarer unterschiedlicher Halbleitermaterialien der IV. chemischen Hauptgruppe, vorzugsweise Silizium-Germanium (SiGe),
• - III-V-Halbleitermaterial, vorzugsweise Gallium-Arsenid, Indiumphosphit
• - II-VI-Halbleitermaterial.

The substrate can contain or be formed from at least one of the following semiconductor materials:

• Mono-elementary semiconductor material of the IV chemical main group, preferably silicon,
• Connections of several mono-elemental different semiconductor materials of the IV chemical main group, preferably silicon germanium (SiGe),
• III-V semiconductor material, preferably gallium arsenide, indium phosphite
• - II-VI semiconductor material.

Especially in the event that the electrically conductive Area and the electrically conductive supply line different process levels, that means on different levels within the semiconductor device are arranged, these are in particular via at least one Contact hole, which with electrically conductive material is filled, coupled.

• - Wolfram, und/oder
• - Aluminium, und/oder
• - Kupfer, und/oder
• - Gold, und/oder
• - eine Legierung zumindest eines der oben genannten Metalle.

According to an embodiment of the invention, this electrically conductive coupling contains at least one of the following metals:

• - tungsten, and / or
• - aluminum, and / or
• - copper, and / or
• - gold, and / or
• an alloy of at least one of the metals mentioned above.

According to one embodiment, the auxiliary conductor track is Invention at a distance from the electrically conductive Supply line arranged adjacent, which is selected depends of a process characteristic of a process step in Framework of manufacturing and / or processing of auxiliary Conductor and / or the electrically conductive feed line. On this way is a further optimization of the invention under Consideration of the respective process characteristics allows.

The distance is preferably selected depending on one Process characteristics of a plasma etching process for manufacturing and / or editing the auxiliary conductor track and / or the electrically conductive supply line.

It is advantageous in the event that the plasma etching process larger exposed ones that come into contact with the plasma Surfaces etch the distance faster than smaller surfaces according to the highest resolution of the overall process choose, for example with today's process technologies in Range of 0.1 µm, 0.3 µm, etc.

However, is the plasma etching process set up such that small areas are etched faster than large areas, it is advantageous, the distance between the auxiliary conductor and the electrically conductive feed line as large as possible so that it is guaranteed that the electrical coupling between the electrically conductive Supply line and the auxiliary conductor track only towards the end of Plasma etching process is electrically separated. In this Context should be used when choosing the spacing in the layout available free space on the chip be taken into account.

The choice of distance is reflected in the scope of the Manufacturing process in the appropriate arrangement and Structuring the photoresist on a respective one Metal layer again, from which the electrically conductive Supply line and the auxiliary conductor track are formed.

In accordance with the invention, the one shown in [2] as Disadvantage of a plasma etching process shown different speed of metal removal used during a plasma etching process to make one as possible good discharge of the charge carriers during a Plasma etching process in the respective highly doped area to achieve and thus damage the dielectric during a plasma etching process.

According to an alternative embodiment of the invention, it is provided one in the substrate or on the substrate arrange another electrically active area and on the another electrically active area another Isolation area made of a dielectric, which is equal to the Dielectric of the insulation area or another Dielectric can be. On the further isolation area is another according to this embodiment of the invention arranged electrically conductive area, which with a further electrically conductive supply line electrically is coupled. The surface of the further Isolation area on which the further electrical conductive area is the same size or larger than the surface of the isolation area on which the electrically conductive area is arranged. Depending on available space can be the ratio of Surface of the further isolation area up to one Factor of 1000. Alternatively or additionally, the Thickness of the further isolation area, i. H. the thickness of the further dielectric can be chosen smaller than the thickness of the Isolation area, d. H. the thickness of the dielectric which should be protected.

According to this embodiment of the invention, it is clear Semiconductor element of the same structure, but with one increased surface area ratio further Isolation area with that of the surface of the Isolation area and / or with a thinner dielectric provided by means of the plasma etching process the beginning of which is the electrically conductive supply line, the auxiliary Conductor track and the electrically conductive additional supply line are coupled together, further to the further Isolation area are derived. In the further Dielectric becomes active due to the increased Dielectric surface and / or due to the thinner Dielectric the damage caused by the charge carriers of the dielectric in the insulation area is greatly reduced.

The invention is particularly suitable for testing a Semiconductor arrangement, in other words, the semiconductor Device particularly advantageously a semiconductor Test structure for testing a semiconductor device.

However, it should be noted that the invention is for everyone any electrical circuit is suitable and there can be used.

In a method of making a Semiconductor device is in a substrate or on a substrate an electrically active area is arranged. On the electric active area becomes an isolation area from a Dielectric applied, on which in turn an electrical conductive area is applied. An electric one conductive supply line, which to the electrically conductive Area is connected is formed. Furthermore, one becomes the electrically conductive feed line arranged adjacent electrically conductive auxiliary conductor track formed and at least one with the doping atom of a first Conductivity type highly doped area, which to the electrically conductive auxiliary conductor is connected.

According to the invention, any number of electrically conductive layers and thus supply lines arranged one above the other and with the respective electrical conductive area, for example the gate area, be electrically coupled.

Correspondingly, any number of parts can also be used in a circuit sub-area with many used electrically conductive areas with the respective high be doped region, but in each case at least one auxiliary conductor track, which after Plasma etching process is inoperative, is provided and during the plasma etching process, especially at the beginning of the Plasma etching process with the respective electrical conductive leads to the electrically conductive Areas is coupled.

Electrically conductive areas can also be electrical in this way stay connected during the plasma process, by between existing electrically conductive Supply lines further, preferably compared to the auxiliary Small additional auxiliary conductor tracks inserted become.

The invention is therefore very well suited for structures or Circuits not only in the area of testing, i.e. H. in one Test chip, but even in a product chip.

According to the invention, the non-functional auxiliary conductor track can be in Analogy to construction technology viewed as a lost formwork be, that is, it becomes an element according to the invention formed or provided, which is only during the Manufacturing process has a function, but after Completion of the semiconductor device no longer functions having.

Embodiments of the invention are in the figures are shown and explained in more detail below.

The same elements with identical elements are shown in the figures Provide reference numerals.

Show it

Fig. 1 is a sketch of a semiconductor device according to a first embodiment of the invention;

FIG. 2a to 2d sketch of the semiconductor device according to the first embodiment of the invention at different times during a plasma etching process, by means of which a metal layer is patterned and the electrically conductive lead is formed to an electrically conductive area;

Fig. 3 is a sketch of a semiconductor device according to a second embodiment of the invention; and

Fig. 4 is a sketch of a section of a semiconductor device according to a third embodiment of the invention.

Fig. 1 shows a semiconductor device 100 according to a first embodiment of the invention.

The semiconductor device 100 has a silicon substrate 101 p-doped with boron atoms (10 ¹⁵ cm ^-3 -10 ¹⁷ cm ^-3 ), one with boron atoms (10 ¹⁶ cm ^-3 -10 ¹⁸ cm ^-3 ) p-doped well 115 , one with arsenic or phosphorus atoms (10 ¹⁹ cm ^-3 -10 ²¹ cm ^-3 ) n ⁺ -doped source region 102 and one with arsenic or phosphorus atoms (10 ¹⁹ cm ^{- 3} -10 ²¹ cm ^-3 ) n ⁺ -doped drain region 103 are introduced. The source region 102 and the drain region 103 are introduced into the p-doped well 115 .

A channel region 104 is formed between the source region 102 and the drain region 103 , on which a dielectric is applied as insulation material in the insulation region 105 .

According to this exemplary embodiment, the dielectric is Invention silicon dioxide selected.

• - Oxynitrid (NO),
• - eine ONO-Struktur (Oxid-Nitrid-Oxid-Struktur),
• - Siliziumnitrid (Si₃N₄),
• - high-k-Dielektrika,
• - eine Stapelstruktur aus unterschiedlichen, übereinander angeordneten high-k-Dielektrika.

Alternatively, the following materials are preferably used as the dielectric:

• - oxynitride (NO),
• an ONO structure (oxide-nitride-oxide structure),
• Silicon nitride (Si ₃ N ₄ ),
• - high-k dielectrics,
• - A stack structure of different high-k dielectrics arranged one above the other.

A gate region 106 is arranged on the insulation region 105 , part of the gate region extending over the dielectric 105 . The gate region is made of polysilicon, doped with 10 ²⁰ cm ^-3 -10 ²¹ cm ^-3 phosphorus doping atoms.

Via a contact hole 107 filled with tungsten, the gate region 106 is electrically coupled to an electrically conductive feed line 108 formed from aluminum, which is arranged in a processing plane arranged above the gate region 106 .

Adjacent to the electrically conductive feed line 108 , in the same processing level as the electrically conductive feed line, an auxiliary conductor track 109 , which according to this exemplary embodiment is also made of aluminum, is not functional in the actual circuit-technical function of the circuit.

The auxiliary conductor track 109 is coupled via a first auxiliary contact hole 110 made of tungsten to an electrically highly doped region 111 arranged in the substrate 101 with p ⁺ doped with boron atoms (10 ¹⁹ cm ^-3 -10 ²¹ cm ^-3 ) , Electrical charges (negative or positive), that is to say electrons that accumulate on the electrically conductive feed line, the gate region and the auxiliary conductor track during the plasma etching process, can thus be dissipated into the highly doped region 111 via the first auxiliary contact hole 110 .

The optional or alternative contact configurations shown in FIG. 1 with the second highly doped region 112 and the second auxiliary contact hole 113 , and / or with the third highly doped region 116 and the third auxiliary contact hole 117 and / or with the fourth Highly doped region 118 and the fourth auxiliary contact hole 119 , which can also have a predetermined circuit function within the framework of the electrical circuit to be actually formed, can be used with better availability. The protective effect of these alternative contact configurations is influenced by the fact that, depending on the charge polarity, a pn diode is located in the direction of flow or in the reverse direction in the discharge current path.

By providing a highly doped region of the same conductivity type as the substrate, it is possible according to the invention to discharge negative as well as positive charges, which can be caused in the context of the plasma etching process, into the substrate 101 and thus into the carrier material, causing damage to the dielectric can be excluded during a plasma etching process, as long as the electrically conductive feed line 108 is electrically coupled to the auxiliary conductor track 109 .

Furthermore, FIG. 1 shows an optional, ^(-3 -10 ²¹ cm ^-3 10 ¹⁹ cm) of p ⁺ doped with boron atoms in the n-well 114 disposed third electrically highly doped region 116 which via a third auxiliary Contact hole 117 made of tungsten is electrically coupled to the auxiliary conductor track 109 . Furthermore, FIG. 1 shows an optional fourth electrically highly doped region, which is doped with arsenic or phosphorus atoms (10 ¹⁹ cm ^-3 -10 ²¹ cm ^-3 ) ^{and is} arranged outside of the n-well 114 in the substrate 101 118 is provided, which is electrically coupled to the auxiliary conductor track 109 via a fourth auxiliary contact hole 119 made of tungsten.

FIG. 2a illustrate to Fig. 2d, as in the present invention reduces the load of the dielectric during a plasma etching process. In FIGS. 2a through Fig. 2d the trays 114, 115 and the third heavily doped region 116, the third auxiliary contact hole 117, the fourth highly doped region 118 and the fourth auxiliary contact hole are not shown 119 for reasons of clarity, which are optional anyway.

First of all, the structure shown in FIG .

An electrically insulating layer 201 , into which the contact hole 107 is introduced, which is filled with tungsten, is arranged above the gate region 106 .

A metal layer 202 made of aluminum is applied to the electrically insulating layer 201 , for example by means of sputtering or vapor deposition or a deposition process from the gas phase, from which metal layer 202 by means of plasma etching, as will be explained in more detail below, the electrically conductive feed line and the auxiliary Trace are formed.

A photoresist layer 203 structured by means of phototechnology is applied to the metal layer 202 , which is structured in such a way that those areas of the metal layer 202 are exposed which are to be removed by means of a plasma etching process which is subsequently used.

FIG. 2b shows the structure from FIG. 2a a short time after the start of the plasma etching process.

According to this exemplary embodiment, it is assumed that, due to the process characteristics of the plasma etching process, larger exposed areas 204 , 205 which are exposed to the process gas are etched away faster than smaller areas 206 , 207 .

As can be seen in FIG. 2a, the structured photoresist layer is structured in such a way that the regions which cover the electrically conductive feed line 108 to be formed and the auxiliary conductor path 109 are arranged adjacent to one another at a distance F which corresponds to the maximum process resolution (minimum Feature size) of the process used to manufacture the semiconductor device corresponds, according to this exemplary embodiment, to 0.25 μm.

FIG. 2b shows the semiconductor device during the plasma etch.

FIG. 2b shows that, as described in [2], larger exposed portions 204, 205 are etched away from the metal more rapidly from the process gas as a smaller surface areas 206, 207.

In FIG. 2b, this means that after a certain process duration, during which the exposed areas 204 , 205 , 206 , 207 are brought into contact with the plasma, the first exposed areas 204 , 205 with a relatively large surface area are etched back further than that exposed areas 206 , 207 that offer a smaller surface area of the metal layer 202 .

FIG. 2 c finally shows the semiconductor device 100 at a point in time at which the metal layer in the larger, second exposed areas 204 , 205 has been completely etched away.

As can be seen from FIG. 2c, there is still a metallic, that is to say electrically conductive coupling between the electrically conductive feed line 108 to be formed and the auxiliary conductor path 109 at this point in time, so that the charge carriers accumulating on the in the gate region 106 , the electrically conductive feed line 108 and the auxiliary conductor track 109 can be derived via the first auxiliary contact hole 110 and the second auxiliary contact hole 112 to the highly doped regions 111 and 113 in the substrate 101 .

FIG. 2d shows the fully processed semiconductor device 100 after completion of the plasma etching step, at which the part of the metal layer 202 which was free of the photoresist has been removed.

Thus, in this state, only the electrically conductive feed line 108 and the auxiliary conductor track 109 are still present, which are now electrically decoupled from one another.

Fig. 3 shows a semiconductor device 300 according to a second embodiment of the invention.

A first field effect transistor 302 is inserted in a silicon substrate 301 p-doped with boron atoms (10 ¹⁵ cm ^-3 -10 ¹⁷ cm ^-3 ), one with boron atoms (10 ¹⁶ cm ^-3 -10 ¹⁸ cm ^-3 ) p-doped well 313 with a with arsenic or phosphorus atoms (10 ¹⁹ cm ^-3 -10 ²¹ cm ^-3) n ⁺ doped source region 303 and a likewise with arsenic or phosphorus atoms (10 ¹⁹ cm ^-3 -10 ²¹ cm ^-3 ) n ⁺ -doped drain region 304 . A channel region 305 is arranged between the source region 303 and the drain region 304 . The source region 303 and the drain region 304 are introduced into the p-doped well 313 .

Above the channel region 305 , the gate dielectric made of silicon dioxide 306 is applied, and on top of it the gate region 307 made of polysilicon highly doped with phosphorus atoms (10 ²⁰ cm ^-3 -10 ²¹ cm ^-3 ), to which is connected an electrically conductive Lead 308 made of polysilicon is attached.

The auxiliary conductor track 309 is located in the same process level as the electrically conductive feed line 308 , which in turn is arranged next to the electrically conductive feed line 308 at a minimal distance, in other words at a distance that corresponds to the maximum process resolution.

According to the second exemplary embodiment of the invention, the auxiliary conductor track 309 and the electrically conductive feed line 308 are likewise made of highly doped polysilicon.

Furthermore, according to the semiconductor device 300 according to the second exemplary embodiment, an auxiliary dielectric structure 310 is provided, which has a further insulation region 311 made of a dielectric, according to this exemplary embodiment made of silicon dioxide, and on which a further gate region 312 , generally another electrically conductive area 312 is applied.

The auxiliary dielectric structure 310 can be a structure that is in itself functionless in the context of the actual electrical circuit, which structure is only used to hold the charge carriers and, with regard to the active dielectric area, can be a correspondingly enlarged or provided with a thinner or equally thick dielectric.

According to this exemplary embodiment, the surface of the further insulation region 311 , on which the further gate region 311 is applied, is larger by a factor of up to 1000 than the surface of the insulation region 306 , on which the gate region 307 of the first field effect transistor 302 is applied.

During is done according to the second embodiment according to as shown in FIGS. 2a through Fig. 2d and not explained in detail for this reason, the plasma etching process, is, at the beginning of the plasma etching an electrically conductive coupling between the gate region 307 of the field effect transistor Auxiliary conductor track 309 and the gate region 311 of the auxiliary dielectric structure 310 are present. At this point in time, charge carriers accumulating on the electrically conductive feed line are mainly discharged by means of the auxiliary dielectric structure 310 .

According to the first exemplary embodiment, the electrical coupling is only destroyed according to the second exemplary embodiment towards the end of the plasma etching step, and only then can charge carriers no longer be diverted into the auxiliary dielectric structure 310 via the auxiliary conductor track 309 .

FIG. 4 shows a top view of part of a semiconductor device 400 according to a third exemplary embodiment of the invention.

The semiconductor device 400 has a large number of transistors arranged next to one another, each having a gate region and an associated gate lead 401 made of highly doped polysilicon or a metal or a metal alloy. The source / drain regions 402 of the transistors are arranged between two gate regions or the associated gate feed lines 401 .

An auxiliary conductor track 403 is arranged at a minimum distance (minimum feature size) F from a gate feed line 401, which is coupled in the same way as the semiconductor device 100 according to the first exemplary embodiment to highly doped regions via which electrical charge carriers can flow off , Alternatively, the auxiliary conductor track 403 corresponding to the semiconductor device 300 according to the second exemplary embodiment can be arranged over a further dielectric.

Furthermore, there are additional auxiliary conductor tracks 404 between two respective two gate regions or the associated gate feed lines 401 . At the beginning of the plasma process step, the auxiliary auxiliary conductor tracks 404 are electrically coupled to the two immediately adjacent gate feed lines 401 , so that a common electrically conductive layer is formed by the gate feed lines 401 , the auxiliary auxiliary conductor tracks 404 and the auxiliary conductor track 403 is formed.

The structuring of the common electrically conductive layer before the start of the plasma process step takes place in such a way that the additional auxiliary conductor tracks 404 are each arranged at a minimum distance F from a gate lead 401 or the auxiliary conductor track 403 after the plasma process step has ended.

This exemplary embodiment clearly means that no continuous auxiliary conductor track has to be provided in the semiconductor device, but in some cases already provided conductor tracks in the electrical circuit as additional auxiliary conductor tracks 404 for diverting the electrical charge to the auxiliary conductor track 403 and above in the highly doped areas or in the further dielectric.

Below are some alternatives to the above shown embodiments shown.

It should be noted that the structure of the auxiliary conductor track is not necessarily designed such that the auxiliary conductor track 109 , 309 runs parallel to the electrically conductive feed line. The shape of the auxiliary conductor track 109 , 309 is also fundamentally arbitrary, preferably at least part of the auxiliary conductor track 109 , 309 being arranged at a minimal distance from the electrically conductive feed line.

For the connecting lines, i.e. the supply lines of the Gate areas and the associated components, the Plasma process-related damage due to electrical Charge can also be reduced according to the invention.

In this context, it should be noted that according to the invention a plurality, in principle any one Number of electrically conductive leads, each are at least partially arranged over a dielectric, be electrically coupled with only one auxiliary conductor track and which auxiliary traces then the entire occurring electrical charge carriers in the in the Most of the gate areas in the highly doped areas or derived into an auxiliary dielectric structure can.

By means of a semiconductor device according to one of the above Exemplary embodiments described, in the event that they are used in a test structure, a very accurate one Determination of the degradation based on the damage to the respective transistors due to plasma process Antennas are guaranteed and there can also be damage on the dielectrics of the transistors, which are avoided Transistors for measuring transistor parameters be used.

Furthermore, when using a distance between Auxiliary conductor tracks arranged on both sides around a feed line of F (Minimum Feature Size) the imaging accuracy of the Semiconductor structure itself can be improved.

It should also be noted that when using a auxiliary conductor track according to the invention a direct contact of the areas prone to charge possible without decoupling diode and then the polarity of the damaging charge carriers damage caused by charging due to the plasma process is irrelevant, which means that both electrons and in contrast, the charge of positive ions can also be dissipated on the use of protective diodes according to the state of the Technology.

Furthermore, according to the invention, further, non-functional filling structures can be provided in the respective metallization levels or in a polysilicon level, that is to say any non-functional conductor track structures that do not have an effect on the auxiliary conductor track 109 , 309 as areas that are charged by the plasma.

Furthermore, according to the invention, a conductor track bridge as shown in FIG is described in [2]. By such additional interconnect bridge can be charged by the Plasma can be reduced even further.

In summary, the invention can be seen clearly in this be that in a test structure or even in that Product layout, generally in a semiconductor device parallel, generally adjacent auxiliary conductor tracks to at least one gate area or its electrical area conductive lead to the top electrode with minimal Distance is provided on all supply levels.

All metallization levels from which conductor tracks are formed are connected to the substrate. Interconnect layers, that do not allow a substrate connection, with electrodes arranged above the gate of the same Semiconductor devices connected, which are thinner or the same contain thick dielectrics and a multiple of the active ones Dielectric surface of the semiconductor component to be protected have.

Furthermore, it can be provided that a trench between the to be protected structure and the highly endowed areas in to provide the substrate by means of which the highly doped Areas of the structure to be protected, for example a field effect transistor or a capacitor, electrical are better insulated. The trench preferably has one Depth at least the depth of the highly doped Areas in the substrate or depth of the to be protected Has structure in the substrate, but also arbitrary can protrude deeper into the substrate. The trench can go with any electrically insulating material, for example silicon dioxide as a dielectric material, be filled.

The following publications are cited in this document:
[1] US 6 028 324
[2] P. Simon, J.-M. Luschies, W. Maly, Antenna Ratio Definition for VLSI Circuits, Proceedings of International Symposium on Plasma Process-Induced Damage, pp. 16-20, 1999 List of reference symbols 100 semiconductor device
101 substrate
102 Source area
103 drain area
104 channel area
105 Isolation area
106 gate area
107 contact hole
108 supply line
109 auxiliary conductor track
110 First auxiliary contact hole
111 First highly endowed area
112 Second auxiliary contact hole
113 Second highly endowed area
114 n tub
115 p-tub
116 Third highly endowed area
117 Third auxiliary contact hole
118 Fourth highly endowed area
119 Fourth auxiliary contact hole
201 insulation layer
202 metal layer
203 photoresist layer
204 Large exposed area
205 Large exposed area
206 Small exposed area
207 Small exposed area
300 semiconductor device
301 substrate
302 field effect transistor
303 Source area
304 drain area
305 channel area
306 isolation area
307 gate area
308 Electrically conductive supply line
309 auxiliary conductor track
310 auxiliary structure
311 dielectric
312 Another gate area
313 p-tub

Claims (22)

1. Semiconductor device
with a substrate,
with an electrically active region arranged in the substrate or on the substrate,
with an insulation area made of a dielectric arranged on the electrically active area,
with an electrically conductive area arranged on the insulation area,
with an electrically conductive feed line that is connected to the electrically conductive area,
with an electrically conductive auxiliary conductor track arranged adjacent to the electrically conductive feed line, and
with at least one region highly doped with doping atoms of a first conductivity type, which is connected to the electrically conductive auxiliary conductor track. 2. The semiconductor device according to claim 1,
with a source area of a field effect element,
with a drain area of a field effect element,
wherein the active region is arranged between the source region and the drain region and forms a channel region of a field effect element, and
wherein the electrically conductive region forms a gate region of a field effect element. 3. The semiconductor device according to claim 1,
in which the electrically active region forms a first electrode of a capacitor, and
in which the electrically conductive area forms a second electrode of the capacitor. 4. Semiconductor device according to one of claims 1 to 3,
with at least one second region highly doped with doping atoms of a second conductivity type, which is connected to the electrically conductive auxiliary conductor track. 5. Semiconductor device according to one of claims 1 to 4,
in which the electrically conductive area and the electrically conductive feed line are arranged in different processing levels of the semiconductor device,
in which the electrically conductive feed line and the electrically conductive auxiliary conductor track are arranged in the same processing level of the semiconductor device. 6. Semiconductor device according to one of claims 1 to 4,
in which the electrically conductive region and the electrically conductive feed line are arranged in different processing levels of the semiconductor device, and
in which the electrically conductive region contains highly doped polysilicon. 7. Semiconductor device according to one of claims 1 to 6,
in which the electrically conductive supply line and / or the auxiliary conductor track contains one of the following materials:
polysilicon,
Silicide. 8. Semiconductor device according to one of claims 1 to 6,
in which the electrically conductive feed line and / or the auxiliary conductor track contains metal or a metal alloy. 9. The semiconductor device according to claim 8,
in which the electrically conductive feed line and / or the auxiliary conductor track contains at least one of the following metals:
Aluminum, and / or
Copper, and / or
Gold, and / or
an alloy of at least one of the metals mentioned above. 10. The semiconductor device according to one of claims 1 to 9,
in which the substrate contains at least one of the following semiconductor materials:
direct semiconductor material of the IV chemical main group,
a connection of several mono-elemental different semiconductor materials of the IV chemical main group,
III-V semiconductor material,
II-VI semiconductor material. 11. The semiconductor device according to claim 10,
in which the substrate contains silicon germanium as a compound of several mono-elementary different semiconductor materials of the IV. main chemical group. 12. The semiconductor device according to claim 10,
in which the substrate contains silicon germanium as a direct semiconductor material. 13. Semiconductor device according to one of claims 1 to 12,
in which an electrically conductive coupling between the electrically conductive region and the electrically conductive feed line and / or an electrically conductive coupling between the auxiliary conductor track and the region heavily doped with doping atoms of a first conductivity type contains metal. 14. The semiconductor device according to claim 13,
in which an electrically conductive coupling between the electrically conductive region and the electrically conductive feed line and / or an electrically conductive coupling between the auxiliary conductor track and the region heavily doped with doping atoms of a first conductivity type contains at least one of the following metals:
Tungsten, and / or
Aluminum, and / or
Copper, and / or
Gold, and / or
an alloy of at least one of the metals mentioned above. 15. The semiconductor device according to one of claims 1 to 14,
in which the auxiliary conductor track is arranged adjacent to one another at a distance from the electrically conductive feed line, which is selected as a function of a process characteristic of a process step in the course of producing and / or processing the auxiliary conductor track and / or the electrically conductive feed line. 16. The semiconductor device according to claim 15,
in which the auxiliary conductor track is arranged adjacent to one another at a distance from the electrically conductive feed line, which distance is selected depending on a process characteristic of a plasma etching process for producing and / or processing the auxiliary conductor track and / or the electrically conductive feed line. 17. The semiconductor device according to one of claims 1 to 16,
with a further electrically active region arranged in the substrate or on the substrate,
with a further insulation area made of a dielectric arranged on the further electrically active area,
with a further electrically conductive area arranged on the further insulation area,
with a further electrically conductive feed line, which is connected to the further electrically conductive region. 18. The semiconductor device according to claim 17,
in which the surface of the further insulation region on which the further electrically conductive region is arranged is the same size or larger than the surface of the insulation region on which the electrically conductive region is arranged. 19. The semiconductor device according to claim 17 or 18,
in which the further insulation area has a smaller or the same thickness as the insulation area. 20. Semiconductor test structure for testing a semiconductor Arrangement with at least one semiconductor device one of claims 1 to 19. 21. Semiconductor protective structure for an integrated circuit with at least one semiconductor device according to one of the Claims 1 to 19. 22. A method of manufacturing a semiconductor device,
in which an electrically active region is arranged in a substrate or on a substrate,
in which an insulation area made of a dielectric is applied to the electrically active area,
in which an electrically conductive area is applied to the insulation area,
in which an electrically conductive feed line, which is connected to the electrically conductive region, is formed,
in which an electrically conductive auxiliary conductor track arranged adjacent to the electrically conductive feed line is formed, and
in which at least one region which is highly doped with doping atoms of a first conductivity type and which is connected to the electrically conductive auxiliary conductor track is formed.