DE10131309A1 - Determining/controlling transition time of electrical signal on line involves detecting time to receive signal from transmitter reflected to receiver at one end of line with other end unterminated - Google Patents

Abstract

The method involves connecting a transmitter (4) and a receiver (5) to one end of the line (3) whose other end is not terminated. The transmitter starts a signal (DQ) and the receiver detects the time to receive the reflected signal. The detected time is halved to determine the transition time. The transmitter is a driver of an input/output channel in an integrated circuit.

Description

The invention relates to a method for determining and / or Control the runtime of an electrical signal on we at least one line according to the type of the main claim. With the increasing switching speeds in today Electronics often encounter the problem that the signal run times on the connecting lines between two units or modules have a significant influence on the function can exercise a device. For example, the clock times of a computer are getting higher and faster capabilities that are common with radio waves. Should be there Data or control signals, for example within the computer over parallel lines, like a parallel bus, from an integrated circuit (IC) to a second integrier th circuit, it is important that the signals time regardless of line properties right at the receiver of the second integrated circuit to meet. Only then is it guaranteed that the second integrated circuit the received data or commands can process properly.

In practice, this problem has been solved so far that the same lengths have been provided for all lines the. However, this is often not possible if the data come from different sources and the same Destination must be transferred. Can also be different Properties of the sending driver stages undesirable Cause runtime delays. Continue to effect under different operating temperatures of the driver stages that un Different signal delays can occur. The Ab equation of line lengths thus represents in many cases is an inadequate solution.  

The problem of maturities naturally also occurs within the integrated circuit between the individual modules. It is all the more important to note here because of the narrow lei Capacitive and inductive effects undesirable Can cause delays.

The method according to the invention for determining and / or Control the runtime of a signal on at least one Management with the characteristic features of the main claim has the advantage that the signal propagation times are not can only be recorded repeatedly. Rather, they can can also be controlled so that, for example, with a Parallel bus all data simultaneously at the destination address to meet. This has the further advantage that it is reliable speed of data transmission improved and unwanted waiting times through preset signal delays be avoided.

Through the measures listed in the dependent claims are advantageous further developments and improvements in Given the main method specified. As special it is considered advantageous that the transmitter is a driver an input / output channel (I / O channel) an integrated Circuit is. The individual integrated circuits have usually already a variety of I / O channels with Transmitters (driver stages) and receivers (receiver) equipped are. These modules can therefore also be advantageous for Acquisition and / or control of the signal transit times with be used.

A particularly simple and advantageous solution for the he The recording of the signal transit times is seen in a counter, preferably by a switch-on signal from the transmitter is started immediately with the transmission of the signal. The tough The clock is usually provided by a clock generator controls and sums up the impulses until it goes through a corresponding stop signal is stopped.  

It is also favorable that the counter is increased by the Amplitude of the reflected signal is stopped. Since the Line not terminated at its second end, i. H. Not is completed with a wave resistance, it will be with reflected about twice the amplitude. This increased Amplitude is therefore a reliable indicator for the reflec tated signal that is clearly recognized and for the counting stop of the counter can be used.

The evaluation of the amplitude of the reflected signal is advantageously carried out using a reference chip voltage that is simply given to an appropriate comparator becomes. Reaches the amplitude of the reflected signal preset value of the reference voltage, then the Comparator the counter. The counting result can then be read out or can in the signal runtime on the line can be converted.

Control the runtime of the signal on the line is most easily done by a delay element. at for example, the counter can ver for a certain period of time hesitates to start, depending on which line conditions prevail. In this way it succeeds for the parallel data transmission on several lines the individual to coordinate the run times of the signals.

It is also considered to be particularly advantageous that the barrel times are coordinated so that the signals arrive at the recipient (s) at the same time. Thereby more reliable signal processing is guaranteed.

For example, since the connecting lines between two Modules, preferably between two integrated circuits subject to diverse influences is an individual Control of signal transit times is particularly cheap.  

The coordination of the signal transit times appears in particular cheap with a parallel bus, because it makes a fast and delay-free signal transmission can take place.

It is also considered an advantage that the registration of the Signal transit times, for example, continuously during the Operation of the integrated circuit takes place. This will a quick automatic adjustment of the signal transit times made possible.

Especially with changing operating parameters such as the Be operating or ambient temperature can mismatch desired consequences.

The invention is based on the object, the term of a To detect and / or control signals on a line. This task is characterized by the features of the main claim given procedure solved.

Two embodiments of the invention are in the drawing are shown and are described in the following description explained in more detail.

Fig. 1 shows a circuit arrangement with a first exemplary embodiment and

Fig. 2 shows a circuit arrangement with a second exemplary embodiment.

In the first embodiment of the invention according to FIG. 1, a line 3 (signal line) is shown schematically, on which a DQ signal is to be transmitted from a first integrated circuit 1 to a second integrated circuit 2 . For this purpose, the integrated circuit 1 has an I / O channel (input / output channel) 6 , which essentially contains a transmitter 4 and a receiver 5 , both with their output or with their input at the same end the line 3 are connected. The Sen der 4 has a driver stage with which the signal to be sent DQout is adjusted to a predetermined level before it is given on line 3 . Accordingly, a DQ signal arriving on line 3 is processed by receiver 5 (receiver) and is available at the output of receiver 5 as a DQin signal for further processing. Here the output line is connected to a control input of a counter 7 via a stop line b. The counter 7 is started via a start line a, which is connected to an output of a delay element 8 . Counter 7 can thus be switched on or off via lines a and b.

In an alternative embodiment of the invention it is also provided that instead of the start line a, the counter 7 can be started via the transmitted DQ signal. This has a smaller amplitude than the reflected signal, as will be explained later. Thus there is also a clear possibility of differentiating between the transmitted and the reflected signal.

The receiver 5 is also connected to a source for a reference voltage Vref. This reference voltage Vref is given to a comparator of the receiver, which compares the incoming voltage of the DQ signal with the value of the reference voltage Vref and controls the DQin signal as a function thereof. The amplitude of the reference voltage can be specified. Their exact function will be explained later.

The transmitter 4 has a control input via which the DQout signal present at the input can be started. The control signal referred to as enable is connected to an input of delay element 8 . The delay element 8 has the task of forwarding the enable signal only after predetermined conditions. The delay time specified by the delay element 8 is dependent on the signal run time on the line 3 and can be adjusted or changed either manually or in dependence on operating parameters such as the ambient temperature or a component temperature, for example on the temperature of the driver stage.

The individual modules such as transmitter 4 , receiver 5 , delay element 8 or counter 7 are known per se and therefore do not need to be explained in more detail.

For the sake of completeness, it should also be mentioned that the second integrated circuit 2 is constructed similarly to the first integrated circuit 1 . Depending on its function, it too generally has a plurality of I / O channels 6 which are required for external communication.

Since the individual units are integrated directly on the integrated circuit 1 , 2 , the measuring circuit is also referred to as an on-chip circuit.

The mode of operation of this measuring arrangement is explained in more detail below. It is assumed that the line 3 is not terminated at its second end, ie it is not terminated with its characteristic impedance. As a result, the amplitude of the reflected signal is practically doubled. The reference voltage Vref is set to this increased voltage, so that the reflected signal can be clearly recognized. It was assumed that in a customized system by the voltage divider, which is formed by the output resistance of the transmitter 4 and the line impedance of the line 3 , half the signal amplitude is reached. This amplitude then reaches the full (double) height due to the reflection at the receiver 5 .

As an alternative solution, a second line can also be used, which is grounded at the receiver 5 (GND), for example. A GND signal would then also arrive at the transmitter 4 as a signal after the double transit time.

If the transmitter 4 and the receiver 5 are matched to one another, the signal line of the receiver 5 can generally be internally open, terminated or set to a predetermined voltage value, which is evaluated during the measurement. The transit time measurement is preferably carried out using the TDR method known per se (Time Domain Reflection Measurement).

After enabling the enable signal via the delay element 8 , the DQout signal is given to the line 3 via the driver stage 3 . At the same time, the counter 7 is started via the start line a. It now sums up its clock pulses until it is stopped by the reflected signal with the increased amplitude via the stop line b. The clock pulses have a fixed, known frequency, so that the time difference between sending and receiving the signal can easily be determined from the number of counting pulses. Halving this value gives the runtime of the signal on line 3 .

For example, by measuring the signal propagation time on-chip once after switching on or / or while running Operation is a continuous correction, respectively Adjustment of the signal runtime ("on the fly") possible. In order to it is advantageously no longer necessary to edge Conditions (worst case conditions) for manufacturing conditional and application-related runtime tolerances through um to determine constant simulations or experiments.

In some cases, line 3 may be terminated. In this case, it is proposed in an alternative embodiment of the invention to determine the signal propagation time by means of a further line which has properties similar to those of the terminated line.

Fig. 2 shows a further embodiment of the invention, in which, in contrast to the first embodiment, a schematic representation of two I / O channels with two lines 3 a and 3 b are shown. The two I / O channels are designed in the same way as described for FIG. 1. Furthermore, it is assumed that both lines 3 a, 3 b are controlled impedance, but whose signals DQ1 and DQ2 have different signal propagation times.

Of course, for a parallel bus, a corresponding number of lines 3 with the associated I / O channels 6 can be provided.

If the integrated circuit 1 sends the signals DQ1 and DQ2 to the receivers 4 a, 4 b of the integrated circuit 2 via the two lines 3 a, 3 b, then the incoming input signal DQIN1 and DQIN2 will be different due to the different signal delays Have arrival times. This can cause problems if the other receivers 5 a, 5 b are clocked with the same signal receive enable. For example, in the case of single date rate SDRAMs, the data from the integrated circuit 1 are sent synchronously to a clock signal to the second integrated circuit 2 and further integrated circuits, in which they must arrive at the same time in order to be evaluated logically.

By measuring the individual transit times of the two signals DQ1 and DQ2, as described above, the two transit time differences can now be compensated for by a suitable setting of the two delay elements 8 a, 8 b. In this case too, the runtime adjustment can be carried out manually or, depending on operating parameters, can be controlled automatically such that the two signals DQ1 and DQ2 arrive at the other receivers 5 a, 5 b of the integrated circuit 2 at the same time. They are then available in the correct sequence for further processing.

The exemplary embodiments are for the application of the inventions method according to the invention not on connecting lines limited between two integrated circuits. itself this process can be understood, for example, between various electronic devices such as computers, printers etc., so generally used wherever un desired runtime differences have an unfavorable impact on the May have functional reliability.  

LIST OF REFERENCE NUMBERS

1

first integrated circuit / module

2

second integrated circuit / module

3

Management (DQ management)

3

a,

3

b Management

4

Transmitter / driver stage

5

Receiver / receiver

5

a, b other recipients

6

I / O channel

7

counter

8th

delay

8th

a, b delay elements
a Start line
b Stop line
DQ electrical signal
DQ1, DQ2 signals
DQIN1 input signal
DQIN2 input signal
Vref reference voltage

Claims (13)

1. A method for determining and / or controlling the transit time of an electrical signal (DQ) on at least one line ( 3 ; 3 a, 3 b), with a transmitter at one end of the line ( 3 ; 3 a, 3 b) ( 4 ) and a receiver ( 5 ) are connected and the second end of the line is not terminated, characterized in that the transmitter ( 4 ) starts the signal (DQ) and the receiver ( 5 ) detects the time until the reflected signal is received and that the transit time of the signal (DQ) on the line ( 3 ; 3 a, 3 b) is determined by halving the time span. 2. The method according to claim 1, characterized in that the transmitter ( 4 ) is a driver of an I / O channel ( 6 ) of an integrated circuit ( 1 ). 3. The method according to any one of the preceding claims, characterized in that the receiver ( 5 ) is part of the integrated circuit ( 1 ). 4. The method according to any one of the preceding claims, characterized in that the receiver ( 5 ) is connected to a counter ( 7 ) which is started by a switch-on signal from the transmitter ( 4 ). 5. The method according to any one of the preceding claims, characterized in that the counter ( 7 ) is stopped by the increased amplitude of the reflected signal. 6. The method according to any one of the preceding claims, characterized in that the stop value for the counter ( 7 ) is predetermined by means of a reference voltage (Vref). 7. The method according to any one of the preceding claims, characterized in that the transit time of the signal can be controlled by means of a delay element ( 8 ). 8. The method according to claim 7, characterized in that in the case of a parallel signal transmission on a plurality of lines ( 3 a, 3 b) the transit times are matched to the same arrival time. 9. The method according to any one of the preceding claims, characterized in that the lines ( 3 ; 3 a, 3 b) between two modules, preferably between two integrated scarf lines ( 1 , 2 ) are connected. 10. The method according to any one of claims 8 or 9, characterized in that the lines ( 3 ; 3 a, 3 b) are bus lines of a parallel bus. 11. The method according to any one of the preceding claims, characterized in that the determination and / or control of the runtime takes place during normal operation of the integrated circuits ( 1 , 2 ). 12. The method according to any one of the preceding claims, characterized in that the determination and / or Control of the runtime after switching on the device he follows. 13. The method according to any one of the preceding claims, characterized in that the control of the runtime in Dependency of an operating parameter, preferably on the Temperature is controlled.