DE10131084A1 - Data processing system is structured to perform as a field programmable logic system - Google Patents

Abstract

The system has a program counter (14) to call sequential instructions and operates with the TOS register (7) to access sub routines using branch codes. The register is integrated into microprocessor architecture. An additional status register (11) is used.

Description

The invention relates to a device for data processing, which has a program memory Data storage, at least two stacks and at least one bus for connecting individual ones Has functional modules.

• - Registerbasiert oder Stackbasiert
• - Von-Neumann oder Harvard-Architektur

Devices for data processing are known in various embodiments depending on the intended application. In particular, there are also different microprocessor architectures that can be implemented, for example, as field-programmable logic modules (FPGAs). The processors currently available can in principle be divided according to the following architecture concepts:

• - Register-based or stack-based
• - Von Neumann or Harvard architecture

The dual-stack Harvard architecture is known, for example, in DE-PS 42 20 258 is explained. In addition, some processors are designed according to the dual stack from Neumann Architecture constructed, for example, in the publications US Pat. No. 5,070,451, U.S. Patent 5,404,555 and U.S. Patent 5,659,703 are discussed.

Typically, the instruction structures of the vast number of processors see that Possibility to enter numerical values, so-called literals, as data or addresses in the instruction code it yourself or add it sequentially to the instruction. This will make the Instruction structure or the instruction width depends on the width of the Data words.

Another type of microprocessor architecture, namely the transputer architecture, is described in US Pat U.S. Patent 4,704,678 and U.S. Patent 4,724,517. Here are those for a complete Characterization of an instruction required literals not attached to the instruction, but each according to the size of the value in one or more parts as separate literal instructions prefixed. The individual parts become literal in a special operand register accumulated and made available to the following instruction. This will not only make the Instruction width regardless of the width of the data words, since with the data word width at most the number of consecutive literal instructions to represent a particular one numerical value varies, but the sequential sequence of literal and Surgical instructions can also be interrupted at any time because each of these instructions is in itself is completed.

Typical of the microprocessor architectures currently available is the trend with minimal To provide hardware as universal properties as possible, so that special The requirements of individual programming languages are hardly taken into account. Generally lies currently a major problem for users in that when implementing control systems there is a significant dependency on the processor components available on the market, whereby the paradigm of "processor-independent programming" is promoted through high-level languages.

The object of the present invention is to introduce a device for data processing mentioned type in such a way that a processor core is provided with little logic who, in particular, the programming language Forth (ISO / IEC 15145) from the instructional repertoire supported here, which can be synthesized in field programmable logic components (FPGAs) and on the data word width specified by the application can be adapted.

This object is achieved in that a "top-of-stack" register (TOS) sequentially both as an accumulator for literal instructions and as a memory for Operands and is used as an address register for the data memory, and that a respective Activation of use is predetermined by a program control, which is a respective Evaluates the program code in which the respective use of the TOS is defined.

Another object of the present invention is to provide a device of the type mentioned in the introduction to be provided in such a way that to support field programmable synthesizability an optimized memory structure is provided with little logic effort. This task will solved according to the invention in that a division of the memory areas is realized such that there is a Harvard architecture with a separate data stack.

The proposed processor architecture also makes it easy to provide Structure with low logic effort enables different, depending on the application requirements Realize data word widths without simultaneously changing the instructions and their Causing width. In addition, it is due to the instruction structure (external, more vertical Microcode) possible to use structural possibilities for parallel processing. This will High data throughput is achieved even at a relatively low clock rate.

By using the TOS as both an operand register for unary and binary operations, for Accumulation of literal instructions in the program code for use by a subsequent operation, as well as an address register for access to data in the data storage device Independence of the data word width from the instruction width is achieved and on the other hand the Possibility of relative and indexed addressing with little effort because the existing adders can be used for binary operations.

A typical application is defined in that the TOS register described above is integrated into a microprocessor architecture.

To support a manufacturability in small quantities and the possibility to application-specific modifications it is proposed that primarily a realization in field-programmable logic modules (field programmable gate arrays, FPGA) is present.

Universal applicability is supported by the fact that in the area of program control an instruction format is implemented independently of a data word width.

This also provides a high degree of flexibility in use with a simple basic structure that there is a dual-stack Harvard architecture.

An effective and at the same time adapted to the hardware structure programmability provided that the program control for processing program instructions as an assembler is trained for the programming language Forth (ISO / IEC 15145).

To support the use of the TOS register as an accumulator for literals, that each instruction has a corresponding marker bit that the literal instructions of the surgical instructions.

Another freedom of use when using the TOS register for data storage addressing can be provided by an auto increment / auto decrement of the TOS register in Dependence on a respective opcode is realized.

To enable compact addressing of program branching operations by Using difference addresses, it is proposed that a accumulated in the TOS register, signed literal is added to the program counter.

An optimization of the memory utilization can be supported by a return stack, which takes the return addresses of subroutine calls, physically a RAM Area is assigned in which the data storage is defined.

An optimization of the address space usage can be supported in that the addresses of Input and output registers are placed in the address area of the data memory, which is from the Return stack is used.

Relative addressing with regard to the return stack pointer allows local variables in the Area of the return stack.

A mechanism for processing program interruptions allows use in Applications in which various asynchronous external events are processed in real time have to.

A mechanism to suppress instruction processing while jumping a specific program address permits use in applications in which external Events must be maintained without blocking the processor so that it can be used during the Waiting time in multi-program operation (multitasking) can do other tasks.

Exemplary embodiments of the invention are shown schematically in the drawing. Show it:

Fig. 1 shows a basic structure of the Mikroprozessorarchitekur,

Fig. 2 is an optional advanced microprocessor architecture,

FIG. 3, an instruction set in tabular form,

Fig. 4, a list of commands for performing branching, subroutine calling and Returns commands and interrupts,

Fig. 5 a list of the commands of the arithmetic logic unit

Fig. 6 shows a list of commands for performing data storage and register operations,

Fig. 7 is a list of status bits and their meaning, which are summarized in the status register, and

Fig. 8 a list of the operations of the Forth programming language that can be executed in one or two processor instructions and their coding.

According to the embodiment in FIG. I, independent memory areas of the device for data processing are divided into a program memory ( 1 ), a data memory ( 2 ) and a stack memory ( 3 ) which, in cooperation with the data stack pointer DSP ( 8 ), realizes a stack. A data exchange between registers and the application-specific input and output registers not shown here takes place via a bus ( 4 ).

An arithmetic-logic unit ALU ( 5 ) is used to carry out the necessary arithmetic operations, which obtains its operands either from the top two stack elements, which are registered as registers TOS ( 7 ) (Top-Of-Stack) and NOS ( 6 ) (Next- Of-Stack) are executed, or from the top stack element TOS ( 7 ) and part of the instruction register INST ( 9 ) or the program counter PC ( 14 ). The stack for the elements below the second element is realized as an implementation from the stack memory ( 3 ) and the data stack pointer DSP ( 8 ).

To support the processing of instructions, an instruction register INST ( 9 ) with a subsequent instruction decoder ( 18 ), the TOS register ( 7 ) with its possibility of accumulating literal instructions, and a status register STATUS ( 11 ) are used.

The program memory ( 1 ) is controlled via a multiplexer MUX ( 13 ), which provides the address of the subsequent instruction in accordance with the instruction that has just been executed. The address of the sequential subsequent instruction is provided in the program counter PC ( 14 ), which is loaded at the end of each clock cycle by means of an incrementer ( 15 ) with the current instruction address increased by one.

In the case of program branches, the content of the TOS register ( 7 ) is controlled by a respective program code with absolute addressing and, with relative addressing, the sum formed in the ALU ( 5 ) from the content of the TOS register ( 7 ) and the content of the program counter PC ( 14 ) via the multiplexer MUX ( 13 ) on the program memory ( 1 ).

When subroutine calls are made, the content of the program counter PC ( 14 ) is stored on the return stack or when the subroutine returns from the return stack via the multiplexer MUN ( 13 ) to the program memory ( 1 ). The return stack is implemented in the data memory by means of the return stack pointer RSP ( 12 ), the return stack pointer RSP ( 12 ) on the two lines ( 100 ) and ( 101 ) simultaneously being the address of both the top element of the return stack, to which a pop Operation would also provide the address of the first free space on the return stack, which would be accessed by a push operation. The data stack consists of the data stack pointer DSP ( 8 ), the stack memory ( 3 ) and the registers NOS ( 6 ) and TOS ( 7 ) for the top two stack elements.

If the bit "IntEnable" in the status register STATUS ( 11 ) is set, program interruptions are processed at any time in that when there is an interrupt request by the signal "external event" ( 107 ), which was synchronized by the interrupt unit ( 10 ), the current cycle is carried out, but in deviation from the normal sequence via line ( 102 ) the current program memory address is loaded into the program counter PC ( 14 ), a special interrupt instruction INTERRUPT is loaded via the read-only memory ( 17 ) into the instruction register INST ( 9 ) , and the status bit "Lit" about the state of the TOS register with respect to the literal accumulation is stored in the status register STATUS ( 11 ). In the following cycle, the charged one (17) interruption instruction is executed, applied via the multiplexer MUX (13) the address of the interrupt handling routine ISR from the read-only memory (16) in the program memory (1), the contents of the program counter PC ( 14 ) on the return stack and the content of the status register STATUS ( 11 ) is saved on the data stack.

At the same time that the INTERRUPT instruction is loaded into the instruction register, that too Status bit "IntlnService" (IIS) set, which indicates that there is a program interruption is processed. As long as the IIS bit is set, further or persistent "external ones Events "does not lead to further program interruptions. The interruption treatment Routine ends with the instruction IRET, which in addition to a normal subroutine Return also restores the status register from the data stack. This will make it IIS bit reset so that program interruptions are accepted again.

Synchronization with external events is achieved without requesting status information in that when an attempt is made to access an external data item that is not yet available, the external unit activates the signal “not ready” ( 108 ) during the current cycle. As a result, the cycle does not end as usual, but all processor registers maintain their previous state with the exception of the instruction register INST ( 9 ), into which the PAUSE instruction is loaded from the read-only memory ( 23 ). In the subsequent cycle, the address of the task change handling routine TSR from the read-only memory ( 22 ) is applied to the program memory ( 1 ). Before attempting to access the external data again, which was "not ready", the return address on the return stack only has to be decremented before the corresponding task can be started again by the IRET instruction.

Based on this mechanism, a register of blocking semaphores can be implemented in a simple manner (not shown in FIG. 1). If a certain bit of the semaphore register was set to '1' and a process tries to write another '1' to the same bit position, the signal "not ready" is triggered internally and the task change handling routine TSR is started.

Furthermore, the PAUSE instruction can be at any one during the debugging Place the object code to interrupt the normal program flow to call the debugger.

To implement an auto increment / auto decrement when accessing the data memory, the TOS register ( 7 ) and the instruction register INST ( 9 ) are applied to the adder of the ALU ( 5 ). The total is stored in TOS ( 7 ) at the end of the cycle. For reasons of runtime efficiency, however, the current content of the TOS register ( 7 ) is applied as an address to the data memory ( 2 ) via line 106 , and at the same time the date is transmitted via bus ( 4 ) between the data memory ( 2 ) and the NOS register ( 6 ) transferred. This topology results in a post increment / post decrement for auto-incrementing data storage access.

FIG. 2 shows an embodiment in which, in addition to the embodiment shown in FIG. 1 for realizing a "decrement and branch instruction" with automatic data recovery in the case of subroutine calls, the uppermost element of the return stack as register TOR (top-of-return stack) ( 19 ) in cooperation with a decrementer ( 20 ). In addition, if the decrementer ( 20 ) is present, there is the possibility of calling the task change handling routine TSR ( 23 ) by means of the "not ready" signal ( 108 ) to read the contents of the program counter PC ( 14 ) via the decrementer ( 20 ). on the return stack so that the return address then already refers to the program code required to restart the task.

To implement addressing of the data memory relative to the return stack, the address ( 100 ) of the return stack pointer RSP ( 12 ) is routed via line 103 to the adder of the ALU ( 5 ), so that when addressing the data memory ( 2 ) via the output of the ALU ( 105 ) accesses the date on the return stack, the index of which is in the TOS register ( 7 ).

With this configuration, it makes sense to carry out the access as a pre-increment / predecrement operation depending on a respective opcode when the data memory ( 2 ) is absolutely addressed by means of the TOS register ( 7 ), since the line ( 105 ) is already connected to the data memory ( 2 ) is performed.

To implement addressing of the data memory relative to a quasi-constant base address, the TASK register ( 21 ) is provided, which is led to the adder of the ALU ( 5 ) by means of line 104 , so that when addressing the data memory ( 2 ) via line 105 Data is accessed whose base is in the TASK register ( 21 ) and whose offset is in the TOS register ( 7 ). This allows, for example, efficient multi-program operation (multitasking) with the ability to write programs that are re-entry-capable, whereby the TASK register ( 21 ) refers to the information block that characterizes the currently active process and its task-local variables.

The processor has three memory areas which can be controlled in parallel, namely the program memory ( 1 ), which can only be read, the data stack ( 3 ) in the form of RAM and the data memory ( 2 ), also in the form of RAM, in which simultaneously the return stack is housed and managed by the return stack pointer RSP ( 12 ). This memory division makes it possible, for. B. within a clock cycle to save a date from the data stack in the data memory and at the same time read the next instruction from the program memory ( 1 ) or z. B. at the same time to store the status register STATUS ( 11 ) on the data stack, to execute a subroutine call, the return address being stored on the return stack and to read the first instruction of the subroutine from the program memory ( 1 ).

Each instruction contains a flag bit that indicates whether it is an instruction to be executed (operation instruction) or a part of a literal (literal instruction) that precedes an instruction to be executed subsequently. Several literal instructions can follow one another immediately and are combined into larger literals in the TOS register ( 7 ). The marker bit is stored in the status register STATUS ( 11 ) for the subsequent cycle, so that the semantics of the subsequent instruction can be determined accordingly. This makes the data word width independent of the instruction width, which is always the same width. This also means that the processor can be interrupted at any time without special circumstances.

• 1. Dem Programmzähler (14), wenn die sequentielle Folgeinstruktion geholt wird.
• 2. Dem Bus (4), über den gemäß eines entsprechenden Opcodes bei einer absoluten Verzweigung oder einem absoluten Unterprogrammaufruf der Inhalt des TOS-Registers (7), bei einer relativen Verzweigung oder einem realtiven Unterprogrammaufruf die Summe des Programmzählers PC (14) und des Inhalts des TOS-Registers (7) oder bei einem Rücksprung von einem Unterprogramm der Returnstack geleitet wird. Wird die relative Adressierung auf die Fälle beschränkt, in denen der Offset im TOS-Register immer aus Literalinstruktionen zusammengesetzt wird, so kann zur Verbesserung des Laufzeitverhaltens die Addition des Programmzählers mit dem in Akkumulation befindlichen Literal im TOS-Register bereits einen Zyklus vor Ausführung des Verzweigungs-Opcodes begonnen werden.
• 3. Der festen Adresse ISR (16) der Unterbrechung-Service-Routine.
• 4. Der festen Adresse TSR (23) der Taskwechsel-Service-Routine.

The address for the next instruction from the program memory ( 1 ) is provided via the multiplexer MUX ( 13 ) from one of the following possible sources:

• 1. The program counter ( 14 ) when the sequential instruction is fetched.
• 2. The bus ( 4 ), according to a corresponding opcode with an absolute branch or an absolute subroutine call, the content of the TOS register ( 7 ), with a relative branching or a realistic subroutine call, the sum of the program counter PC ( 14 ) and the Contents of the TOS register ( 7 ) or in the event of a return from a subroutine the return stack is directed. If the relative addressing is limited to the cases in which the offset in the TOS register is always composed of literal instructions, the program counter can be added to the literal in the TOS register that is in accumulation one cycle before the branch is executed to improve the runtime behavior -Opcodes are started.
• 3. The interrupt service routine's fixed address ISR ( 16 ).
• 4. The fixed address TSR ( 23 ) of the task change service routine.

With the exception of the interrupt processing cycle, the incrementer ( 15 ) always loads the address increased by one from the output of the multiplexer ( 13 ) into the program counter ( 14 ), so that the sequential subsequent address is available there in the subsequent cycle.

Claims (19)

1. A device for data processing, which has a program memory, a data memory, at least two stacks and at least one bus for connecting individual function modules, characterized in that a top-of-stack register TOS ( 7 ) successively in time both as an accumulator for literal instructions , and also as an operand register for the arithmetic-logic unit ALU ( 5 ) and that a respective usage activation is predefined by a program control which evaluates a respective program code in which the respective use of the TOS register ( 7 ) is defined. 2. Device according to claim 1, characterized in that the top-of-stack register ( 7 ) is integrated in a microprocessor architecture. 3. Device according to claim 1 or 2, characterized in that there is additionally a status register ( 11 ) which contains at least one carry flag and a literal flag. 4. Device according to one of claims 1 to 3, characterized in that an implementation is in a field programmable logic module (FPGA). 5. Device according to one of claims 1 to 4, characterized in that in the area of Program control an instruction format is implemented regardless of a data word width. 6. Device according to one of claims 1 to 5, characterized in that a dual stack Harvard architecture is present. 7. Device according to one of claims 1 to 6, characterized in that the Program control for processing program instructions as assembler for the programming language Forth is trained. 8. Device according to one of claims 1 to 7, characterized in that each instruction a marker bit that contains operation instructions of literal instructions different. 9. Device according to one of claims 1 to 8, characterized in that branches or subroutine calls are made to the address contained in the top-of-stack register TOS ( 7 ). 10. Device according to one of claims 1 to 9, characterized in that branches or subroutine calls are implemented relative to the program counter PC ( 14 ). 11. Device according to one of claims 1 to 10, characterized in that the external signal "not ready" ( 108 ) leads to an abort of the cycle currently running and to the calling of a subroutine at a fixed address. 12. The device according to one of claims 1 to 11, characterized in that an auto-increment / auto-decrement of the TOS register ( 7 ) is implemented as a function of a respective opcode. 13. Device according to one of claims 1 to 12, characterized in that when accessing the data memory ( 2 ) the top-of-stack register TOS ( 7 ) contains the address and a transfer of the date between the data memory and the next- Of-stack register NOS ( 6 ) is provided. 14. Device according to claims 12 and 13, characterized in that the auto-increment / auto-decrement on addressing the data memory ( 2 ) via line 105 is executed as a pre-increment / predecrement. 15. Device according to claims 12 and 13, characterized in that the auto-increment / auto-decrement on addressing the data memory ( 2 ) via line 106 is carried out as a post-increment / post-decrement. 16. Data processing device comprising a program memory, a data memory, at least two stacks and at least one bus to connect individual ones Has functional modules, characterized in that a division of the Memory areas are implemented in such a way that a Harvard architecture is present. 17. The apparatus according to claim 16, characterized in that a return stack is physically assigned to a RAM area in which the data memory ( 2 ) is defined. 18. The apparatus according to claim 16 or 17, characterized in that local variables in Area of the return stack can be saved. 19. Device according to one of claims 16 to 18, characterized in that the data memory ( 2 ) is addressable relative to a base address register TASK ( 21 ).