DE10130752B4 - Semiconductor memory device with circuit for generating a boosted potential and associated control method - Google Patents

Abstract

A semiconductor memory device comprising:
a memory cell array (10) having a plurality of word lines (11);
a word selection circuit (3) that activates one of the plurality of word lines based on the value of an address;
a boosted potential generating circuit (5-8) coupled to the word selecting circuit (3), wherein the boosted potential generating circuit supplies an amplified potential to the word selecting circuit (3) when the word line is to be activated characterized in that the boosted potential generating circuit (5-8) detects a command to activate a word line (11) and supplies a higher potential than a first fixed potential before the word line (11) has been activated.

Description

TECHNICAL AREA

The The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a control method, which a potential reduction of a word line potential power supply can suppress it to a word line selection.

BACKGROUND OF THE INVENTION

A Semiconductor memory device, such as a dynamic Random Access Memory (DRAM), may have a memory cell which by a memory cell transistor and a memory cell capacitor is formed. The memory cell transistor is typically a n-type field effect transistor with insulated gate (IGFET). The control gate of the Memory cell transistor is connected to a word line, a Source / drain is connected to a bit line and another source / drain is connected to connected to the memory cell capacitor. The memory cell capacitor stores a charge that is the logical level of the stored in the memory cell Indicates bits. Because the potential of the source terminal of an n-type IGFET limited to a threshold voltage (Vt) below the potential which is connected to the gate terminal of the n-type IGFET is applied, which is held in the memory cell capacitor Potential limited. In the case where a power supply voltage Vint is the maximum potential applied to a word line the memory cell capacitor has a maximum potential of Vint - Vt, where Vt is the threshold voltage of the memory cell transistor. Consequently even if a data potential corresponding to the power supply Vint is applied to the bit line, a potential of Vint - Vt in Memory cell capacitor stored. This can affect data integrity and / or Affect refresh specifications.

To the Preventing the above problem, the wordline typically becomes supplied a potential, the higher when the power supply potential is Vint. The potential, that higher than that Power supply voltage Vint is, as word line activation potential be considered. The word line activation potential may be the potential to provide an adequate charge transfer is necessary to and from the memory cell capacitor.

It There are two approaches for obtaining a voltage higher than the power supply voltage Vint is.

One Approach uses an oscillator that multiplies with one Charge pump rectifier connected is. The approach can constant increased or increased tension respectively.

One Another approach is to use a bootloader capacitor, so the existence Bootloader over a word line supply potential can be placed.

According to 9 Fig. 12 is a schematic block diagram of a conventional DRAM and is the general reference numeral 100 allocated.

A conventional DRAM 100 contains a command decoder 101 which decodes a command received from a central processing unit (CPU) and a control signal to a row control circuit 104 supplies. Also included is an address buffer 102 receiving an address signal and a row address to a word selection circuit 103 and a column address to a bit selection circuit 109 supplies. The command decoder 101 supplies a row enable signal RE to the address buffer 102 and to the word selection circuit 103 ,

The conventional DRAM 100 contains a field of memory cells 110 , Memory cells (for example, a memory cell 113 ) are at the interface of a bit line (eg a bit line 112 and a wordline (eg, a wordline 111 ) educated. The word selection circuit receives a boosted voltage VPP from an amplifier circuit 108 and selects based on that from the address buffer 102 received address value a word line 111 when the row enable signal RE becomes active. The amplified voltage VPP is applied to a selected word line 111 created.

A circuit for detecting an amplified potential 106 receives the amplified potential VPP and detects whether the amplified potential VPP falls below a predetermined potential or not. The circuit for detecting an amplified potential 106 provides a boost voltage signal VBUP to an oscillator circuit 107 and an amplifier circuit 108 , The oscillator circuit 107 provides an oscillation signal VBOS to the amplifier circuit 108 ,

A sense amplifier 114 includes a data signal in a row of selected memory cells (eg, the memory cells associated with the selected wordline) 111 are connected). The bit selection circuit 109 then selects a column (for example, the bit line 112 ) based on one of the address buffers 102 received column address. Thus, data becomes or becomes from the conventional DRAM 100 by means of an input / output (I / O) buffer 115 delivered.

Now take reference 10 13 is a schematic circuit diagram of a boosted potential detection circuit 106 demonstrated. The circuit for detecting an amplified potential 106 is the circuit for detecting an amplified potential 106 of the 9 ,

The circuit for detecting an amplified potential 106 has resistance devices (R101a and R101b) connected in series between the boosted potential VPP and the ground GND. The amplified potential VPP is connected to one terminal of the resistance device R101a. One terminal of the resistance device R101b is connected to the ground GND. The other terminals of the resistance devices (R101a and R101b) are connected to supply a potential to an input terminal of a comparator circuit COM101. A reference potential Vs is supplied to the other input terminal of the comparator circuit COM101. The boost voltage signal VBUP is output from the comparator COM101. The resistance values of the resistance devices (R101a and R101b) are determined based on the values of the desired amplified potential VPP and the reference potential Vs, so that when the amplified potential is at a desired potential, one at the junction of the resistance devices (R101a and R101b). obtained potential is equal to the reference voltage Vs.

Now take reference 11 Figure 13 is a schematic circuit diagram of an oscillator circuit 107 demonstrated. The oscillator circuit 107 is an oscillator circuit 107 of the 9 ,

The oscillator circuit 107 has a NAND gate NAND110 and inverters (IV111 to IV115). The NAND gate NAND110 and the inverters (IV111 to IV114) are connected in series to form a ring oscillator circuit, the output of the inverter IV114 being connected to an input of the NAND gate NAND110. The NAND gate NAND110 also receives the boost voltage signal VBUP at an input. The inverter IV115 is connected to receive the output of the inverter IV114 as an input, and supplies the oscillation signal VBOS as an output.

When the boost voltage signal VBUP is at a high logic level, the oscillator circuit oscillates 107 and the oscillation signal VBOS periodically changes the logic level. However, when the boost voltage signal VBUP is at a low logic level, the oscillator circuit stops 107 an oscillation, and the oscillation signal VBOS is maintained at a predetermined logic level (logic low).

Now take reference 13 Figure 13 is a schematic diagram of an amplifier circuit 108 demonstrated. The amplifier circuit 108 is an amplifier circuit 108 of the 9 ,

The amplifier circuit 108 has transistors (Tr111 and Tr112), an inverter IV116, a boosting capacitor Cc and a smoothing capacitor Cd. A power supply voltage Vint is connected to the gate and the source of the transistor Tr111. A drain of the transistor Tr111 is connected to a node a. The inverter IV116 receives an oscillation signal VBOS as input and provides an output to a terminal of the amplification capacitor Cc at a node b. Another terminal of the amplification capacitor Cc is connected to the node a. The transistor Tr112 has a source and a gate connected to the node a, and a drain connected to the smoothing capacitor Cd at a node c. A boosted potential VPP is an output at node c. Another terminal of the smoothing capacitor Cd is connected to the ground potential.

Now, the operation of the amplifier circuit or booster circuit or booster circuit 108 described.

If the oscillation signal VBOS is high, is the node b at a low potential. The node a is then replaced by the Transistor Tr111 to a potential of the power supply voltage Vint minus Vt (a threshold voltage of transistor Tr111). When the oscillation signal VBOS transitions to logic low, node b transitions to a high potential (Vint). The knot a is then boosted to 2Vint minus Vt. Of the Transistor Tr112 in diode connection then carries a charge and transmits it from boost capacitor Cc to the smoothing capacitor CD. The oscillation signal VBOS continues to oscillate, and the reinforced Potential VPP has a theoretical limit of (2Vint - 2Vt), where 2Vt is the combined threshold voltages of the transistors (Tr111 and Tr112).

The increased Potential VPP can be increased by increasing the number of stages of the transistor Tr112 and the amplification capacitor Cc increased become.

Now take reference 12 13, there is shown a timing chart illustrating an amplifying operation in the conventional DRAM 100 represents.

According to 12 relating to 9 decoded in conventional DRAM 100 , when a Command in a command decoder 101 is input, the command decoder 101 the command. When the command is a data read, data write or refresh command, the command decoder issues a control signal ACT / REF as a single or stable signal to the row control circuit 104 out. The line control circuit 104 gives a row enable signal RE for activating the address buffer 102 and the word selection circuit 103 out. During the time at which the instruction enters the instruction decoder 101 is input, also an address signal in the address buffer 102 entered. The address buffer 102 transmits the address in synchronization with the rise of the row enable signal RE to the word selection circuit 103 ,

Now take reference 10 , is in the circuit for detecting an increased or increased potential 106 the amplified potential VPP is input to one terminal of the resistance device R101a. Resistance values of the resistors (R101a and R101b) are selected so that the potential at the connection node between the resistance devices (R101a and R101b) is VPP / 2. The comparator COM101 compares the potential VPP / 2 with the reference potential Vs. The reference potential Vs is set to 2.0V. When the potential VPP / 2 is higher than the reference potential Vs (eg, 2.0 V), the boosted voltage signal VBUP is logically low. However, when the boosted potential VPP drops so that the potential VPP / 2 falls below the reference potential Vs, the boosted voltage signal VBUP is logically high. This indicates that the amplified potential VPP has dropped below the desired minimum potential of 4.0V.

Take again reference 12 , at a time before the command has been input, it can be seen that the boosted potential VPP falls below the minimum potential of 4.0V. Then, the amplified voltage signal VBUP becomes logic high. Now take reference 11 , receives the oscillator circuit 107 the logic high amplified voltage signal VBUP. The oscillator circuit 107 will be released. Thus, the oscillation signal VBOS starts to oscillate a time delay Δt1 after the amplified potential VPP falls below the minimum potential (4.0 V), and the amplification circuit 108 begins to reinforce the increased potential VPP. The time delay Δt1 is determined by the propagation delay of the amplified potential detection circuit 106 and the oscillation circuit 107 certainly.

After the command from the command decoder 101 is received, the command decoder gives 101 when the command is a data read, a data write or a refresh command, a control signal ACT / REF as a stable signal to the row control circuit 104 out. The line control circuit 104 gives a row enable signal RE for activating the address buffer 102 and the word selection circuit 103 out. During the time at which the instruction enters the instruction decoder 101 is input, also an address signal in the address buffer 102 entered. The address buffer 102 transmits the address in synchronization with the rise of the row enable signal RE to the word selection circuit 103 ,

When the word selection circuit 103 receives the active row enable signal RE, connects the word select circuit 103 the amplified power potential VPP electrically connected to a word line (eg, the word line 111 ). A wordline 111 is connected to a large number of memory cells. Thus, a word line has a relatively large word line capacitance Cw. This causes the boosted power potential VPP to drop immediately as shown in FIG 12 is shown.

Accordingly, the boosted potential detection circuit is provided 106 a logic high amplified voltage signal VBUP. A time delay Δt2 after the amplified potential VPP drops, the oscillator circuit starts 107 to oscillate and deliver an oscillating oscillation signal VBOS. The amplifier circuit 108 then begins to amplify the amplified potential VPP. Thus, it can be seen that the boosted potential VPP does not start to recover until a time delay Δt2 after the boosted potential VPP drops. When the boosted potential VPP becomes higher than 4.0V, the boosted voltage signal VBUP returns to low, and the oscillator circuit 107 and the amplifier circuit 108 will be closed.

In In recent years, the capacity of DRAMs is steadily increasing. When The result is the number of memory cells selected during an activation operation greater. Consequently will be a larger number of memory cells having a boosted potential VPP to the Control gates of the memory cell transistors supplied. This increases the capacity Cw, the the reinforced Potential VPP charges, when memory cells selected become.

When a word line is selected, a charge on a smoothing capacitor Cd is transferred to the selected word line. This charge transfer causes the boosted potential VPP to drop as determined by the capacitance ratios between the smoothing capacitor Cd and the wordline capacitance Cw and their respective potentials. Due to the time delay Δt2 before the boosted potential VPP starts to recover, a sufficient boosted voltage VPP can not be immediately obtained be. When the boosted voltage VPP becomes lower, the word line potential Vw slowly recovers to an appropriate level. This can affect the operating speed of the DRAM.

Of the Voltage drop of the amplified Potential VPP can be increased by increasing the capacity value of the smoothing capacitor Cd be scaled down. However, this increases the chip size, which in turn increases production costs.

An example of the second amplification method is disclosed in Japanese Published Unexamined Patent Application JP 05-151773 A shown.

The second amplification method contains one Detecting the application of the row address indication (RASB) signal and a temporary one Reinforce one Potential RX, which is supplied to the word line driver. Because, however, a reinforcing temporarily under Using a pulse is performed, the level of the increased Voltage fluctuate greatly. Various factors can be the fluctuation of the potential RX cause. Such factors contain fluctuations from: transistor characteristics, wiring resistances, parasitic capacitance, power supply voltages and Temperatures, which are just a few examples.

If the level of the amplified Voltage (the potential RX) is too high, a voltage at the Memory cell cause the Cell transistor is deteriorated and the life of the semiconductor memory device shortened becomes. Alternatively, if the level of the boost voltage is too low, no sufficient amount of charge is supplied to the memory cell capacitor. Thus, data integrity is degraded and insufficient charge may be available for a read operation, or the reading operation may be delayed because it is for the sense amplifier longer can take the differential voltage on a bit line pair suitable to capture. Likewise, the data will be in the memory cell deteriorate faster over time and must have the refresh period shortened become.

As well can if the parasitic capacity the word line gets bigger, no predetermined level of boosted voltage can be achieved without to increase the amplification capacity. This increased amplification capacity must by a big Be driven transistor. As a result of these factors, the Chip size of the semiconductor memory device greater. As well A continuous charging and discharging of large capacitors can cause a noise generate on the chip which operations, such as a Reading, can influence.

in view of the discussion above would be it desirable a semiconductor memory device with a control method create that can increase a word line potential, without the chip size disadvantageous to influence. It would be also desirable the potential drop of a reinforced To suppress potential if a wordline is selected becomes. It would be also desirable to reduce the time to start a recovery of the reinforced Potential and to improve read and write speeds is required. It would be also desirable to reduce the occurrence of noise that comes from providing a reinforced Potentials can be generated.

From the JP 11-288588 A A semiconductor circuit for generating an increased voltage is known, comprising an internal voltage generating circuit for generating an internal voltage of a predetermined level, a detection circuit for detecting the voltage level of the internal voltage and an initialization circuit for activating the detection circuit for a fixed period of time when a power supply is on a power supply node is started, wherein the detection circuit is activated in response to an internal control signal after a predetermined period of time.

SUMMARY OF THE INVENTION

According to the present The invention is a semiconductor memory device according to claim 1 and a control method for controlling a semiconductor memory device according to claim 8 proposed.

According to one another aspect of the embodiments may be a gain control circuit single or single loop gain control signal which indicates that one Word line is to be activated.

According to one another aspect of the embodiments For example, a boosted potential detection circuit may amplify the control signal receive and can be a fortified Voltage signal having an oscillator enable state and an oscillator disable state deliver. The reinforced Voltage signal may have the oscillator enable state when the gain control signal indicates that the Word line is to be activated.

According to one another aspect of the embodiments can the amplified Voltage signal to have the oscillator enable state when the node a reinforced Potential drops below a predetermined potential.

According to one another aspect of the embodiments can the amplified Voltage signal to have the oscillator enable state when the amplified potential is lower than a predetermined potential when the boost control signal is not indicates that the Word line is to be activated. The amplified voltage signal can be the Have oscillator enable state when the boosted potential is lower than is a second predetermined potential when the gain control signal indicates that the Word line is to be activated. The second predetermined potential can be bigger than be the first predetermined potential.

According to one another aspect of the embodiments For example, the oscillator circuit may include an oscillation signal generator and an oscillator presetting circuit contain. The oscillation signal generator can oscillate when the reinforced Voltage signal in the oscillator enable state, and the oscillator preset circuit may cause the oscillation signal generator to an opposite start state Preset when the amplified voltage signal is in the oscillator lockout state.

According to one another aspect of the embodiments For example, an oscillation circuit may be coupled to an oscillation signal which can have periodic logic transitions when the amplified voltage signal in the oscillator release state. An amplifier circuit can be coupled be to charge in response to logic transitions in the oscillation signal to Knot of a reinforced To deliver potential.

According to one another aspect of the embodiments may be a gain control circuit Gain control signal in response to a control signal indicating that a word line is to be activated. The gain control signal may may be a single pulse and an instruction decoder may be one of Outside received command and generate the control signal.

According to one another aspect of the embodiments For example, the boosted potential detection circuit may be a comparator containing a reference potential and a boosted level, which indicates a potential, can compare, and can be an amplified voltage signal with an oscillator enable state generate when the reference potential is greater than the potential for display a reinforced Level is.

According to one another aspect of the embodiments For example, the boosted potential detection circuit may receive the boost control signal with a first gain control logic state generate when a word line is to be released. The circuit for Capturing an increased potential can the amplified Generate voltage signal with the oscillator enable state when the gain control signal the first gain control logic state Has.

According to one another aspect of the embodiments For example, the boosted potential detection circuit may include a voltage divider circuit contain a reinforced Can receive potential, and deliver a potential that is proportional to reinforced Potential is. A comparator can use the proportional potential the reinforced one Compare potential and the amplified voltage signal based deliver on the comparison.

According to one another aspect of the embodiments For example, the boosted potential detection circuit may be a first and a second voltage divider circuit according to the logical Value of the gain control signal selectable can. This can reinforce the knot Enable potentials a higher one To have potential when selecting a word line.

According to one another aspect of the embodiments For example, a control method for controlling a semiconductor memory device with an amplifier circuit, the one reinforced Can generate potential in response to an oscillation signal passing through an oscillator circuit can be generated, the following steps include: receiving a command and an address, decoding of the command, generating a gain control signal in response to the decoded command indicating that to activate a wordline is, delivering a charge to a node of an amplified potential in response to the gain control signal, Providing an electrical connection between the node a reinforced Potentials and the word line according to the value of the received Address.

According to one another aspect of the embodiments For example, the step of supplying a charge to the node of an amplified potential a reinforced one Deliver potential greater than that is an activation potential of the word line.

According to one another aspect of the embodiments For example, the step of generating a boosted control signal may generate of the reinforced Control signal with a single pulse included.

According to another aspect of the embodiments, the step of supplying a charge to a boosted node includes generating the oscillation signal with an oscillation signal period between logical transitions. The oscil The lation signal can be generated in response to the gain control signal.

According to one another aspect of the embodiments may include generating the oscillation signal in response to the gain control signal Generating an oscillation control signal in response to the gain control signal contain. The oscillation signal may have a last oscillation state when the oscillation control signal is in an oscillation locked state is, and the oscillation signal can be compared to a last Oscillation state to go opposite state when the control signal goes to an oscillation release state, without it through the oscillation signal period is delayed between transitions.

BRIEF DESCRIPTION OF THE DRAWINGS

1 FIG. 10 is a schematic block diagram of a semiconductor memory device according to an embodiment of the invention. FIG.

2 Fig. 10 is a schematic circuit diagram of a gain control circuit according to an embodiment of the invention.

3 FIG. 12 is a schematic circuit diagram of a boosted potential detection circuit according to an embodiment of the invention. FIG.

4 FIG. 12 is a schematic circuit diagram of an oscillator circuit according to an embodiment of the invention. FIG.

5 FIG. 13 is a timing diagram illustrating the operation of a gain control circuit according to an embodiment of the invention. FIG.

6 FIG. 13 is a timing diagram illustrating the boost operation according to an embodiment of the invention. FIG.

7 FIG. 12 is a schematic circuit diagram of a boosted potential detection circuit according to an embodiment of the invention. FIG.

8th FIG. 13 is a timing diagram illustrating the boost operation according to an embodiment of the invention. FIG.

9 Fig. 10 is a schematic block diagram of a conventional DRAM.

10 FIG. 12 is a schematic circuit diagram of a conventional boosted potential detection circuit. FIG.

11 Fig. 10 is a schematic circuit diagram of a conventional oscillator circuit.

12 FIG. 13 is a timing chart illustrating the amplifying operation of a conventional DRAM. FIG.

13 is a schematic diagram of an amplifier circuit.

DETAILED DESCRIPTION THE EMBODIMENTS

Now Be different embodiments of the present invention in detail with reference to a Number of drawings described.

Now take reference 1 1, a semiconductor memory device according to an embodiment is shown in a schematic block diagram, and it is the general reference numeral 50 allocated. It is understood that the in 1 illustrated semiconductor memory device 50 only show parts that may be relevant in discussing the present invention.

The semiconductor memory device 50 can be a command decoder 1 which may receive a command CMD from an external device such as a central processing unit (CPU). The command CMD may be input in synchronism with a clock signal CK. The clock signal CK can by a clock buffer 16 be generated. The clock buffer 16 may receive an external clock CLK and may generate the clock signal CK. The command CMD may be synchronized with the clock signal CK by the command decoder 1 be decoded. When a command CMD requests that a wordline be activated, the command decoder may 1 activate a control signal ACT / REF. The control signal ACT / REF may indicate that an activation command or a refresh command has been received, which are only two examples. A line control circuit 4 may receive the control signal ACT / REF and may generate a row enable signal RE. A gain control circuit 5 may receive the control signal ACT / REF and the row enable signal RE and may generate a gain control signal PREVBT. The gain control signal PREVBT may be a pulse having a predetermined delay relative to the activated control signal ACT / REF. The gain control signal PREVBT may be a single pulse having a predetermined pulse width.

A circuit for detecting an amplified potential 6 may receive the gain control signal PREVBT and an amplified potential VPP as input, and may amplify a span generate signal VBUP. The amplified voltage signal VBUP may have a released state when either the boost control signal PREVBT is active or the boosted potential VPP is below a predetermined potential. An oscillator circuit 7 may receive the amplified voltage signal VBUP and may generate an oscillation signal VBOS. An amplifier circuit 8th may receive an oscillation signal VBOS and the amplified voltage signal VBUP and may generate the amplified potential VPP. A smoothing capacitor Cd can receive the amplified potential VPP. The smoothing capacitor Cd may be used to provide an immediate charge to the circuit that can use the boosted potential VPP as a power supply. In this way voltages with peaks at the amplified potential VPP can be reduced.

The semiconductor memory device 50 can also have an address buffer 2 contain. The address buffer 2 may receive an address signal ADD and may input a row address to a word selection circuit 3 and / or a column address to a bit selection circuit 9 deliver. A memory field 10 may be wordlines (eg, a wordline 11 ), Bitlines (eg, a bitline 12 ) and memory cells (for example, a memory cell 13 ), which may be formed at the intersection of word lines and bit lines. That way the memory box can 10 a field of memory cells (such as the memory cell 13 ) contain.

The word selection circuit 3 For example, the row enable signal RE, a row address (from the address buffer 2 ) and the amplified potential VPP and may receive a word line (eg, the word line 11 ) based on the value of the received row address. In this way, the word selection circuit 3 the amplified potential VPP to a predetermined word line (for example, to the word line 11 ) deliver.

A sense amplifier 14 may be bitlines (such as the bitline 12 ) and can amplify received small signals. In this way, data from a row of memory cells (such as the memory cell 13 ) are detected. The bit selection circuit 9 may be a predetermined bit or group of bits based on a column address (from the address buffer 2 ) choose. An input / output (I / O) buffer 15 can data DATA between the sense amplifier 14 and external connections.

In this way, the data DATA can be synchronized with the clock signal CK from the memory array 10 read or written to him.

Now take reference 2 Fig. 10 is a schematic circuit diagram of a gain control circuit 5 shown according to an embodiment. The gain control circuit 5 may be the gain control circuit 5 in the in 1 illustrated semiconductor memory device 50 be.

The gain control circuit 5 may receive the control signal ACT / REF and the row enable signal RE and may generate the gain control signal PREVBT. The gain control circuit 5 may include an inverter IV1, transistors (transistor to Tr3), delay circuits (D1 to D3), NAND gates (NAND1 and NAND2) and a latch circuit L1.

Of the Inverter IV1 may receive the row enable signal RE at an input and may connect an output to a gate of the transistor Tr3 to have. The transistor Tr3 may have a source terminal with a Ground potential GND connected and a drain terminal with a Source of the Transistor Tr2 have connected. The transistor Tr2 may have a gate terminal for receiving the control signal ACT / REF connected and a drain terminal with a Have connected node N1. The transistor Tr1 may have a gate terminal for receiving the control signal ACT / REF connected, a source terminal with a Power supply VCC connected and a drain connection with the Have connected node N1. The transistors (Tr2 and Tr3) may be n-type field-effect transistors with insulated gate (IGFETs). The transistor Tr1 may be a p-type IGFET be.

The Latch circuit L1 can connect an input to node N1 to have. The latch circuit may include inverters (IV2 and IV3). Inverter IV2 may connect an input to node N1 and an output connected to an input of the inverter IV3 to have. Inverter IV3 may connect an output to node N1 to have. In this way, the latch circuit L1 can node N1 to prevent it from floating.

The delay circuit D1 can connect an input to node N1 and an output with an input of the NAND gate NAND1 and an input of the delay circuit D1 have connected. The delay circuit D1 can be an inverter chain with an odd number of levels contain. Thus, the delay circuit D1 a delayed and inverted output with respect to that received from node N1 Deliver signal.

The delay circuit D2 may be a Output connected to an input of the NAND gate NAND1. The delay circuit D2 may include an inverter chain having an odd number of stages. Thus, the delay circuit D2 can provide a delayed and inverted output with respect to the signal received from the delay circuit D1. The NAND gate NAND1 may have an output connected to an input of the NAND gate NAND2 and an input of the delay circuit D3. The delay circuit D3 may have an output connected to an input of the NAND gate NAND2. The delay circuit D3 may include an inverter chain having an even number of stages. Thus, the delay circuit D3 can provide a delayed output with respect to the signal received from the NAND gate NAND1. Element ratios, such as transistors, may be adjusted in the delay circuit D3 to provide a rising edge delay so that a falling edge of the received input signal may propagate through the delay circuit D3, but a rising edge may be delayed by a predetermined period of time. The NAND gate NAND2 may generate the gain control signal PREVBT at an output.

Now, the operation of the gain control circuit 5 explained.

At first For example, the control signal ACT / REF may be logically low and may Row enable signal RE logic low. Thus, the transistor Tr1 can be turned on and the node N1 through the transistor Tr1 be pulled up to logical. The delay circuit D1 may be a deliver a logically low output. Thus, the delay circuit D2 deliver a logically high output. With an input on logical low, the NAND gate NAND1 can be a logically high output to one Input of the NAND gate NAND2 supply. The delay circuit D3 may be a Logically high output to the other input of the NAND gate NAND2 deliver. With both inputs at the NAND gate NAND2 to logic high, the gain control signal PREVBT be logically low.

When the command decoder 1 ( 1 ) receives a command CMD indicating that a word line is to be activated, the control signal ACT / REF may go high. With the control signal ACT / REF at logic high and the row enable signal RE at logic low, the two transistors Tr2 and Tr3 can be turned on and the node N1 can be pulled low. The delay circuit D1 may provide a logic high output after a predetermined delay period. Because the output of the delay circuit D1 may still be logic high, the output of the NAND gate NAND1 may transition to logic low. With an input of the NAND gate NAND2 to logic low, the gain control signal PREVBT can transition to logic high. In this way, the delay circuit D1 can supply substantially the predetermined delay from the rising edge of the control signal ACT / REF to the rising edge of the boost control signal PREVBT.

Because the delay circuit D3 a predetermined delay only for may provide a rising edge, the output of the delay circuit D3 shortly after the NAND gate NAND1 has a logic low output delivers, logically low.

A predetermined delay (determined by the delay circuit D2) after the output of the delay circuit D1 goes high, can be the output of the delay circuit D2 go to logic low. Thus, the output of NAND gate NAND1 can go back to logical go over high. However, the gain control signal PREVBT, because the output of the delay circuit D3 is still open Logically low, stay at logical high. However, one can predetermined delay (determined by the delay circuit D3), after the output of the NAND gate NAND1 becomes logically high, the output of the delay circuit D3 logically high. With both inputs to the NAND gate NAND2 to logic high, the gain control signal PREVBT become logically low. In this way, the gain control signal have a pulse width substantially through the delay circuits (D2 and D3) is determined.

Consequently a predetermined delay (determined through the delay circuit D1) after the control signal ACT / REF transitions to logic high, the gain control signal PREVBT logically high. Then, a predetermined delay (determined by the sum of the delay circuits D1 and D2) later the gain control signal PREVBT return to logically low. In this way, the gain control signal PREVBT a delayed be a single pulse with a predetermined pulse width.

The delay circuit D2 and the NAND gate NAND1 can functionally form a positive pulse triggered single pulse with a negative pulse output. The delay circuit D3 and the NAND gate NAND2 may functionally comprise a pulse extension unit or a pulse extension unit form with a positive pulse output.

Short That is, the row enable signal RE after the control signal ACT / REF becomes logically high, becomes logically high. Thus, the transistor Tr3 are turned off. However, the logical state of the node can N1 be maintained by the latch circuit L1.

The Control signal ACT / REF may be a pulse. When the pulse width of the control signal ACT / REF is equal to or greater than the desired predetermined one Pulse width of the gain control signal PREVBT is, can the delay circuits (D2 and D3) are omitted.

Now take reference 3 13 is a schematic circuit diagram of the boosted potential detection circuit 6 shown according to an embodiment. The circuit for detecting an amplified potential 6 For example, the circuit for detecting an amplified potential 6 in the in 1 illustrated semiconductor memory device 50 be.

The circuit for detecting an amplified potential 6 may receive a reference potential Vref1, the boosted potential VPP, and the boost control signal PREVBT as inputs, and may provide an amplified voltage signal VBUP as an output.

The circuit for detecting an amplified potential 6 may include resistance devices (R1a and R1b), a comparator COM1 and an OR gate OR1. The resistance device R1a may have one terminal connected to the amplified potential VPP and another terminal having a terminal of the resistance device R1b at a resistance connection node. The resistance device R1b may have connected another terminal to the ground potential GND. The comparator COM1 may have one input connected to the resistance connection node and connected another terminal for receiving the reference potential Vref1. The reference potential Vref1 may be about 2.0V, which is only an example.

Of the Comparator COM1 may have an output to an input of the OR gate Deliver OR1. The OR gate OR1 may be the gain control signal PREVBT received at a further input and the amplified voltage signal VBUP produce.

Now, the operation of the boosted potential detection circuit will become 6 explained.

If the gain control signal PREVBT is high, the OR gate OR1 a logically high fortified one Supply voltage signal VBUP.

The Resistor devices (R1a and R1b) can be used as voltage dividers for Supplying a potential at an input of the comparator COM1 act, which can be proportional to the increased potential VPP. The resistance devices (R1a and R1b) can have resistance values of about 1000 have kΩ, which is just an example. In this way, that can be done at the entrance of the Comparator COM1 available Asked potential about equal to half of the potential of the amplified potential VPP be. If the amplified Potential VPP drops below 4.0 volts, the connection node of the resistance device (R1a and R1b) have a potential below 2.0 volts. The comparator COM1 can then provide a high output to an input of the OR gate OR1. Thus, the OR gate OR1 may be a logic high amplified voltage signal VBUP deliver. However, if the amplified potential VPP is above 4.0 Volts can, the connection node of the resistance devices (R1a and R1b) have a potential of over Have 2.0 volts. The comparator COM1 can then have a low output to an input of the OR gate OR1. In this condition can the amplified Voltage signal VBUP be logically low when the gain control signal PREVBT is also logically low.

Thus, the circuit for detecting a boosted potential 6 indicate whether the boosted potential VPP or a predetermined potential (about 4 volts, which is just one example) has dropped or whether a wordline is to be activated (the boost control signal PREVBT goes high). In this way, the circuit for detecting a boosted potential 6 indicate that more charge can be supplied to the amplified potential VPP.

Now take reference 4 Figure 13 is a schematic circuit diagram of an oscillator circuit 7 shown according to an embodiment. The oscillator circuit 7 can the oscillator circuit 7 in the in 1 illustrated semiconductor memory device 50 be.

The oscillator circuit 7 may receive the boosted voltage signal VBUP and a reference potential Vref, and may generate an oscillation signal VBOS. The oscillator circuit 7 may be an oscillation signal generator 7a , an oscillator presetting circuit 7b , an oscillator state latch circuit 7c and a driver circuit 7d contain.

The oscillation signal generator 7a Can In verter (IV11 and IV12), transistors (Tr11 and Tr37) and a transmission gate G1 included. The reference potential Vref may be supplied to gate terminals of the transistors (Tr11 and Tr12), respectively. The transistor Tr11 may have a source connected to the ground potential and may have a drain connected to a source of the transistor Tr12. The transistor Tr12 may have a drain connected to a drain of the transistors (Tr13 and Tr14) and a gate of the transistors (Tr13 to Tr20). The transistors Tr13 to Tr20 may each have a source connected to a power supply Vint. The power supply Vint may be, for example only, an internally generated power supply. The transistor Tr15 may have a drain connected to a drain of the transistors (Tr21 and Tr22) and gates of the transistors (Tr22 to Tr27). The transistors (Tr16 to Tr20) may each have a drain connected to a respective source of the transistors (Tr28 to Tr32). The transistors (Tr21 to Tr27) may each have a source connected to the ground potential. The transistors (Tr23 to Tr27) may each have a drain connected to a source of each of the transistors (Tr33 to Tr37). The inverter IV11 may receive the boosted voltage signal VBUP at an input and may provide an output to a gate of the transistor Tr21 and an input of the inverter IV12. The inverter IV12 may provide an output to a gate of the transistor Tr14.

The Transistors (Tr11, Tr12 and Tr21 to Tr27) may be n-type IGFETs. The Transistors (Tr13 to Tr20) can be p-type IGFETs.

The Transistors (Tr28 and Tr33) can in each case one control gate is connected to an output of the transmission gate G1 to have. The transistors Tr28 and Tr33) may be connected in common to drain terminals to have. The transistors (Tr29 and Tr34) may each have a control gate with drains of the transistors (Tr28 and Tr33). The transistors (Tr29 and Tr34), drain connections can be common have connected. The transistors (Tr30 and Tr35) can each a control gate with drains of the transistors (Tr29 and Tr34). The transistors (Tr30 and Tr35) drains have joined together. The transistors (Tr31 and Tr36) can one control gate with drain terminals of the transistors (Tr30 and Tr35). The transistors (Tr31 and Tr36) can share drain connections have connected. The transistors (Tr32 and Tr37) can each a control gate with drains of transistors (Tr31 and Tr36). The transistors (Tr32 and Tr37) drains have joined together at node N3. The transistors (Tr28 to Tr32) be p-type IGFETs. The transistors (Tr33 to Tr37) may be n-type IGFETs.

The transfer gate G1 may connect an input to drains of the transistors (Tr32 and Tr37) at node N3 and an output to the oscillator state latch 7c connected at node N4. The transmission gate G1 may include transistors (Tr61 and Tr62). The transistor Tr61 may connect a source / drain terminal to drains of the transistors (Tr32 and Tr37), another source / drain terminal to the oscillator state latch circuit 7c at the node N4 and a gate terminal may be turned on by the oscillator preset circuit 7b received signal received. The transistor Tr62 may connect a source / drain terminal to drains of the transistors (Tr32 and Tr37), another source / drain terminal to the oscillator state latch circuit 7c at the node N4 and a gate terminal may be turned on by the oscillator preset circuit 7b received signal received. The transistor Tr61 may be a p-type IGFET. The transistor Tr62 may be an n-type IGFET.

The oscillator presetting circuit 7b may include inverters (IV13 and IV14) and transistors (Tr41 to Tr60). The inverter IV13 may receive the boosted voltage signal VBUP at an input and may provide an output to an input of the inverter IV14 and a gate of the transistors (Tr46 to Tr50, Tr64 and Tr61). The inverter IV14 may provide an output to a gate of the transistors (Tr41 to Tr45, Tr63 and Tr62). The transistors (Tr41 to Tr45) may each have a source connected to the power supply Vint and may each have a drain connected to a respective source of the transistors (Tr51 to Tr55). The transistors (Tr46 to Tr50) may each have a source connected to the ground potential and may each have a drain connected to a respective source of the transistors (Tr56 to Tr60). The transistors (Tr51 and Tr56) may have a gate connected to the node N4 and may have drain terminals connected in common to the gates of the transistors (Tr52 and Tr57). The transistors (Tr52 and Tr57) may have common drain terminals connected to the gates of the transistors (Tr53 and Tr58). The transistors (Tr53 and Tr58) may have common drain terminals connected to the gates of the transistors (Tr54 and Tr59). The transistors (Tr54 and Tr59) can share drain connections to the Gate terminals of the transistors (Tr55 and Tr60) have connected. The transistors (Tr55 and Tr60) may have common drain terminals connected to the node N3. The transistors (Tr41 to Tr45 and Tr51 to Tr55) may be p-type IGFETs. The transistors (Tr46 to Tr50 and Tr56 to Tr60) may be n-type IGFETs.

In addition, the transistors (TR51 and Tr56) of the oscillator preset circuit 7b For example, drain terminals may be common to the drains of the transistors (Tr28 and Tr33) of the oscillation signal generator 7a have connected. The transistors (Tr52 and Tr57) of the oscillator preset circuit 7b For example, drain terminals may be common to the drains of the transistors (Tr29 and Tr34) of the oscillation signal generator 7a have connected. The transistors (Tr53 and Tr58) of the oscillator presetting circuit 7b For example, drain terminals may be common to the drains of the transistors (Tr30 and Tr35) of the oscillation signal generator 7a to have closed. The transistors (Tr54 and Tr59) of the oscillator presetting circuit 7b For example, drains may be connected in common to the drains of the transistors (Tr31 and Tr36) of the oscillation signal generator 7a have connected. The transistors (Tr55 and Tr60) of the oscillator presetting circuit 7b For example, drain terminals may be common to the drains of the transistors (Tr32 and Tr37) of the oscillation signal generator 7a have connected.

The oscillator state latch circuit 7c may include an inverter IV15 and transistors (Tr63 to Tr66). Inverter IV15 may have an input connected to node N4 and an output connected to a gate of transistors (Tr65 and Tr66). The transistor Tr63 may have a source connected to the power supply Vint and a drain connected to a source of the transistor Tr65. The transistor Tr64 may have a source connected to the ground potential and may have a drain connected to a source of the transistor Tr66. The transistors (Tr65 and Tr66) may have common drain terminals connected to node N4. The transistors (Tr63 and Tr65) may be p-type IGFETs. The transistors (Tr64 and Tr66) may be n-type IGFETs.

The driver circuit 7b may include inverter (IV16 and IV17). The inverter IV16 may have an input connected to an output of the inverter IV15 and an output connected to an input of the inverter IV17. The inverter IV17 may generate an oscillation signal VBOS at an output.

Now the operation of the oscillator circuit 7 described.

The oscillation signal generator 7a may form a ring oscillator in which an odd number of inverters may be arranged in a ring. The transistors (Tr28 and Tr33) can form an inverter. The transistors (Tr29 and Tr34) may form an inverter. The transistors (Tr30 and Tr35) can form an inverter. The transistors (Tr31 and Tr36) may form an inverter. The transistors (Tr32 and Tr37) may form an inverter. When the transmission gate G1 is enabled (conducting), the oscillation signal generator 7a be a ring oscillator with five inverter stages connected in a ring, and can provide an oscillation output at node N4.

Within the oscillation signal generator 7a For example, the transistors (Tr11 to Tr13 and Tr15 to Tr20 and Tr22 to Tr27) may be a current source for the ring oscillating part of the oscillation signal generator 7a provide. The reference potential Vref may be used to adjust the amount of current supplied. Thus, the reference potential Vref can be used to set the frequency of oscillation of the ring oscillator part. The reference potential Vref may be supplied to gate terminals of the transistors (Tr11 and Tr12). This can adjust the current flowing through the diode-connected transistor Tr13. The transistors (Tr15 to Tr20) may each form current mirror type configurations and thus may have a current which (depending on device sizes) may be proportional to the current flowing through the transistor Tr13. The current flowing through the transistor Tr15 may also flow through the transistor Tr22 in diode configuration. The transistors (Tr23 to Tr27) may each form current mirror type configurations and thus may have a current which (depending on device sizes) may be proportional to the current flowing through the transistor Tr22.

The transistors (Tr14 and Tr21) can be considered as blocking devices. When the transistor Tr14 is turned on, gates of the transistors (Tr13 and Tr15 to Tr20) can be pulled high. Thus, the transistors (Tr13 and Tr15 to Tr20) can be turned off, and a current can flow in the ring oscillator part of the oscillation signal generator 7a be interrupted or disturbed. Similarly, when the transistor Tr21 is turned on, gate terminals of the transistors (Tr22 to Tr27) can be pulled low. Thus, the transistors (Tr22 to Tr27) can be turned off, and a current flow can in the ring oscillator part of the oscillation signal generator 7a be disturbed. By disturbing or interrupting a current flow in the oscillation signal generator 7a For example, power consumption can be reduced and power consumption of the entire chip can be reduced.

When the boosted voltage signal VBUP is at logic high, the oscillation signal generator 7a can be enabled and it can provide an oscillation signal at node N4. When the boosted voltage signal VBUP is at logic low, the oscillation signal generator 7a be locked.

When the boosted voltage signal VBUP is logic low, the oscillator preset circuit may 7b Transistors (Tr41 to Tr50) that can be turned on. Thus, three-state inverters formed by the transistors (Tr41 to Tr60) can be enabled. The first inverter input (gates of transistors Tr51 and Tr56) may receive a logic level from node N4 (which may be latched). After propagating through the series-connected five three-state inverters formed by the transistors (Tr41 to Tr60), a logic level opposite to node N4 can be applied to node N3. In this way, the oscillator presetting circuit 7b provide a logical state at node N3 which is the opposite of the logic state at node N4.

In addition, each of the within the oscillator preset circuit 7b Three-state inverter formed the outputs of all the inverters that make up the ring oscillator of the oscillation signal generator 7a form to the last logical state at which the oscillation signal generator 7a has been released, set opposite logical states.

If the reinforced Voltage signal VBUP is logic low, the transmission gate G1 be locked.

When the boosted voltage signal VBUP is logic low, the oscillator state latch circuit may 7c can be released and can latch a logic level at node N4. When the boosted voltage signal VBUP is logic low, the transistors (Tr63 and Tr64) can be turned on. Thus, the inverter IV15 and the transistors (Tr63 to Tr66) can operate as a flip-flop type latch circuit and can latch a logic level at the node N4.

The driver circuit 7d can by the oscillator state latch circuit 7c latched logic level and can generate the oscillation signal VBOS.

When the amplified voltage signal VBUP transitions to logic high, the oscillation signal generator 7a be released. The oscillator state latch circuit 7c can be turned off (transistors Tr63 and Tr64 can be turned off). The transmission gate G1 can be turned on, and the logic level opposite to the node N4, which is applied to the node N3, can be applied to the node N4. In this way, the oscillation signal VBOS can only be a short period of time after the oscillator circuit 7 a high falling edge of the amplified voltage signal VBUP receives change.

The oscillator presetting circuit 7b may provide a predetermined delay for changing the logic level of node N3 when the boosted voltage signal transitions to a logic low. This can eliminate unwanted defects in the oscillation signal VBOS when the boosted voltage signal VBOS transitions in the logic state.

Next, the operation of the semiconductor memory device 50 with reference to the 1 to 6 described.

Now take reference 5 13, there is shown a timing diagram illustrating the operation of the gain control circuit 5 represents.

The time diagram of the 5 may include the control signal ACT / REF, the row enable signal RE and the gain control signal PREVBT.

When the command decoder 1 ( 1 ) receives a command indicating that a word line is to be activated, the control signal ACT / REF may be a pulse which is at the high level. This state can be represented at time t1. This high-going edge of the control signal ACT / REF can be controlled by the gain control circuit 5 ( 2 ) are received at the gate terminals of the transistors (Tr1 and Tr2), which can turn on the transistor Tr2. Because the row enable signal RE is low at time t1 ( 5 ), the transistor Tr3 can also be turned on and the node N1 can be pulled low. After a predetermined delay provided by the delay circuit D1, the input to the NAND gate NAND1 may go high, and the NAND gate NAND1 may supply a low output to the NAND gate NAND2. Thus, the gain control signal PREVBT may transition to high after a delay from T1. In this way, the delay T1 can be determined substantially by the delay circuit D1.

Because the delay circuit D3 a vor may provide certain delay for only a rising edge, the output of the delay circuit D3 may become logic low shortly after the NAND gate NAND1 provides a logic low output.

A predetermined delay (determined by the delay circuit D2) after the output of the delay circuit D1 goes high, can be the output of the delay circuit D2 go to logic low. Thus, the output of NAND gate NAND1 can go back to logical go over high. However, because the output of the delay circuit D3 is still open is logic low, the gain control signal PREVBT stay logically high. A predetermined delay (determined by the delay circuit D3), after the output of the NAND gate NAND1 becomes logically high, can be the output of the delay circuit D3 logically high. With both inputs to the NAND gate NAND2 to logic high, the gain control signal PREVBT logically low. In this way, the gain control signal can be a Pulse width, which essentially by the delay circuits (D2 and D3) is determined.

Consequently can after a delay from T2 (at a time t3), essentially through the delay circuits (D2 and D3) may be determined, the gain control signal PREVBT return to low. The time delays T1 and T2 can by adjusting the delays the delay circuits (D1 to D3) according to a desired one Charge transfer to reinforced Potential VPP be set when a word line is activated can be.

The row enable signal RE may transition to logic high after a time t1. However, the latch circuit L1 (FIG. 2 ) keep node N1 at the logic low until the control signal ACT / REF returns to low. In this way, the node N1 can be prevented from being in the floating state.

After a time t3, the instruction decoder may 1 ( 1 ) receive another command indicating that a wordline is to be activated. However, a wordline can not be activated until the row enable signal RE returns to low and the memory array 10 ( 1 ) has been summoned. Thus, the gain control signal PREVBT can not be generated. As indicated, the transistor Tr3 ( 2 ) when the row enable signal RE is high, are turned off.

Now take reference 6 13, there is shown a timing diagram illustrating the amplification operation according to one embodiment.

The time diagram of the 6 For example, the control signal ACT / REF, the gain control signal PREVBT, an output of the comparator circuit COM1 (FIG. 3 ), the boosted voltage signal VBUP, the oscillation signal VBOS, the boosted potential VPP and the potential of the word line 11 of the ( 1 ) contain.

During normal operation of the circuit for an amplified potential 6 ( 3 ), the gain control signal PREVBT may be low. The circuit for an amplified potential 6 may generate an amplified voltage signal VBUP when the comparator COM1 indicates that the amplified potential VPP has dropped below about 4.0V. This can be indicated by the fact that the output of the comparator COM1 becomes high. As it is in 6 at a time t1, the boosted potential VPP may drop below 4.0V. This may cause the output of the comparator circuit COM1 to go high, causing the boosted voltage signal VBUP to go high.

The oscillation circuit 7 ( 4 ) can receive the logic high amplified voltage signal VBUP. This may cause the oscillation signal generator 7a an oscillation begins. As stated earlier, the current state of the oscillation signal VBOS can be detected by the oscillator state latch circuit 7c cached. The oscillator presetting circuit 7b may have received the current state of the oscillation signal VBOS by means of the node N4 and may be the oscillation signal generator 7a have been preset in such a way that the opposite logical state may have been established at node N3. In this way, the oscillation signal VBOS can make a logical transition shortly after the amplified voltage signal VBUP becomes active (logic high). This can occur with a delay of ΔT1 after a time t1 in 6 be displayed. In this way, the amplifier circuit 8th ( 1 ) rapidly deliver a charge to the amplified potential VPP. The oscillation signal VBOS can subsequently be at a by the oscillation signal generator 7a certain frequency oscillate. This frequency can be adjusted by modifying the potential level of the reference potential Vref.

The oscillation signal VBOS may continue to oscillate until the amplifier circuit 8th ( 1 ) amplifies the amplified potential VPP to a potential above about 4.0V. The circuit for detecting an amplified potential 6 can provide an output of the comparator COM1, which can logically become low, and the amplified voltage signal VBUP can become logically low.

You still take it on 6 Reference, the control signal ACT / REF may be a high pulse at time t2. This may indicate that the instruction decoder 1 ( 1 ) has received a command in which a word line can be activated. With a time delay which is essentially determined by the delay circuit D1 ( 2 ) can be determined after time t1, the gain control signal PREVBT may become high. The circuit for detecting an amplified potential 6 may receive the gain control signal PREVBT and may generate a logic high boosted voltage signal VBUP. The oscillator circuit 7 can receive the logic high amplified voltage signal VBUP. As indicated earlier, the oscillator state latch circuit 7c have latched a logic state of the oscillation signal VBOS by latching a logic state at node N4. The oscillator presetting circuit 7b may have delivered an opposite state to node N3. This may enable the oscillation signal VBOS shortly after receiving a released (logic high) boosted voltage signal VBUP to change a logic level. In this way, the amplifier circuit 8th ( 1 ) rapidly deliver a charge to the amplified potential VPP.

At a time t3, the word line can 11 ( 1 ) increase. This may place a burden on the boosted potential VPP. Due to the charge loss from the smoothing capacitor Cd ( 1 ), the amplified potential VPP may drop below about 4.0V. The circuit for detecting an amplified potential 6 ( 3 ) can provide an output of the comparator COM1, which can become logic high. This can keep the boosted voltage signal VBUP high even after the boost control signal PREVBT returns to low. This can be the oscillator circuit 7 keep released and the amplifier circuit 8th may further supply a charge to the boosted potential VPP. A time delay ΔT2 after the time t3 may become the boosted potential VPP and the word line potential Vw over about 4.0V. Thus, the output of the comparator COM1 and the amplified voltage signal may become low. This can be the Oszilla gate circuit 7 lock and the amplifier circuit 8th may stop supplying a charge to the boosted potential VPP.

The oscillator state latch circuit 7c can latch the logic state of the oscillation signal VBOS and the oscillator preset circuit 7b can the oscillator circuit 7 to quickly change the logic state of the oscillation signal VBOS when the boosted voltage signal VBUP returns to high.

The embodiments can allow that increased Potential VPP receives a charge, before a charge-consuming event receives a charge from a smoothing capacitor Cd can deplete. This can allow the increased potential VPP to maintain a predetermined potential better.

Now take reference 7 12, there is shown a schematic circuit diagram of a boosted potential detection circuit according to an embodiment, and is the general reference numeral 60 allocated. The circuit for detecting an amplified potential 60 can be considered as the circuit for detecting a boosted potential 6 in the in 1 illustrated semiconductor memory device 50 be used.

The circuit for detecting an amplified potential 60 may receive as inputs a reference potential Vref1, an amplified potential VPP and a gain control signal PREVBT and may provide an amplified voltage signal VBUP as an output.

The circuit for detecting an amplified potential 60 may include resistance devices (R1a, R1b, R2 and R3), inverters (IV4 and IV5), transistors (Tr4 and Tr5) and a comparator COM1. The resistance device R1a may have one terminal connected to the amplified potential VPP and another terminal connected to a terminal of the resistance device R1b at a resistance connection node. The resistance device R1b may have connected another terminal to the ground potential GND. The resistance device R2 may have one terminal connected to the amplified potential VPP and another terminal connected to a terminal of the resistance device at a resistance connection node. The resistance device R3 may have another terminal connected to the ground potential GND. The transistor Tr4 may have a source / drain connected to the resistor connection node of the resistors (R1a and R1b) and another source / drain connected to an input of the comparator COM1. The transistor Tr5 may have a source / drain connected to a resistor connection node of the resistors (R2 and R3) and another source / drain connected to an input of the comparator COM1. The comparator COM1 may have another input connected to receive the reference potential Vref1. The reference potential Vref1 may be about 2.0 V, for example only. The comparator COM1 may provide the boosted voltage signal VBUP as output.

Of the Inverter IV4 may be the gain control signal PREVBT received at an input and can output to a gate of the transistor Tr4 and an input of the inverter IV5 deliver. The inverter IV5 may provide an output to a gate of the transistor Tr5.

Now, the operation of the boosted potential detection circuit will become 60 explained.

The Resistance devices (R1a and R1b) can act as voltage dividers by a potential at its respective resistor connection node which can be proportional to the amplified potential VPP. The resistance devices (R1a and R1b) can, for example only, be resistance values of about 1000 kΩ. On this can be done at their respective resistor connection node provided potential approximately equal to one half of the potential of the amplified potential Be VPP. The resistance devices (R2 and R3) can be used as Voltage dividers act to apply a potential at their respective resistor connection node which can be proportional to the amplified potential VPP. The resistance device R2 may, for example only, have a resistance value of about 1048 kΩ. The resistance device R3 may, for example only, have a resistance value of about 952 kΩ. In this way, this can be done at their respective resistor connection node supplied potential about equal to or less than half of the Potential of the amplified Potential VPP.

If the gain control signal PREVBT is low, the transistor Tr4 can be turned on and the transistor Tr5 can be turned off.

Consequently For example, the connection node of the resistance devices (R1a and R1b) are electrically connected to the input of the comparator COM1. If the amplified Potential VPP drops below about 4.0 volts, the connection node may the resistance devices (R1a and R1b) have a potential below about Have 2.0 volts. The comparator COM1 can then have a high output to the amplified voltage signal VBUP deliver. However, if the amplified potential VPP exceeds about 4.0 volts, the connection node of the resistance devices (R1a and R1b) a potential over about 2.0 volts. The comparator COM1 can then be a low Issue to the fortified Supply voltage signal.

If the gain control signal PREVBT is high, the transistor Tr4 can be turned on and the transistor Tr5 can be switched off. Thus, the connection node the resistance devices R2 and R3 are electrically connected to the input of the comparator COM1. When the amplified potential VPP drops below a predetermined potential, the connection node the resistance devices (R2 and R3) have a potential below about Have 2.0 volts. Because the resistance values of the resistance devices (R2 and R3) selected can be to a potential at the connection node of the resistance devices (R2 and R3), which is greater than the half of VPP, the comparator COM1 can then have a high output to reinforced Voltage signal VBUP deliver when the amplified potential below a predetermined Potential drops, the bigger than can be about 4.0 volts. However, then, if the amplified potential VPP over is the predetermined potential, the connection node of Resistance devices (R1a and R1b) have a potential greater than about Have 2.0 volts. The comparator COM1 can then output a low output increased Supply voltage signal VBUP.

In this way, when the boost control signal PREVBT is high, the boosted potential detection circuit can be provided 60 to control the boosted potential VPP to ensure a predetermined potential that may be high enough to supply a sufficient charge to a wordline that can be selected. The predetermined potential can be determined by the ratio of resistance values of the resistors (R2 and R3). The predetermined potential may be determined by the equation VPP≅Vref1 ((R2 + R3) / R3), where Vref1 is the potential of the reference potential Vref1, R2 is the resistance of the resistor R2, and R3 is the resistance of the resistor R3. If R2 ≅ 952 kΩ, R3 ≅ 1048 kΩ, and Vref1 ≅ 2.0 volts, then the predetermined potential of the boosted potential, when the control signal PREVBT is high, may be about 4.2 volts.

Now take reference 8th 13, there is shown a timing diagram illustrating the boost operation according to an embodiment using the boosted potential detection circuit 60 represents.

The time diagram of the 8th For example, a control signal ACT / REF, a gain control signal PREVBT, an output of the comparator circuit COM1 (FIG. 7 ), an amplified voltage signal VBUP, an oscillation signal VBOS, an amplified potential VPP, and a potential of the word line 11 ( 1 ) contain.

During normal operation of the boosted potential detection circuit 60 ( 7 ), the gain control signal PREVBT may be low. In this case, the cons state connection node of the resistors (R1a and R1b) to be electrically connected to an input of the comparator COM1. The circuit for an amplified potential 60 may generate an amplified voltage signal VBUP when the comparator COM1 indicates that the amplified potential VPP has dropped below about 4.0V. This can be indicated by the fact that the output of the comparator COM1 becomes high. As it is in 8th at time t1, the amplified potential VPP may drop below 4.0V. This may cause the output of the comparator circuit COM1 to go high, causing the boosted voltage signal VBUP to go high.

The oscillator circuit 7 ( 4 ) can receive the logic high amplified voltage signal VBUP. This may cause the oscillation signal generator 7a an oscillation begins. As stated earlier, the current state of the oscillation signal VBOS can be detected by the oscillator state latch circuit 7c cached. The oscillator presetting circuit 7b may have received the current state of the oscillation signal VBOS by means of the node N4 and may be the oscillation signal generator 7a have been preset in such a way that the opposite logical state may have been set at node N3. In this way, the oscillation signal VBOS can make a logical transition shortly after the amplified voltage signal VBUP becomes active (logic high). This can occur with a delay of ΔT3 after the time t1 in 6 be displayed. In this way, the amplifier circuit 8th ( 1 ) rapidly deliver a charge to the amplified potential VPP. The oscillation signal VBOS may subsequently oscillate at a frequency determined by the oscillation signal generator 7a is determined. This frequency can be adjusted by modifying the potential level of the reference potential Vref. The oscillation signal VBOS may continue to oscillate until the amplifier circuit 8th ( 1 ) amplifies the amplified potential VPP to a potential above about 4.0V. Then, the circuit for detecting a boosted potential 60 provide an output of the comparator COM1, which may become logic low, and the boosted voltage signal VBUP may become logic low.

If you still refer to 8th At time t2, the control signal ACT / REF may be a high pulse. This may indicate that the instruction decoder 1 ( 1 ) has received a command in which a word line can be activated. With a time delay which is essentially determined by the delay circuit D1 ( 2 ), after a time t1, the gain control signal PREVBT may become high. The circuit for detecting an amplified potential 60 may receive the gain control signal PREVBT. In this case, the resistance connection node of the resistors (R2 and R3) may be electrically connected to an input of the comparator COM1. The circuit for an amplified potential 60 may generate an amplified voltage signal VBUP when the comparator COM1 indicates that the boosted potential VPP has dropped below a predetermined potential of about 4.2V. This can be indicated by the fact that the output of the comparator COM1 becomes high. As it is in 8th can be seen, after the time t2, the amplified potential VPP can be below about 4.2V. This may cause the output of the comparator circuit COM1 to go high, causing the boosted voltage signal VBUP to go high.

The oscillator circuit 7 ( 4 ) can receive the logic high amplified voltage signal VBUP. This may cause the oscillation signal generator 7a an oscillation begins. As stated earlier, the current state of the oscillation signal VBOS can be detected by the oscillator state latch circuit 7c cached. The oscillator presetting circuit 7b may have received the current state of the oscillation signal VBOS by means of the node N4 and may be the oscillation signal generator 7a have been preset in such a way that the opposite logical state may have been set at node N3. In this way, the oscillation signal VBOS can make a logical transition shortly after the amplified voltage signal VBUP becomes active (logic high). This can occur at a delay after time t2 in 8th be displayed. In this way, the amplifier circuit 8th ( 1 ) rapidly deliver a charge to the amplified potential VPP. The oscillation signal VBOS may subsequently oscillate at a frequency determined by the oscillation signal generator 7a is determined. This frequency can be adjusted by modifying the potential level of the reference potential Vref. The oscillation signal VBOS may continue to oscillate until the amplifier circuit 8th ( 1 ) amplifies the amplified potential VPP to a potential above about 4.2V. Then, the circuit for detecting a boosted potential 60 provide an output of the comparator COM1, which may become logic low, and the boosted voltage signal VBUP may become logic low.

At time t3, the word line can 11 ( 1 ) increase. This may place a burden on the boosted potential VPP. Due to the charge loss from the smoothing capacitor Cd ( 1 ), the amplified potential VPP may drop below about 4.0V. The circuit for detecting an amplified potential 60 ( 3 ) can provide an output of the comparator COM1, which can remain logically high. This can keep the boosted voltage signal VBUP high even after the boost control signal PREVBT returns to low. This can be the oscillator circuit 7 keep released and the amplifier circuit 8th may proceed with supplying a charge to the boosted potential VPP. A time delay ΔT4 after the time t3 may become the boosted potential VPP and the word line potential Vw over about 4.0V. Thus, an output of the comparator COM1 and the amplified voltage signal may become low. This can be the oscillator circuit 7 lock and the amplifier circuit 8th may stop supplying a charge to the boosted potential VPP.

The oscillator state latch circuit 7c can latch the logic state of the oscillation signal VBOS and the oscillator preset circuit 7b can the oscillator circuit 7 to quickly change the logic state of the oscillation signal VBOS when the boosted voltage signal VBUP returns high.

The embodiments can allow that increased Potential VPP receives a charge, before a charge-consuming event receives a charge from the smoothing capacitor Cd can deplete. This can allow an increased potential VPP to maintain a predetermined potential better.

Thus, the circuit for detecting a boosted potential 60 indicate whether the boosted potential VPP has dropped below a predetermined potential (about 4 volts when the boost control signal is logic low, which is only an example) or whether to enable a word line (the boost control signal PREVBT goes high), and the boosted potential detection circuit 60 may indicate whether the amplified potential VPP has dropped below a higher predetermined potential (about 4.2 volts, which is just one example). In this way, the circuit for detecting a boosted potential 60 indicate that more charge can be supplied to the amplified potential VPP.

The increased Potential VPP can be boosted before a load (such as selecting a word line) the reinforced Potential VPP exercised becomes.

It it should be noted that the higher predetermined potential of the amplified Potential VPP, for example, has been assigned such that it is about 4.2 volts. The higher one predetermined potential should not be limited to this value. When the predetermined potential of the boosted potential VPP increases to is set low Problems occur that are similar the conventional one Approach are. When the predetermined potential of the boosted potential VPP is set too high, the memory cell transistor suffer from a breakthrough due to a voltage. As such can resistance values the resistance devices (R2 and R3) are selected accordingly.

A semiconductor memory device 50 may include a boosted potential detection circuit, selectively as either a boosted potential detection circuit 6 or a circuit for detecting a boosted potential 60 can work. In this case, when a boosted potential detection circuit is desired, the gate of the transistor Tr5 (FIG. 7 ), and the gate of the transistor Tr4 can be set to a high potential. This can be done through options such as metallic options, fuses or bonding options, which are just a few examples. However, if a circuit for detecting a boosted potential 60 is desired, the input to the OR gate OR1 (FIG. 3 ) and the transistors (Tr4 and Tr5) can have gate terminals connected as shown in 7 is shown.

As described above, a potential higher than that required for a word line selection may be supplied in advance by previously amplifying a boosted potential VPP before the word line selection. This can reduce the adverse effects of charge depletion from a smoothing capacitor Cd, which can store a charge for the boosted potential VPP, and can reduce the operating speeds of a semiconductor memory device 50 improve. This may also allow a reduced size of a smoothing capacitor Cd and may reduce a chip size.

Claims (11)

A semiconductor memory device comprising: a memory cell array ( 10 ) with a plurality of word lines ( 11 ); a word selection circuit ( 3 ) activating one of the plurality of word lines based on the value of an address; a circuit ( 5 - 8th ) for generating an amplified potential which is connected to the word selection circuit ( 3 ), the boosted potential generating circuit applying an amplified potential to the word selection circuit (10). 3 ), when the word line is to be activated, characterized in that the circuit ( 5 - 8th ) to generate a boosted potential an instruction to activate a word line ( 11 ) and supplies a higher potential than a first fixed potential before the word line ( 11 ) was activated. A semiconductor memory device according to claim 1, wherein: said command to activate a word line ( 11 ) is a read command or a write command. A semiconductor memory device according to claim 1, wherein: said command to activate a word line ( 11 ) is a refresh command. A semiconductor memory device according to any one of claims 1 to 3, wherein said boosted potential generating circuit includes: an oscillation circuit ( 7 ) coupled to generate an oscillation signal; an amplifier circuit ( 8th ) coupled to provide a boost to the boosted potential in response to the oscillation signal; a gain control circuit ( 5 ) coupled to provide a single gain control signal indicating that the wordline is to be activated; and a circuit ( 6 ) for detecting an amplified potential coupled to receive the single gain control signal and to provide a boosted voltage signal having an oscillator enable state and an oscillator off state. A semiconductor memory device according to claim 4, wherein: the amplified voltage signal has the oscillator enable state when the single gain control signal (PREVBT) indicates that the word line ( 11 ) is to be activated; and the amplified voltage signal has the oscillator enable state when the amplified potential is lower than a predetermined potential. A semiconductor memory device according to claim 4, wherein: the increased Voltage signal has the oscillator enable state when the amplified potential lower than a first predetermined potential is when the single one Gain control signal (PREVBT) does not indicate that the wordline is to be activated; the increased Voltage signal has the oscillator enable state when the amplified potential is lower than a second predetermined potential, if that single gain control signal indicates that the wordline is to be activated; and the second predetermined potential greater than the first predetermined potential is. A semiconductor memory device according to claim 4, 5 or 6, wherein: said oscillator circuit ( 7 ) includes an oscillation signal generator and an oscillator preset circuit; the oscillation signal generator ( 7a ) oscillates when the amplified voltage signal is in the oscillator enable state; and the oscillator presetting circuit ( 7b ) the oscillation signal generator ( 7a ) to a last logical state in which the oscillation signal generator ( 7a ), sets the opposite state when the amplified voltage signal is in the oscillator locked state. Control method for controlling a semiconductor memory device with an amplifier circuit, the a reinforced one Potential in response to a generated by an oscillator circuit Generated oscillation signal, the method comprising the following steps: Receive a command and an address; Decoding the command; Produce a gain control signal (PREVBT) in response to the decoded instruction indicating that a wordline is to be activated; Delivering a charge to a node of a increased Potential (VPP) in response to the gain control signal; and Deliver an electrical connection between the node of the amplified potential and the word line according to the value the received address, characterized in that the step for supplying a charge to the node of the boosted potential, an amplified potential delivers that larger than is an activation potential of the word line. A control method according to claim 8, wherein: of the Step of generating a gain control signal (PREVBT) contains generating a single pulse. A control method according to claim 8, wherein: of the Step of providing a charge to the node of the boosted potential generating the oscillation signal in response to the gain control signal (PREVBT) contains; and the oscillation signal has an oscillation signal period between transitions. The control method of claim 10, wherein: generating an oscillation signal in response to the gain control signal includes generating an oscillation control signal in response to the gain control signal; and the oscillation signal has a last oscillation state when the oscillation control signal is in an oscillation inhibited state, and the oscillation signal transitions to a state opposite to the last oscillation state when the oscillation control signal transits to an oscillation enable state without being caused by the oscillation signal period between transitions is delayed.