DE10129012C1 - Developing electrostatic discharge protection elements by component simulation involves designing voltage/current characteristic by computer simulation so elements fire homogeneously - Google Patents

Abstract

The method involves designing the voltage/current characteristic of the electrostatic discharge protection elements by computer simulation so that the elements fire homogeneously and so electrostatic discharge protection elements only fail at high current. The doping profile is entered in a first step layout parameters and/or the doping profile is/are varied in a further step. Independent claims are also included for the following: an IC with electrostatic discharge protection elements.

Description

The invention relates to a method for developing ESD Protective elements according to the preamble of claim 1.

Electronic components are both during manufacture as well as high electrical loads in use exposed. In particular, electrostatic Discharges ESD (Electrostatic Discharge) for the corresponding products are becoming increasingly larger Security and reliability risk. Especially in safety-critical applications, such as in Automotive or smart card area, are highly effective Protective measures on the components required.

One way to increase the ESD security of ICs are ESD protection elements that work together with the rest of the circuit be implemented on silicon. As ESD protection elements in particular transistors (MOS or bipolar), Thyristors or diodes are used.

The protective behavior of ESD protective elements has so far examined using test chips on which a variety of test structures (ESD protection elements) that were based on of empirical values, but often also designed purely empirically were. The test structures were regarding the Technology (doping profiles) or the layout slightly different, so that after performing an ESD test the most robust or suitable ESD protection elements selected could become.

This test procedure is relatively reliable, but is on the other side with a very high expenditure of time - a Test chip cycle lasts from the design of the structures to  first evaluable chip about a year - and high costs - for development, implementation and analysis - connected. Due to the ever shorter development times for IC Components can only be used in ESD test structures today be developed and analyzed to a limited extent before they used in (pilot) products.

Due to the large number of adjustable process parameters and the almost unlimited variation of the individual Parameters would have to develop enormous amounts of test structures and evaluated to achieve optimal results.

Because of the strong dependence of ESD protection behavior on It is neither the manufacturing process of the ESD protection elements possible to use ESD protection concepts from a previous technology still take on the effects of process changes to predict an existing ESD concept.

Under these circumstances it becomes clear that one on the Evaluation of ESD test structures based ESD optimization is only possible with great effort. Both the multitude of Process parameters as well as the long time required for you Test cycles allow targeted ESD optimization Evaluation of ESD test structures no longer applies today.

It is therefore the object of the present invention To create procedures with respect to function and layout (Space requirement) optimized ESD protection elements in simple Way can be developed.

The object of the invention is achieved by the Claim 1 specified features. Further Embodiments of the invention are the subject of Dependent claims.

The main idea of the invention is that the U / I- Characteristic curve of ESD protection elements, such as MOS  or bipolar transistors, thyristors or diodes, by means of Computer simulation designed so that several of the ESD Protection elements when a certain limit is exceeded Ignite threshold voltage homogeneously without being destroyed become.

Usually several ESD protection elements are parallel arranged to each other, on which the discharge current divides. In this context, "homogeneous ignition" means that several, preferably all, ESD protective elements, into the conductive state simultaneously or in quick succession pass over and derive the overload. This process is supposed to be reversible, d. H. without damaging or destroying the ESD protection elements expire.

There are numerous advantages to using component simulation:

• - An optimization of the ESD robustness is already in one very early stage of technology development without that Evaluation of test structures on silicon possible. The is complex production and analysis of test structures so no longer necessary.
• - The ESD protection circuits can also with regard to Area to be optimized.
• - The simulation approach shortens the Development time dramatically and reduces the effort for Layout and measurements significantly.
• - The ESD component simulation can also be used for one more targeted selection of test structures can be used. Especially with new protective elements, where z. Legs large number of layout parameters can be varied, must have a certain selection before the test chip layout have been carried out. This targeted selection saves  again valuable test chip space and considerable Analysis effort.
• - With the help of ESD component simulation Effects of process changes (various Doping profiles) can be analyzed on the screen.

In the computer simulation, the components are individually or simulated in groups, initially in a first step set the doping profile of the protective elements, and then in a second step different layout parameters varied become. Under the term "layout parameters" in this Context refers to parameters that define the spatial Arrangement or expansion of various elements of an ESD Specify protection element, d. H. Parameters such as the gate length, base width, the distance between the gate and Source contact or gate and drain contact, etc.

The use of computer simulation in together Hang with an ESD protection circuit is off known from EP 0 335 965 B1.

Varying the layouts in turn influences ESD-relevant parameters of the U / I characteristic. ESD-relevant parameters of the U / I characteristic are in particular the breakdown voltage Vbd, the trigger voltage Vt1, the holding voltage Vsp and the differential high current resistance Rdiff (cf. FIG. 2).

When adjusting the ESD-relevant parameters, two basic conditions must be observed: on the one hand, the multi-finger current Imf (compare FIG. 2) must be smaller than the fault current It2, in which the ESD protection element is irreversibly damaged, on the one hand others, the ESD-relevant parameters and thus the U / I characteristic of the SD protection element should lie within a certain design window, which is limited at the lower end by the maximum signal voltage and at the upper end by the minimum breakdown voltage, at which parasitic or technologically implemented Break through the structures of the protective element.

According to a preferred embodiment of the invention this design window by specifying a certain Security area still reduced. In this case it is specified minimum voltage which is at least 10%, in particular at least 20% above the maximum Signal voltage Vsig is. At the upper limit of the Design window can also be given a voltage be the z. B. at least 10% below that Breakdown voltage Vd of parasitic structures.

In computer simulation, the differential resistance Rdiff by variation of Layout parameters, especially by varying the distance between gate and drain contact or gate and source contact (for MOS transistors) or the base width (for Bipolar transistors designed as an ESD protection element).

Furthermore, the trigger point (Vt1, It1) at which the voltage the U / I characteristic curve jumps back, based on layout parameters, in particular by varying the distance between the gate and Source contact or gate length (for MOS transistors) be adjusted.

Finally, the holding voltage Vsp can also be changed of the layout can be adjusted.

According to a preferred embodiment of the invention also the leakage current Ileak, which in normal operation, ie. H. at Signal voltage Vsig through which ESD protection elements flow, minimized by varying the layout. In the case of a MOS For this purpose, the transistor is changed, in particular, the gate length.

From the current and Temperature distribution in the protective element during ESD exposure can also make statements about ESD resistance with different process variants (different Gain doping profiles). Vulnerabilities, e.g. B.  unfavorable current distributions with too high current densities, recognized and eliminated accordingly.

The computer simulation is based on mathematical models, those for the high current case, d. H. the current flow that occurs at a electrostatic discharge occurs in the ESD protection element, are adapted. In particular, the Corresponding to the temperature dependence of the ionization rate α customized.

The invention is described below with reference to the accompanying Drawings explained in more detail by way of example. Show it:

Figure 1 is a circuit model with which the electrostatic discharge caused by a human body can be simulated.

FIG. 2 shows the U / I-characteristic of an ESD protection element;

FIG. 3 shows the dependence of the multi-finger distance from the current gate-drain contact; and

Fig. 4 is a flowchart representing the flow of a computer simulation.

Fig. 1 shows the so-called "human body model" with which the electrostatic discharge of a human body is simulated. A capacitor C with a capacitance of approximately 100-150 pF, to which a voltage of several kV is applied, is assumed as the charge source.

When the switch S is closed, the stored charge is discharged and a current in the ampere range flows via a pin or a contact pad 2 into the circuit (IC) 1 .

To protect against overload, ESD protection elements 3 , 3 'are provided at the output of the IC 1 , which ignite above a certain threshold or breakdown voltage Vbd and discharge the current to ground. An ESD protection element 3 or 3 ′ shown is representative of a plurality of protection elements arranged in parallel.

Particularly suitable as ESD protection elements 3 , 3 'are those whose U / I characteristic curve has a return or a good clamping behavior, as is the case with MOS or bipolar transistors, thyristors or diodes.

The circuit part shown on the right in FIG. 1 is the output stage of the actual IC 1 to the contact pad 2 , the output stage being constructed from two complementary MOS transistors 4 , 4 '.

Fig. 2 shows a typical U / I-characteristic of an ESD protection element 3, 3 ', wherein the course of the characteristic curve essentially by the breakdown voltage Vbd, the trigger voltage Vt1, the holding voltage Vsp and the differential high-current resistor is determined Rdiff. The breakdown voltage Vbd is the voltage from which the protective element 3 , 3 'changes to the conductive state, the trigger voltage Vt1 is the voltage from which the characteristic curve shows a return in the voltage and the holding voltage Vsp is the voltage from which the U / I characteristic curve with a differential resistance Rdiff or conductance increases further.

The multi-finger current Imf, which is defined as the current that flows in the ignited state (in the upper branch d of the characteristic curve) at the trigger voltage Vt1, has an important meaning for the ESD behavior of the protective element 3 , 3 '. In order to enable all protective elements 3 , 3 'to be fired as uniformly as possible, ie homogeneously, the multi-finger current Imf must be smaller than the fault current It2 in which the ESD protective element 3 , 3 ' is irreversibly damaged.

When using MOS transistors as ESD protection elements 3 , 3 ', various layout parameters, in particular the gate length or the distance between gate and drain contact or gate and source contact, are varied in the simulation in order to meet this boundary condition.

In addition to the multi-finger current Imf, a second boundary condition must be fulfilled: The U / I characteristic curve of an ESD protection element 3 , 3 'must neither be the maximum signal voltage Vsig nor the minimum breakdown voltage Vd of parasitic or real structures (gate oxide ) exceed. To ensure that this design window 5 is observed, a certain security area 6 is provided at the lower limit of the design window 5 . In the event of a high current, the characteristic curve must not enter this safety area 6 .

An optimization of the leakage current Ileak in normal operation can in simulation, for example, by setting the Gate length (with MOS transistors) are performed.

Another important variable in the design of the U / I characteristic is the differential resistance Rdiff in branch d of the characteristic. A homogeneous ignition of several ESD protection elements 3 , 3 'arranged in parallel is achieved the sooner the flatter branch d of the U / I characteristic curve, ie the greater the differential resistance Rdiff. On the other hand, with increasing differential resistance Rdiff, the ESD resistance of the ESD protective elements suffers, since with increasing differential resistance Rdiff the power loss increases and the ESD protective elements can fail due to high heat dissipation. The aim of the simulation must therefore also be to find an optimum between these limits by specifying technology and layout.

Fig. 3 shows the dependence of the multi-finger current Imf of the distance between the gate and drain contact (DCG) for an IC 1, wherein the MOS transistors for ESD protection elements 3, 3 'are provided. As can be seen, the optimal distance DCGopt is (arrow A) where the multi-finger voltage Imf falls below a predetermined threshold current Is. The threshold current Is is selected so that it is less than the leakage current It2. This enables homogeneous ignition of the ESD protective elements 3 , 3 'without destruction.

Fig. 4 shows a flowchart for the sequence of a typical computer simulation for the development of ESD protection elements 3, 3 '. In a first step 10 doping profiles and the layout of an ESD protection element 3 , 3 ', such as. B. a MOS transistor, entered into a simulation software or read from a database.

In a second step 11 , the virtual ESD protection element 3 , 3 'is simulated using mathematical models. The ESD protection element is in a suitable circuit ("human body model"), as z. B. is shown in Fig. 1, integrated in the simulation program. The result of the simulation is, in particular, the U / I characteristic of the ESD protection element 3 , 3 'and the ESD-relevant parameters Imf, It1, It2, etc. of the U / I characteristic. When using thermodynamic models, statements can also be made about the internal temperature distribution in the ESD protection element 3 , 3 '.

In step 12 it is checked whether the U / I characteristic curve complies with the boundary conditions mentioned above with reference to FIG. 2, ie whether the multi-finger current Imf is smaller than the leakage current It2, and whether the characteristic curve within a design window 5 also predetermined voltage limits. If both boundary conditions are met, it can be assumed with a high degree of probability that an ESD protection element 3 , 3 'realized with the doping and layout data specified in the simulation shows sufficiently good ESD protection behavior.

If one of the two boundary conditions is not met, the layout, possibly also the doping profile of the ESD protection element 3 , 3 ', is changed in the simulation program according to predetermined patterns (step 13 ) and a new simulation is carried out with the new data (step 11 ), until the specified boundary conditions are met.

LIST OF REFERENCE NUMBERS

1

integrated circuit (IC)

2

contact pad

3

.

3

'' ESD protection element

4

.

4

'MOS transistor

5

design window

6

security area

10-13

simulation Tasks
C capacitor
S switch
R resistance
Vsig signal voltage
Vsp withstand voltage
Vbd breakdown voltage
Vt1 trigger voltage
Vt2 failure voltage
Vd breakdown voltage
Rdiff differential resistance
It1 trigger current
It2 leakage current
Imf multi-finger stream
Ileak leakage current
DCG distance gate, drain contact

Claims (13)

1. A method for developing ESD protective elements, in particular transistors, thyristors or diodes, the U / I characteristic of which has a return, characterized in that the U / I characteristic of the ESD protective elements is designed by means of computer simulation in such a way that the ESD - Ignite protective elements ( 3 , 3 ') homogeneously. 2. The method according to claim 1, characterized in that the U / I characteristic of the ESD protection elements is designed by means of computer simulation in such a way that the ESD protection elements ( 3 , 3 ') only fail at high currents. 3. The method according to claim 1 or 2, characterized in that in a first step ( 10 ) the doping profiles are entered into the computer simulation and in a further step ( 13 ) layout parameters and / or the doping profiles are varied. 4. The method according to claim 1, 2 or 3, characterized, the U / I characteristic is designed so that a multi Finger current (Imf) is less than a leakage current (It2). 5. The method according to any one of the preceding claims, characterized in that the U / I characteristic or ESD-relevant parameters of the characteristic are designed such that the U / I characteristic is neither a maximum signal voltage (Vsig) nor a minimum Breakdown voltage (Vd) of parasitic or technologically implemented structures of the ESD protection element ( 3 , 3 ') exceeds. 6. The method according to claim 5, characterized, that ESD-relevant parameters of the U / I characteristic, in particular the breakdown voltage (Vbd), the trigger voltage (Vt1), the Holding voltage (Vsp) and / or the differential resistance (Rdiff), can be interpreted accordingly. 7. The method according to claim 6, characterized in that an ESD design window ( 5 ) limited by the maximum signal voltage (Vsig) and the minimum breakdown voltage by specifying a safety range, that is to say a voltage which is greater than the maximum signal voltage (Vsig) and / or a voltage that is less than the minimum breakdown voltage (Vd) is reduced. 8. The method according to any one of the preceding claims, characterized, that the U / I characteristic or the ESD-relevant parameters by varying the basis of the computer simulation Technology (doping profiles) and / or the layout becomes. 9. The method according to any one of claims 5 to 8, characterized in that the differential high current resistance (Rdiff) by varying the layout of the ESD protection elements ( 3 , 3 '), when using transistors as ESD protection elements ( 3 , 3 ') , by varying the distance between gate and drain contact, gate and source contact or the base width. 10. The method according to any one of the preceding claims, characterized, that the length of the recessed branch (c) of the U / I- Characteristic curve by varying the layout, in the case of Transistors, by varying the base width or the Gate length.   11. The method according to any one of claims 5 to 10, characterized, that the trigger voltage (Vt1) based on layout parameters, in particular the distance between the gate and source contact or the gate length. 12. The method according to any one of the preceding claims, characterized, that models implemented in computer simulation for the High current case are adapted, especially the Temperature dependence of the ionization rate (α) is adjusted. 13. Integrated circuit with ESD protection elements that were developed according to one of the preceding methods.