DE10120155B4 - Modulation with parallel turbo-rotary coding - Google Patents

Abstract

encoder for one Turbo coded trellis codemodulation with an encoder data block for storing incoming data and at least two parallel ones recursive systematic convolutional encoders, the recursive ones systematic convolutional encoder for receiving data in parallel are connected by the encoder data block, each being parallel recursive systematic convolutional encoders a first set of adders, wherein each adder is for receiving a plurality of data streams from connected to the encoder data block, a second set of Adders, with the outputs the respective adder of the first set of adders are, and delay units to Respectively the outputs of the second set of adders to their inputs in a recursive arrangement.

Description

Field of the invention

These The invention relates to the field of digital data transmissions and more particularly, an encoder for use in implementing a turbocharc-coded modulation schemes.

Background of the invention

One Turbo code has due to its larger coding gain attracted much interest. See, for example, "Application of Turbo Codes for Discrete Multi-Tone Modulation ", Hamid R. Sadjadpour, AT & T Shannon Labs. 1996. A turbo code consists of two or more convolutional codes, which are separated by an interleaving device, which processes the input sequence of the first encoder. In a digital Subscriber Multiplexing (DSL) system, a turbo code can be used to replace a trellis code for better bit error rate (BER) performance to obtain. However, as the constellation size increases, the Reduce coding gain advantage of the turbo code. This is because that the redundant bits make the constellation size even larger.

Our currently pending Patent application with same date describes as a turbo code can be used to get only the least significant bit (LSB) in to encode the constellation and thereby better performance to achieve than the currently used trellis-coded modulation, such as For example, a Wei code. The achievable data rate is only a few dB from the Shannon capacity away.

Out the article "DMT scheme with multidimensional turbo trellis code "by Cai, Z., Subramanian, K.R. Zhang, L. in Electronics Letters, vol. 36, no. 4, 17th February 2000, pp. 334-335 is an encoder for a turbocoded trellis code modulation with an encoder data block for storing incoming data and at least two parallel ones Recursive systematic convolutional encoders known, where the recursive systematic convolutional encoder for receiving data in parallel are connected by the encoder data block.

Further is in the article "Symbol-Based Turbo Codes "by Bingeman, M., and Khandani, A.K. in IEEE Communications Letters, Vol. 3, No. 10, October 1999 describes a symbol-based turbo coding, where a symbol consists of several bits. An encoder that performs this encoding, thus receiving several bits per symbol in parallel.

A The object of the invention is to provide a fast implementation an encoder for a turbotrellis-coded modulation.

Summary of the invention

According to the present According to the invention, there is provided a coding apparatus comprising a turbo-rolling code modulation signal generated, with an encoder data block for storing incoming Data and at least two recursive systematic convolutional encoders, the convolutional coders for receiving data from the encoder data block are connected, each parallel recursive systematic convolutional coders a first set of adders, wherein each adder is for receiving a plurality of data streams from the Encoder block is connected, a second set of adders, those with the outputs the respective adder of the first set of adders are, and delay units for feeding the outputs of the second set of adders to their inputs in a recursive arrangement.

The reduced structure with parallel implementation the implementation cycle for both the encoder and the associated decoder. In addition, can also the memory (RAM) requirement for such a turbo decoder saved in the case of a parallel implementation for three bits by 1/3 become.

Brief description of the drawings

The The invention will now be described by way of example only with reference to FIG the associated Drawings described in more detail, in which:

1 is a block diagram of a coder for a turbo-rolling code modulation;

2 Fig. 10 is a block diagram of a parallel implementation of the encoder;

3a shows a typical RSC encoder;

3b shows a parallel RSC encoder according to the principles of the invention;

4 Fig. 10 is a block diagram of a parallel turbo decoder;

5 represents the operation of the decoder;

6 represents the implementation of forward iteration;

7 shows a detail of 6 ; and

8th represents the implementation of backward iteration.

DETAILED DESCRIPTION OF THE INVENTION

Parallel encoder

The general constellation coder structure for a turbocharged-coded modulation scheme is shown in FIG 1 for the cases x> 1 and y> 1 shown. The input binary word u = (u _{z '} , u _z'-1 , ..., u ₁ ) determines two binary words v = (v _z'-y , ..., v ₀ ) and w = (w _y-1 , ..., w ₀ ) (where z '= x + y - 1) used to search two constellation points in an encoder table.

Of the Encoder data block 10 receives a portion of the data from an input bitstream and stores it In the storage room. The lowest order bits are taken from the encoder data block and recursive systematic convolutional encoders RSC1 and RSC2 forwarded.

Of the Turbocoder formed by block 20 is a more systematic one Encoder with a coding rate of 3/4, which at a rate of 1/2 is interrupted. The turbo encoder consists of two recursives systematic convolutional encoders RSC1 and RSC2. The RSC1 takes over continuous data from the encoder data block and the RSC2 takes over nested data from the same data block. In this structure There are three implementation cycles required to complete a single Constellation point, mainly due to the implementation requirement the turbo encoder is located.

To accelerate the process is in 2 a parallel encoder structure shown. The difference over 1 is that both RSC1 and RSC2 simultaneously accept three input data and generate one error check bit in a single implementation cycle.

A comparison between a normal RSC encoder and a parallel RSC encoder is in 3 shown, where 3 (a) is a normal 8-state RSC encoder and 3 (b) shows a parallel implementation. The parallel coder needs only one implementation cycle for every three input bits. Even though 3 (b) the same encoder as 3 (a) shows, it is not necessary that the parallel encoder is derived from a normal RSC encoder.

Parallel turbo decoder

• 1. Softdecodierung für das niedrigstwertige Bit (LSB);
• 2. Hartdecodierung für die höchstwertigen Bits (MSB);
• 3. Decodieren des LSB unter Verwendung eines Turbodecodiereralgorithmus;
• 4. Bestimmen aller Datenbits.

The decoding procedure for a turbo-radelliscoded modulation consists of the following steps:

• 1. Soft decoding for least significant bit (LSB);
• 2. hard decoding for the most significant bits (MSB);
• 3. decoding the LSB using a turbo decoder algorithm;
• 4. Determine all data bits.

Around to decode the LSB (third step) takes over the parallel turbo decoder three softbite input signals for each forward (α) and backward (β) iteration. In this way, only 1/3 cycles for each turbo decoder iteration and the memory requirements for storing α and β values also reduced by a factor of three.

The parallel turbo decoder is in 4 shown. It consists of two decoders 1, 2 and an interleaving device and a deinterleaving device.

5 shows a detail of the decoder 1 (the decoder 2 has the same structure). The decoders 1, 2 consist of blocks for calculating γ values, blocks for performing an iteration and a soft bit output block.

The first step in the decoding process, as in 5 is three soft bits P _3k (0), P _3k (1), P _{3k + 1} (0), P _{3k + 1} (1), P _{3k + 2} (0), P _{3k + 2} (1) to take eight probability values (a normal turbo decoder has only two values, since it contains only one information bit): P ^k ₀₀₀ , P ^k ₀₀₁ , P ^k ₀₁₀ , P ^k ₀₁₁ , P ^k ₁₀₀ , P ^k ₁₀₁ , P ^k ₁₁₀ and P ^k ₁₁₁ .

For example P k 000 = log [Prob (b 3k = 0, b 3k + 1 = 0, b 3k + 2 = 0)] = P 3k (0) + P 3k + 1 (0) + P 3k + 2 (0)

In general, P ^k _j can (j = mn1 = 000, 001, ..., 111) as P k mn1 = log [Prob (b 3k = m, b 3k + 1 = n, b 3k + 2 = 1)] = P 3k (m) + P 3k + 1 (n) + P 3k + 2 (1) to be obtained.

With P ^k _j and the corresponding error check bit (P _ck (0), P _ck (1)), the value γ _j (R _k , s', s) can be written as γ j (R k , s', s) = log (Pr (d k = j, p k = s, R k | S k-1 = s')) = P j k + P ck (M) where j = 000, 001, ..., 111 and m = 0 or 1 in response to the error check bit when transitioning from the state s' to s with the input data j. R _k represents the received information.

With γ _j (R _k , s', s), the forward iteration (a) can be performed with a LOG-MAP algorithm as in 6 be implemented, the normalization block puts all γ _j (R _k , s', s) in the middle of the dynamic range with the same scale factor so that the entire dynamic range can be used in a fixed point implementation.

The same principle is applied to the output α _k (s), ie all α _k (s) in another state s (for the same iteration k) are normalized with the same normalization factor, so that they are all in the middle of the dynamic range. The determination of the normalization factor is the same as that used in the implementation of the normal turbo decoder. The difference in forward iteration is that every state s in the iteration k (α _k (s)) is preceded by eight previous states (α ' _k-1 (s' ₀₀₀ ), α ' _k-1 (s' ₀₀₁ ), ..., α ' _k-1 (s' ₁₁₁ )) each corresponding to a value of an input γ _j (R _k , s', s) (in a conventional turbo decoder, each state at the iteration k is replaced by only two previous states are determined since the input signal is only one bit of information). The LOG-ADD-OPERATION in 6 is in 7 shown which consists of a max operation and a lookup table.

The backward iteration has the same structure as the forward iteration and is in 8th shown.

After completing forward and backward iteration, the soft bit outputs are calculated in two steps as follows:
first calculating eight P _j ^k values for j = 000, 001, ..., 111 as P k j = MAX (S, s') [γ j (R k , s, s') α k-1 (S ') β k (S)]

Then the soft output is the combination of P _i ^k values such as. B. P 3k 0 (0) = prob (b 3k = 0) = P k 000 + P k 010 + P k 100 + P k 110 P 3k 0 (1) = prob (b 3k = 1) = P k 001 + P k 011 + P k 101 + P k 111 P 3k + 1 0 (0) = prob (b 3k + 1 = 0) = P k 000 + P k 001 + P k 100 + P k 101 P 3k + 1 0 (1) = prob (b 3k + 1 = 1) = P k 010 + P k 011 + P k 110 + P k 111 P 3k + 2 0 (0) = prob (b 3k + 2 = 0) = P k 000 + P k 001 + P k 010 + P k 011 P 3k + 2 0 (1) = prob (b 3k + 2 = 1) = P k 100 + P k 101 + P k 110 + P k 111

During the last iteration, the soft error check bits are also output as: P 3k + 2 c (1) = prob (b 3k + 2 c = 1) = MAX (S, s') [γ c k1 (R k , s, s') α k-1 (S ') β k (S)] P 3k + 2 c (0) = prob (b 3k + 2 c = 0) = MAX (S, s') [γ ck0 (R k , s, s') α k-1 (S ') β k (S)] wherein γ _k0 (R _k, s, s ') and γ _ck1 (R _k, s, s'), the transition probability from state s represent to s, wherein the error check is (at time 3k + 2) 0 and 1 respectively.

The blocks described above can in a digital signal processor using standard digital processing methods, the Professionals of digital signal processing are implemented become.

The increase the procedure described the implementation speed of the turbo encoder and decoder and lead Significant memory savings in the parallel decoder.

she are applicable to a decoder with a variable coding rate.

Claims (4)

Encoder for a turbocoded trellis code modulation with an encoder data block for storing incoming data and at least two parallel ones recursive systematic convolutional encoders, the recursive ones systematic convolutional encoder for receiving data in parallel are connected by the encoder data block, each being parallel recursive systematic convolutional encoders a first set of adders, wherein each adder is for receiving a plurality of data streams from connected to the encoder data block, a second set of Adders, with the outputs the respective adder of the first set of adders are, and delay units for feeding the outputs of the second set of adders to their inputs in a recursive arrangement. An encoder according to claim 1, wherein each parallel recursive systematic convolutional encoder further comprises a further adder, the for receiving some of the data streams from the encoder data block and connected by output signals from some of the delay units is, wherein the output of the further adder, the output signal provides the recursive systematic convolutional encoder. An encoder according to claim 1, wherein the output signal an error check bit represents. The coder of claim 1, wherein the data streams are the least significant ones Represent bits of the encoded data.