DE10110624B4 - Integrated memory with several memory areas - Google Patents

Abstract

Integrated memory with the features:
a first (1) memory area writable via a connected third (11) data bus having a datum to a predetermined address, and a second (2) memory area communicating via a connected fourth databus (12) with a datum to a predetermined address is writable;
a data input circuit (10) via which a data can be applied to the third (11) and fourth (12) data buses;
selecting means (14, 15) comprising first (14) and second (15) selecting circuits, said selecting means (14, 15) between said data bus (11, 12) and said first (1) and second (2) storage areas wherein the first selection circuit (14) is connected to the first (1) memory area and the second (15) selection circuit is connected to the second (2) memory area and arranged in close proximity to the first (1) and second (2) memory areas are;
- Driver devices (3, 4), which between the first (14) and second (15) selection circuit ...

Description

The The invention relates to an integrated memory with a selection circuit for several storage areas.

integrated Memory usually have memory cells which are arranged in a matrix and via row and column lines can be addressed. About line addresses can on the row lines and over column addresses on the Column lines are accessed. This is the column address processed using an address decoder. The address decoder selects those column lines from where the addressed memory cells are located, in an entered date should be written into it.

at especially fast memory devices become data for writing applied to the memory synchronously with an external clock, with data transferred to the memory module with every rising edge and every falling edge become. As a result, the data rate compared to the previously common method (a transmission of data only on each rising or falling edge) become (Double Datarate technology).

at This fast integrated memory is provided with data even addresses, d. H. Addresses where the address value is even is, in a first memory area and data with odd addresses, d. H. Addresses in which the address value is odd, into one write second memory area. In a binary representation the respective address thus determines the least significant address bit, whether it is an odd or even address.

dates and addresses are essentially sent to the integrated memory created simultaneously, so that an appending address is the starting address for the simultaneously created date or the starting address for several Data (eg in case of burst access). It happens, however, that there is a time offset between addresses and data. For this reason, an internal clock for the integrated memory provided, with the help of addresses and data at the same time in the memory module to disposal can be made. Because addresses and data are due to the spatial distance of the external connections be applied to the integrated memory in various places, play the signal propagation times, especially at high data rates within the integrated circuit an essential role.

It It is an object of the invention to provide an integrated memory, where the selection of the storage area for even and odd addresses improves is, especially in the case of the negative influence of the signal propagation times is reduced within the integrated circuit.

These The object is achieved by the integrated memory according to claim 1. Further advantageous embodiments are given in the dependent claims.

According to the invention is a integrated memory having a first memory area and a second memory area Memory area provided over a connected data bus with a date at a given Address are writable. The date can be via a data input circuit be created on the data bus. Between the data bus and the first Memory area and between the data bus and the second memory area a selection device is arranged to be dependent on the created address the date to the first or the second Create storage area.

Of the Advantage of this integrated memory is that more time for the Decode the address and for the transfer the address to the respective memory area are made available can, since the selection, which date in the respective memory area is written individually with each driver device.

According to the invention is still provided that at the selection circuit, which is on the data bus Assigning data to the respective memory area, the least significant Address bit of the address before the data is applied, so that the data is correct can be assigned. Since after synchronization the data has a certain runtime until to the respective memory area, the selection circuits in the vicinity placed in the respective memory areas. In this way stands the Address signals, in particular the least significant address bit, more Time available, to get to the selection circuit before the address assigned to the address Data reach the selection circuit.

According to the invention is still provided that the selection device has selection circuits, immediately before an associated memory area is arranged to switch between the selection circuit and the writing in the memory area the smallest possible time offset to have.

When applying the data via the input circuit relative to the external clock signal, there is a time offset, ie the data comes up to a quarter of the clock period sooner or later. However, the address is always with the rise the edge of the external clock signal. Frequently, data is written in a so-called burst access in which a start address is applied, from which the subsequently transmitted data is written into a contiguous memory section starting from. In the integrated memory, the successively transmitted data are then written in the first and second memory areas for the even addresses and the odd addresses, respectively, and then in the second and first memory areas for the odd addresses and so on.

Tries one now directly with the least significant address bit of the address, the preferably with a rising edge of the internal clock is applied, the Decision about it to make sure that the respective date is in even or odd Memory area should be written, so problems arise due to the temporal offset of the applied data. In particular this is the case when with successive edges of the clock signal different Handing over addresses become. For this reason, the external data is first regarding a internal clock signal synchronized. Stand after the synchronization Although data and address are synchronized to each other, the data is available however, the addresses are in different places in the integrated one Memory in front.

The The invention will be explained in more detail below with reference to the following drawings. It demonstrate:

1 an integrated memory with a selection circuit according to the prior art; and

2 an integrated memory with a selection circuit according to an embodiment of the invention.

1 shows an integrated memory with a first memory area 1 for data with even addresses and a second memory area 2 for data with odd addresses. Successive addresses are not stored in a memory area with contiguous addressable memory cells, but in memory areas distinguished according to the evenness or oddness of the address value. The reason for this is that the writing and reading speed of the memory can be increased, in particular when data is to be written or read out into successive addresses.

The memory cells are in the memory areas 1 . 2 arranged so that they are addressed by row lines and column lines. The data is usually applied to the addressed column line at which the memory cell to be addressed is located. The date is written when the corresponding row line is activated.

To drive the column lines are for the first memory area 1 a first driver device 3 and driving the column lines of the second memory area 2 a second driver device is provided. The first and second driver devices 3 . 4 are with a first address decoder circuit 5 and a second address decoder circuit 6 connected. The first and second address decoder circuits 5 . 6 select according to an address A, the column lines on which the date to be written is to rest. At the first and second address decoders 5 . 6 are in each case via the address lines A1-AN to the address in which the data is to be written. The address lines A1-AN are connected to an address input circuit 16 connected to the external address A is applied. The first address decoder circuit 5 and the second address decoder circuit 6 can also be implemented in a common address decoder circuit.

To apply the data to be written to the addressed column lines is the first driver device 3 with a first data bus 7 and the second driver device 4 with a second data bus 8th connected. Via a data channel 9 are data packets from external source to an input circuit 10 created and transmitted data with each rising and falling edge. In the input circuit 10 In each case, two data received with the rising and the following falling edge of the external clock signal are parallelized. The input circuit 10 sets the data present at the rising edge of the clock signal to a third data bus 11 and the data present on a falling edge on a fourth data bus 12 ,

The integrated memory provides an internal clock signal. The input circuit 10 synchronizes over the data channel 9 received data to the internal clock signal. The address input circuit also synchronizes the externally applied address A to the internal clock, so that data and addresses are in synchronism with the internal clock signal but at different locations of the integrated memory.

The third data bus 11 and the fourth data bus 12 are with a selection circuit 13 connected. The selection circuit has as an input one with the address input circuit 16 connected address line A0, to each of which the least significant address bit of the multi-bit address A is present. Depending on the value of the least significant address bit, either the data on the third data bus 11 on the first data bus 7 and the data on the fourth data bus 12 on the second data bus 8th placed or the data on the third data bus 11 on the second data bus 8th and the data on the fourth data bus 12 on the first data bus 7 placed.

Usually located in an integrated memory, a plurality of memory areas, which are each provided with a driver device. Due to the size of the memory areas, the driver devices are located at some distance apart so that the data buses for supplying the respective data to be written to the memory areas are very branched. This usually makes it necessary for the selection circuit 13 near the input circuit 10 must be arranged so that the branching of the data buses 7 . 8th as efficiently as possible.

2 shows an embodiment of the integrated memory according to the invention, wherein like elements are provided with the same reference numerals.

As well as in 1 shown, the integrated memory points in 2 a first storage area 1 and a second storage area 2 on. First and second memory area 1 . 2 are with the first driver device 3 and the second driver device 4 connected. The first and second driver devices 3 . 4 are each with an address decoder 5 . 6 to which the external column address is applied via the address lines A1-AN. The in the storage areas 1 . 2 Data to be written is via the data channel 9 from the input circuit 10 received and on the third data bus 11 and the fourth data bus 12 placed so that the data received with the rising edge of the external clock signal on the third data bus 11 and the data received with the falling edge on the fourth data bus 12 be placed.

According to the invention now the third data bus 11 and the fourth data bus 12 distributed over the integrated memory circuit so that it connects to each of the driver circuits 3 . 4 be available. Furthermore, instead of a common selection circuit 13 at the first driver device 3 a first selection circuit 14 and at the second driver device 4 a second selection circuit 15 intended. The first and the second selection circuit 14 . 15 are very close to the respective driver devices in the integrated memory 3 . 4 arranged so that the data from the selection devices 14 . 15 only with a slight delay to the respective driver device 3 . 4 can reach. The first selection device 14 and the second selector 15 are controlled by the least significant address bit on the designated address line A0.

If the value of the address bit A0 is "0", then the first selection device is located 14 the third data bus 11 to the driver device 3 on and the second selection device 15 the data on the fourth data bus 12 to the second driver device 4 at. If the value of the address bit A0 is "1", the data on the fourth data bus becomes 12 over the first selection device 13 to the first driver device 3 created. The data on the third data bus 11 are then via the second selection device 14 to the second driver device 4 created. In this way it is achieved that consecutive data on the data channel 9 in the two different memory areas 1 . 2 be written into it.

The first address decoder 5 and the second address decoder 6 are controlled via the remaining address bits on the address lines A1-A0 so that according to a predetermined function, the first transmitted data in an address specified by the address bits either in the first memory area 1 or the second memory area 2 is written and the following date, that on the fourth data bus 12 is present, either in the logically subsequent memory address or the logically underlying memory address is written.

So a write to the memory areas 1 . 2 can be performed, the column lines through the respective driver devices 3 . 4 via the corresponding address decoder 5 . 6 be driven before the date to be stored in this memory cell at the respective driver device 3 . 4 is applied. In particular, this presents a problem because, according to the specification (eg, the double-data rate technology), that caused by the input circuit 10 received data in synchronism with an external clock signal, while the associated address information may be compared to the external clock signal by up to a quarter of the clock period earlier or later. Due to the fact that the external signals are made available in different places in the integrated memory, signal propagation times which are not negligible occur due to the line lengths required thereby. So that jewei time selection circuit 14 . 15 always the data in the correct assignment on the data bus selected by the address bit A0 11 . 12 to the driver device 3 . 4 applies, the least significant address bit A0 must be present before the arrival of the data. This is particularly difficult to realize when the input circuit 10 arranged to receive the external data immediately in the vicinity of the terminals for the external data and due to the necessary branches of the data buses, as related to 1 explains the common selection circuit 13 in front of the necessary branches in the vicinity of the respective input circuit 10 is arranged. In this case, the least significant address bit from the address input located at another location of the integrated memory must be supplied via the corresponding address line A0 to the selection circuit 13 be guided, which requires the term T1. So far, for this reason, the received data either in the input circuit 10 or artificially delayed shortly thereafter, to ensure that the selection circuit 13 is driven with the aid of the applied least significant address bit so that the data received with the rising clock edge and the data received with the falling clock edge, respectively the addressed memory area 1 . 2 be assigned.

Because the selection circuit 13 at 1 near the input circuit 10 is arranged, the first data bus 7 and the second data bus 8th ( 1 ) has a non-negligible length, which requires a certain transit time T2. At the earliest, therefore, the data are at the respective driver device 3 . 4 after a period of T1 + T2. It is the respective address decoder 5 . 6 then this time duration T1 + T2 is available to decode the applied column addresses and via the respective driver device 3 . 4 to address the corresponding column lines. The address decoder 5 . 6 and the address lines A1-AN connected thereto have a transit time of T3. It is therefore to be provided that the address data, in particular the least significant address bit A0, is connected to the selection circuit 13 is present before the data is the input circuit 10 as well as the third data bus 11 and the fourth data bus 12 have happened. This is time critical and for this reason makes it necessary to introduce a time delay with the data before reaching the selection circuit 13 can be delayed. The time delay must be at least T1, so that the least significant address bit, the selection circuit 13 reached before the respective data.

The circuit according to the invention now provides to relax the temporal condition, and the time period which is available to the least significant address bit A0 to the respective selection circuit 14 . 15 create, enlarge. Due to the fact that the respective selection circuits 14 . 15 near the driver device 3 . 4 are arranged, the transit time of the data signals over the third data bus 11 and the fourth data bus 12 as well as through the input circuit 10 T2, whereby the address bit A0 more time available, the respective selection circuit 14 . 15 to reach. On an artificial delay of the data z. B. in the input circuit 10 can u. May even be omitted entirely if T2 is greater than T1. It is only necessary to provide that instead of a common selection circuit 13 near the input circuit 13 is arranged, in each case a selection circuit 14 . 15 at each driver device 3 . 4 is arranged.

The critical timing thus results from the fact that the least significant address bit is to be applied before the data at the respective selection circuit, so that the respective correct date of the third data bus 11 and the fourth data bus 12 to the corresponding memory area 1 . 2 is passed on. The selection devices 14 . 15 Thus, according to the invention, they continue in the direction of the data receiver, ie the memory area 1 . 2 , postponed. The runtime of the data is not changed as the absolute cable length remains unchanged. In particular, when the address signals are applied with a small time shift less than a quarter of the clock period later than the data signals, such an arrangement is advantageous.

1

storage area

2

storage area

3

first driving device

4

second driving device

5

first address decoder

6

second address decoder

7

first bus

8th

second bus

9

data channel

10

input circuit

11

third bus

12

fourth bus

13

selector

14

first selector

15

second selector

16

Address input circuit

A1-AN

address bits

A1

least significant address bit

DQ

dates

Claims (3)

Integrated memory with the features: a first ( 1 ) Memory area connected via a third ( 11 ) Data bus with a date to a given address is writable, and a second ( 2 ) Memory area which is connected via a connected fourth data bus ( 12 ) is writable with a date to a given address; a data input circuit ( 10 ), on which a date is sent to the third ( 11 ) and fourth ( 12 ) Data bus can be applied; a selection device ( 14 . 15 ), which is a first ( 14 ) and second ( 15 ) Selection circuit, the off dialing device ( 14 . 15 ) between the data bus ( 11 . 12 ) and the first ( 1 ) and the second ( 2 ) Memory area is arranged, wherein the first selection circuit ( 14 ) with the first ( 1 ) Memory area and the second ( 15 ) Selection circuit with the second ( 2 ) Storage area are connected and in close proximity to the first ( 1 ) and second ( 2 ) Memory area are arranged; Driver devices ( 3 . 4 ), which between the first ( 14 ) and second ( 15 ) Selection circuit ( 14 . 15 ) and the first ( 1 ) and second ( 2 ) Memory area are arranged; - a third one ( 11 ) Data bus which is connected between the data input circuit ( 10 ) and the selection circuit ( 14 ), and a fourth ( 12 ) Data bus which is connected between the data input circuit ( 10 ) and the selection circuit ( 15 ), wherein a datum from the data input circuit ( 10 ) to one of the selection circuits ( 14 . 15 ) requires a second time (T2); An address bus (A) connected between the address input circuit ( 16 ) and the selection device ( 14 . 15 ), wherein an address data within a first time (T1) from the address input circuit ( 16 ) to the selector ( 14 . 15 ) and that the length of the data bus ( 11 . 12 ) and the length of the address bus (A) are selected such that the second time (T2) is greater than the first time (T1). The integrated memory of claim 1, wherein the address has a plurality of address bits, and wherein the respective select circuits ( 14 . 15 ) the date sets the date to the first and second memory area depending on the least significant address bit. Integrated circuit according to one of claims 1 to 2, wherein on the data bus ( 11 . 12 ), a first date and a second date are provided, the selection means ( 14 . 15 ) applies the first date to one memory area and the second date to the other memory area, depending on the address applied.