DE10104274C5 - Semiconductor device with MOS gate control and with a contact structure and method for its production - Google Patents

Semiconductor device with MOS gate control and with a contact structure and method for its production Download PDF

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Publication number
DE10104274C5
DE10104274C5 DE10104274A DE10104274A DE10104274C5 DE 10104274 C5 DE10104274 C5 DE 10104274C5 DE 10104274 A DE10104274 A DE 10104274A DE 10104274 A DE10104274 A DE 10104274A DE 10104274 C5 DE10104274 C5 DE 10104274C5
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Prior art keywords
layer
contact
contact structure
sidewall spacers
active surface
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DE10104274A
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German (de)
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DE10104274A1 (en
DE10104274B4 (en
Inventor
Thomas Manhattan Beach Herman
Kyle Temecula Spring
Mark Temecula Maier
Harold San Diego Davis
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Publication of DE10104274C5 publication Critical patent/DE10104274C5/en
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Abstract

Halbleiterbauteil mit MOS-Gatesteuerung, mit einer Kontaktstruktur für einen Kontakt an die aktive Oberfläche des Bauteils,
wobei die aktive Oberfläche ein Übergangsmuster vom DMOS-Typ in der oberen Oberfläche eines Silizium-Halbleiterplättchens aufweist, und das DMOS-Übergangsmuster aus Isoliermaterial bestehende Seitenwand-Abstandselemente zur Isolation eines Polysilizium-Gates von der Kontaktstruktur aufweist,
wobei die Seitenwand-Abstandselemente eine Dicke von ungefähr 0,5 μm an den Seitenkanten der Polysiliziumschicht aufweisen,
wobei die Kontaktstruktur eine dünne, metallische, leitende Trennschicht (100), die direkt auf die freiliegenden Oberflächen der Seitenwand-Abstandselemente (63–67) aufgebracht ist,
sowie eine relativ dickere aus reinem Aluminium bestehende Aluminium-Schicht (101) aufweist, die über der gesamten aktiven Oberfläche und über der dünnen, metallischen, leitenden Trennschicht aufgebracht ist und mit dieser in Kontakt steht.Semiconductor device with MOS gate control, having a contact structure for contact with the active surface of the device,
wherein the active surface has a DMOS-type junction pattern in the top surface of a silicon die, and the DMOS transition pattern comprises insulating sidewall spacers for isolating a polysilicon gate from the contact structure,
wherein the sidewall spacers have a thickness of approximately 0.5 μm at the side edges of the polysilicon layer,
the contact structure comprising a thin, metallic, conductive separation layer (100) applied directly to the exposed surfaces of the sidewall spacers (63-67),
and a relatively thicker pure aluminum aluminum layer (101) applied over and in contact with the entire active surface and over the thin metallic conductive barrier layer.

Figure 00000001
Figure 00000001

Description

Die Erfindung bezieht sich auf ein Halbleiterbauteil mit MOS-Gatesteuerung, mit einer Kontaktstruktur für einen Kontakt an die aktive Oberfläche des Bauteils, wobei die aktive Oberfläche ein Übergangsmuster vom DMOS-Typ in der oberen Oberfläche eines Silizium-Halbleiterplättchens aufweist, und das DMOS-Übergangsmuster aus Isoliermaterial bestehende Seitenwand-Abstandselemente zur Isolation eines Polysilizium-Gates von der Kontaktstruktur aufweist, sowie auf ein Verfahren zur Herstellung dieses Halbleiterbauteils.The The invention relates to a semiconductor device with MOS gate control, with a contact structure for a contact to the active surface of the component, wherein the active surface a transition pattern DMOS type in the upper surface of a silicon wafer and the DMOS transition pattern insulating sidewall spacer elements for insulation a polysilicon gate of the contact structure, as well as to a method of manufacturing this semiconductor device.

Die Erfindung bezieht sich insbesondere auf ein Halbleiterbauteil und ein Herstellungsverfahren für Halbleiterbauteile mit MOS-Gatesteuerung, wie z.B. Leistungs-MOSFET- und IGBT-Bauteile und Thyristoren mit MOS-Gatesteuerung.The The invention relates in particular to a semiconductor device and a manufacturing process for Semiconductor devices with MOS gate control, e.g. Power MOSFET and IGBT devices and thyristors with MOS gate control.

Der Erfindung liegt die Aufgabe zugrunde, ein neuartiges Halbleiterbauteil sowie ein Verfahren zu seiner Herstellung, das eine verbesserte Drahtkontaktierung mit einer Kontaktschicht oberhalb einer die Übergänge enthaltenden aktiven Oberfläche ermöglicht und weiterhin Stufen in der Struktur besser abdeckt.Of the Invention is based on the object, a novel semiconductor device and a process for its preparation which has improved Wire bonding with a contact layer above one of the transitions active surface allows and continues to better cover levels in the structure.

Diese Aufgabe wird durch die im Patentanspruch 1 bzw. 6 angegebenen Merkmale gelöst.These The object is achieved by the features specified in claim 1 and 6 respectively solved.

Stand der TechnikState of the art

Halbleiterbauteile mit MOS-Gatesteuerung mit aktiven Kontaktflächen, bei denen eine Drahtkontaktierung oder dergleichen direkt oberhalb von aktiven Übergängen hergestellt werden kann, die unter einer Source- oder Emitter-Kontaktschicht liegen, sind gut bekannt. Derartige Bauteile sind beispielsweise in der US 5 795 793 A gezeigt.Semiconductor devices with MOS gate control with active pads in which wire bonding or the like can be made directly above active junctions underlying a source or emitter contact layer are well known. Such components are for example in the US 5 795 793 A shown.

Derartige Bauteile haben üblicherweise ein geeignetes Übergangsmuster, beispielsweise ein DMOS-Muster, auf der oberen Oberfläche eines monokristallinen Silizium-Halbleiterplättchens. Eine kontinuierliche Aluminium-Source-Elektrode (Aluminium, das ungefähr 1% Silizium enthält) wird dann über der oberen Oberfläche des Halbleiterbauteils ausgebildet und ergibt einen Ohm'schen Kontakt mit den Source- und Basis-Bereichen des Übergangsmusters. Diese Bereiche können irgendeine gewünschte Topologie aufweisen, die z.B. eine planare zellulare oder planare Streifen- oder eine Grabenstruktur. Im Fall eines IGBT kann der Source-Bereich als Emitterbereich bezeichnet werden, während die Source-Elektrode als Emitterelektrode bezeichnet wird.such Components usually have a suitable transition pattern, For example, a DMOS pattern on the top surface of a monocrystalline silicon semiconductor chip. A continuous one Aluminum source electrode (aluminum containing about 1% silicon) then over the upper surface formed of the semiconductor device and gives an ohmic contact with the source and Basic areas of the transition pattern. These areas can any desired Have topology, e.g. a planar cellular or planar Strip or trench structure. In the case of an IGBT, the Source region can be referred to as the emitter region, while the Source electrode is referred to as emitter electrode.

Die obere Oberfläche des Silizium-Halbleiterplättchens weist weiterhin eine Polysilizium-Gateelektrodenstruktur auf, die über einer Gate-Isolierschicht (üblicherweise einem Oxid) angeordnet ist. Die Seitenkanten und die Oberseite der Gateelektrodenelemente oder des Gateelektrodenmusters werden üblicherweise durch eine Niedrigtemperatur-Oxidschicht abgedeckt, die vertikale Seitenwände oder Abstandselemente aufweist. Die Aluminiumelektrode gelangt dann mit den Basis- und Sourcebereichen an der Siliziumoberfläche in Kontakt, sie ist jedoch von der Polysilizium-Gateelektrode isoliert. Wie dies weiter oben erwähnt wurde, ist die "Aluminium"-Elektrode tatsächlich AlSi, eine Legierung aus Aluminium und ungefähr 1% Silizium.The upper surface of the silicon semiconductor chip further comprises a polysilicon gate electrode structure overlying a Gate insulating layer (usually an oxide) is arranged. The side edges and the top of the Gate electrode elements or the gate electrode pattern usually become covered by a low-temperature oxide layer, the vertical Sidewalls or Has spacer elements. The aluminum electrode then arrives the base and source regions on the silicon surface in contact, however, it is isolated from the polysilicon gate electrode. As this is mentioned above was, the "aluminum" electrode is actually AlSi, an alloy of aluminum and about 1% silicon.

Diese Bauteile sind so ausgebildet, daß Drahtleitungen, üblicherweise dünne Golddrahtleitungen, durch Ultraschall mit der oberen Oberfläche der Source- oder Emitter-Elektrode (die nachfolgend als "Source"-Elektrode bezeichnet wird) verbunden werden können, und zwar direkt oberhalb der aktiven Übergänge, ohne daß diese Übergänge beschädigt werden.These Components are designed so that wire cables, usually thin gold wire cables, by ultrasound to the top surface of the source or emitter electrode (hereinafter referred to as "source" electrode will be connected), directly above the active transitions without damaging these junctions.

Es wurde festgestellt, daß insbesondere bei Verwendung eines dünnen Seitenwand-Abstandselemente-Oxids (beispielsweise mit einer Dicke von ungefähr 0,5 Mikrometern) Bauteile mit durch Ultraschall verbundenen Drahtleitungen während eines Betriebs mit periodisch schwankenden Temperaturen ausfallen können. Nach einer Überprüfung dieser Teile wurde davon ausgegangen, daß die Ausfälle sich aus dem unerwarteten Vorhandensein von sehr harten Siliziumkörnern oder -klumpen ergeben, die in dem Grenzbereich zwischen dem Seitenwand-Abstandsstück und dem AlSi-Sourcekontakt auftraten. Es wird angenommen, daß diese Klumpen oder Körner aus dem AlSi-Kontakt ausgefällt werden, und daß sie mechanisch die Seitenwand während kontinuierlicher Temperaturänderungen beanspruchen und/oder abschleifen. Es wird weiterhin angenommen, daß derartige Schäden aus der Drahtkontaktierung mit dem AlSi-Kontakt entstehen.It it was found that in particular when using a thin Sidewall spacer oxide (for example, having a thickness of about 0.5 microns) components with ultrasonically connected wire leads while operation with periodically fluctuating temperatures can. After a review of these parts It was assumed that the Failures themselves from the unexpected presence of very hard silicon grains or resulting in the boundary region between the side wall spacer and the AlSi source contact occurred. It is believed that this Lumps or grains precipitated from the AlSi contact be, and that they mechanically the sidewall during continuous temperature changes claim and / or abrade. It is further assumed that such damage arising from the wire bonding with the AlSi contact.

Aufgabenstellungtask

Vorteilhafte Ausgestaltungen und Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen.advantageous Refinements and developments of the invention will become apparent the dependent claims.

Gemäß der vorliegenden Erfindung wird eine dünne Metall-Trenn- oder Sperrschicht zwischen dem AlSi- oder dem Al-Sourcekontakt und den Seitenwand-Abstandselementen angeordnet, wobei diese Trennschicht als Trennschicht für mechanische Spannungen zwischen den Seitenwand-Abstandselementen und dem darüberliegenden Kontakt wirkt. Es wird angenommen, daß die dünne Trennschicht Drahtkontaktierungskräfte absorbiert oder verteilt. Es wurde weiterhin festgestellt, daß es möglich ist, aufgrund der Verwendung der Trennschicht die übliche AlSi-Sourceelektrode durch eine Elektrode aus reinem Aluminium (Reinheit von 0,9999) zu ersetzen, die einen niedrigeren spezifischen Widerstand (ungefähr 15% niedriger) aufweist, als das übliche AlSi-Sourceelektrodenmetall. Hierdurch wird weiterhin die Bildung von ausgefällten harten, eine Schleifwir kung aufweisenden Körnern oder Klumpen und deren Schleifwirkung während zyklischer Temperaturänderungen verhindert.In accordance with the present invention, a thin metal barrier layer is disposed between the AlSi or Al source contact and the sidewall spacers, which interface acts as a stress relieving layer between the sidewall spacers and the overlying contact. It is believed that the thin release layer absorbs or distributes wire bonding forces. It has also been found that it is possible, due to the use of the separation layer, the usual AlSi source electrode by an electrode from rei to replace aluminum (purity of 0.9999), which has a lower resistivity (about 15% lower) than the usual AlSi source electrode metal. As a result, the formation of precipitated hard, abrasive effect having grains or lumps and their abrasive action during cyclic temperature changes is further prevented.

Als weiterer Vorteil der Erfindung hat es sich herausgestellt, daß die dünne (0,2 Mikrometer) Trennschicht und die dicke, aus reinem Aluminium bestehende Schicht (8 Mikrometer) eine verbesserte Abdeckung von Stufen durch die Sourceelektrode über den verschiedenen Kanten ergeben, die in der oberen Siliziumoberfläche und aufgrund der Polysilizium-Elektrode vorliegen.When Another advantage of the invention, it has been found that the thin (0.2 Micrometer) separating layer and the thick, made of pure aluminum Layer (8 microns) improved coverage of stages through the source electrode over the different edges that result in the upper silicon surface and due to the polysilicon electrode.

Die Verwendung von aus reinem Aluminium bestehenden Kontakten führt zu weiteren unerwarteten Vorteilen. Beispielsweise wird hierdurch die Verwendung von Kupfer-Kontaktierungsdrähten ermöglicht.The Use of contacts made of pure aluminum leads to more unexpected benefits. For example, this is the use of copper bonding wires allows.

Ausführungsbeispielembodiment

Ein Ausführungsbeispiel der Erfindung wird im folgenden anhand der Zeichnungen noch näher erläutert.One embodiment The invention will be explained in more detail below with reference to the drawings.

In der Zeichnung zeigen:In show the drawing:

1 eine Querschnittsansicht des aktiven Teils eines bekannten Leistungs-MOSFET-Bauteils, das ein übliches DMOS-Übergangsmuster und einen AlSi-Sourcekontakt verwendet, 1 12 is a cross-sectional view of the active part of a prior art power MOSFET device using a common DMOS junction pattern and an AlSi source contact;

2 eine der 1 entsprechende Querschnittsansicht, die jedoch eine Trennmetallschicht unterhalb eines aus reinem Aluminium bestehenden Sourcekontaktes gemäß der Erfindung verwendet. 2 one of the 1 corresponding cross-sectional view, however, which uses a separation metal layer below a pure aluminum source contact according to the invention.

In 1 ist ein sehr kleiner Abschnitt des aktiven Teils eines Leistungs-MOSFET-Bauteils im Querschnitt gezeigt. Das gezeigte Bauteil kann irgendeine gewünschte Topologie aufweisen, beispielsweise mit Abstand voneinander angeordnete vieleckige Zellen, wie in der US 5 008 725 A oder parallele, in Abstand voneinander angeordnete Streifen.In 1 For example, a very small portion of the active part of a power MOSFET device is shown in cross-section. The component shown may have any desired topology, such as spaced-apart polygonal cells, as shown in FIG US 5 008 725 A or parallel, spaced-apart strips.

Allgemein wird das MOSFET-Bauteil in einem Halbleiterplättchen oder Chip (der ein Teil einer Halbleiterscheibe ist, in dem viele derartige Chips gleichzeitig verarbeitet werden) gebildet, das bzw. der einen N+-Hauptteil 20 und eine darauf angeordnete epitaxial abgeschiedene, die Übergänge aufnehmende N–-Schicht 4 aufweist. Die Dicke und Konzentration der Schicht 21 ist durch die gewünschte Durchbruchspannung des Halbleiterbauteils bestimmt. Wenn das Bauteil nach 1 ein IGBT sein soll, so würde der Hauptteil 20 vom P-Leitungstyp sein und allgemein eine dünne N+-Pufferschicht über dieser Schicht aufweisen, und der N–-Bereich 21 würde über der Pufferschicht liegen.Generally, the MOSFET device is formed in a die or chip (which is a part of a wafer in which many such chips are processed simultaneously) which is an N + body 20 and an epitaxially deposited transition-receiving N - layer disposed thereon 4 having. The thickness and concentration of the layer 21 is determined by the desired breakdown voltage of the semiconductor device. If the component after 1 an IGBT should be, so the main part 20 of the P-type conductivity and generally have a thin N + buffer layer over this layer, and the N - region 21 would be above the buffer layer.

Ein Übergangsmuster vom DMOS-Typ wird dann in der oberen Oberfläche des Bereiches 21 ausgebildet, obwohl auch andere Muster verwendet werden könnten und einen Vorteil aus der zu beschreibenden Erfindung ziehen würden. Ein typisches Muster besteht aus mit Abstand voneinander angeordneten P-Basis-(oder Kanal-)Bereichen 30, 31 und 32, die selbstausgerichtete N+-Source-Bereiche 33, 34 bzw. 35 enthalten. Wenn eine zellenförmige Geometrie verwendet wird, so sind die Source-Bereiche 33, 34 und 35 ringförmig und bilden ringförmige invertierbare Kanalbereiche zwischen ihren Außenumfängen und den Umfängen der P-Bereiche 30, 31 bzw. 32 an der oberen Oberfläche des Bereiches 21. Wenn eine streifenförmige Geometrie verwendet wird, so würden die Bereiche 30, 31 und 32 parallele Streifen sein, und die Source-Bereiche 33, 34 und 35 würden sich entlang der gegenüberliegenden Seiten jedes der Basisbereiche erstrecken.A transition pattern of the DMOS type will then be in the upper surface of the area 21 Although other patterns could be used and would benefit from the invention to be described. A typical pattern consists of spaced P-base (or channel) regions 30 . 31 and 32 , the self-aligned N + source areas 33 . 34 respectively. 35 contain. If a cellular geometry is used, then the source regions are 33 . 34 and 35 annular and form annular invertible channel regions between their outer peripheries and the peripheries of the P regions 30 . 31 respectively. 32 on the upper surface of the area 21 , If a strip-shaped geometry is used, the areas would be 30 . 31 and 32 be parallel stripes, and the source areas 33 . 34 and 35 would extend along the opposite sides of each of the base regions.

Unabhängig von der verwendeten Geometrie ist eine Gate-Isolation, üblicherweise Siliziumdioxid, oberhalb der Kanalbereiche angeordnet und erstreckt sich über die gleichen Bereiche wie diese. Somit erstrecken sich dünne Gateoxidschichten 40, 41 und 42 über den invertierbaren Kanalbereichen, wie dies gezeigt ist. Dieses Gateoxid würde ein einziges Gitter sein, wenn eine zellenförmige Geometrie verwendet wird, während es mit Abstand voneinander angeordnete parallele Streifen umfassen würde, wenn eine streifenförmige Geometrie verwendet wird. Leitende Polysilizium-Schichten 50, 51 und 52 (oder ein Polysilizium-Gitter) liegen über den Gateoxidelementen 40, 41 bzw. 42 und erstrecken sich über gleiche Flächen wie diese.Regardless of the geometry used, a gate insulation, typically silicon dioxide, is disposed above the channel regions and extends over the same regions as these. Thus, thin gate oxide layers extend 40 . 41 and 42 over the invertible channel regions, as shown. This gate oxide would be a single grating if a cellular geometry were used, while it would include spaced apart parallel strips if a stripe geometry is used. Conductive polysilicon layers 50 . 51 and 52 (or a polysilicon grid) overlying the gate oxide elements 40 . 41 respectively. 42 and extend over similar surfaces like these.

Eine LTO-(Niedrigtemperatur-Oxid-)Schicht mit oberen Segmenten 60, 61, 62 und Seiten wand-Abstandselementen 63, 64–65 bzw. 66–67 bedeckt vollständig die leitenden Polysiliziumsegmente 50, 51 und 52 und isoliert diese. Die Seitenwandsegmente weisen üblicherweise eine Dicke von ungefähr 0,5 Mikrometern auf.An LTO (low temperature oxide) layer with upper segments 60 . 61 . 62 and side wall spacers 63 . 64 - 65 respectively. 66 - 67 completely covers the conductive polysilicon segments 50 . 51 and 52 and isolate them. The sidewall segments typically have a thickness of about 0.5 microns.

Danach wird in der in 1 gezeigten Weise eine übliche AlSi-Sourceelektrode 70 über der oberen Oberfläche des Bauteils und über der Oberfläche der LTO-Schicht abgeschieden. Es sei darauf hingewiesen, daß flache Öffnungen 80, 81 und 82 in die Oberfläche des Siliziums an den Mittelpunkten jeder der Basiszellen und zwischen benachbarten, mit Abstand angeordneten Seitenwandabschnitten eingeätzt sind. Diese Öffnungen ermöglichen es, daß die Aluminium-Silizium-Sourceelektrode 70 einen guten Kontakt mit den P-Bereichen 30, 31 und 32 und ihren jeweiligen Sourcebereichen herstellt.After that, in the in 1 shown a common AlSi source electrode 70 deposited over the top surface of the device and over the surface of the LTO layer. It should be noted that shallow openings 80 . 81 and 82 etched into the surface of silicon at the midpoints of each of the base cells and between adjacent spaced apart sidewall portions. These openings allow the aluminum-silicon source electrode 70 a good Contact with the P areas 30 . 31 and 32 and their respective source areas.

Ein unterer Drain-(oder Kollektor-)Kontakt 90, der aus einer üblichen Drei-Metall-Schicht bestehen kann, wird dann auf der Unterseite des Halblei terplättchens ausgebildet.A lower drain (or collector) contact 90 , which may consist of a conventional three-metal layer is then formed terplättchens on the underside of the semicon.

Es ist üblich, ein oder mehrere Gold- oder Aluminiumdrähte durch Drahtkontaktierung mit der oberen Oberfläche des Bauteils und oberhalb der aktiven Übergangsbereiche zu verbinden, wie dies für den Kontaktierungsdraht 92 in 1 gezeigt ist.It is common to connect one or more gold or aluminum wires by wire bonding to the top surface of the device and above the active junction regions, as for the bonding wire 92 in 1 is shown.

Es wurde festgestellt, daß die mechanischen Spannungen, die durch die Drahtkontaktierungen erzeugt werden, und durch periodische Temperaturschwankungen Ausfälle des Bauteils durch Schäden an den Seitenwänden 63–67 hervorgerufen werden können, wodurch ein Kurzschluß oder eine Verbindung zwischen der Sourceelektrode und dem im übrigen isolierten Gate-Polysilizium 50, 51 und 52 zustande kommen kann. Bei einer Überprüfung von ausgefallenen Bauteilen wurden winzige harte Silizium-Körner oder -Klumpen in dem Grenzbereich zwischen den Seitenwänden 63–67 und der AlSi-Kontaktschicht 70 gefunden. Es wird angenommen, daß diese aus der üblichen AlSi-Elektrode 70 ausgefällt wurden.It has been found that the mechanical stresses generated by the wire bonds and by periodic variations in temperature failures of the component due to damage to the side walls 63 - 67 which can cause a short circuit or a connection between the source electrode and the otherwise isolated gate polysilicon 50 . 51 and 52 can come about. Upon inspection of failed components, tiny hard silicon grains or clumps were in the interface between the sidewalls 63 - 67 and the AlSi contact layer 70 found. It is believed that these are from the usual AlSi electrode 70 were precipitated.

Gemäß einem ersten Merkmal der Erfindung, wie dies in 2 gezeigt ist, wird eine dünne metallische Sperr- oder Trennschicht 100, vorzugsweise aus TiW, direkt über der mit dem Muster versehenen LTO-Schicht nach 2 abgeschieden, und diese Trennschicht liegt unter dem Haupt-Sourcekontakt. Die Schicht 100 ist dünn, und sie weist vorzugsweise eine Dicke von 0,25 Mikrometern auf, und sie kann eine Dicke im Bereich von 0,05–0,35 Mikrometern aufweisen. Vorzugsweise besteht die Schicht 100 aus TiW (10% Ti und 90 W), und sie wird durch ein übliches Zerstäubungsverfahren abgeschieden. Andere Materialien, wie z.B. TiN, können ebenfalls verwendet werden.According to a first feature of the invention, as shown in FIG 2 is shown, a thin metallic barrier or release layer 100 , preferably of TiW, directly over the patterned LTO layer 2 deposited, and this separation layer is below the main source contact. The layer 100 is thin, and preferably has a thickness of 0.25 microns, and may have a thickness in the range of 0.05-0.35 microns. Preferably, the layer consists 100 TiW (10% Ti and 90 W), and it is deposited by a conventional sputtering method. Other materials, such as TiN, may also be used.

Es wurde festgestellt, daß die dünne Trennschicht dazu neigt, mechanische Spannungen zu verteilen, die während der Drahtkontaktierung hervorgerufen werden, was dazu beiträgt, ein Brechen der Oxid-Seitenwände oder Abstandselemente zu verhindern.It it was found that the thin separating layer tends to distribute mechanical stresses during the Wire contacting caused what contributes to a Breaking the oxide sidewalls or to prevent spacers.

Es wurde als nächstes erkannt, daß weil eine dünne leitende Trennschicht über der oberen Oberfläche des Halbleiterplättchens liegt und mit den Source- und Basis-Bereichen an der Oberfläche des Bauteils in Kontakt kommt, die Sourceelektrode keine Silizium-Komponente aufweisen muß, die sonst in der AlSi-Elektrode vorhanden ist. Somit kann die Hauptelektrode oberhalb der Trennschicht 100 eine aus reinem Aluminium (0,999) bestehende Schicht 101 (2) sein, die beispielsweise 8 Mikrometer dick ist (unkritisch). Weiterhin wird bei Verwendung der TiW-Trennschicht reines Aluminium gegenüber AlSi bevorzugt, weil dies eine verbesserte Kompatibilität mit TiW ergibt. Dieser aus reinem Aluminium bestehende Kontakt hat einen um ungefähr 15% niedrigeren spezifischen Widerstand, als das übliche AlSi-Material, wodurch sich ein niedrigerer Einschaltwiderstand RDSON für das Bauteil ergibt. Weiterhin wurde festgestellt, daß sich eine bessere Überdeckung von und Anpassung an Stufen über den Kanten des Polysilizium-Gates und in den Öffnungen 80, 81, 82 aufgrund der Verwendung der kombinierten Trennschicht und der aus reinem Aluminium bestehenden Schicht ergab.It has next been recognized that because a thin conductive separation layer overlies the upper surface of the die and contacts the source and base regions on the surface of the device, the source electrode need not have a silicon component otherwise present in the device AlSi electrode is present. Thus, the main electrode above the separation layer 100 a layer of pure aluminum (0.999) 101 ( 2 ), which is for example 8 microns thick (non-critical). Furthermore, using the TiW separation layer, pure aluminum is preferred over AlSi because this results in improved compatibility with TiW. This pure aluminum contact has approximately 15% lower resistivity than the standard AlSi material, resulting in a lower on- resistance R DSON for the device. It has also been found that there is better overlaying and conforming to steps across the edges of the polysilicon gate and in the openings 80 . 81 . 82 due to the use of the combined release layer and the pure aluminum layer.

Ein weiterer Vorteil der Verwendung einer siliziumfreien oder aus reinem Aluminium bestehenden Elektrode 101 ergibt sich daraus, daß festgestellt wurde, daß die harten Silizium-Körner oder -Klumpen nicht mehr in der Grenzfläche mit den Oxid-Seitenwänden oder Seietnwand-Abstandselementen gebildet wurden, so daß diese Abstandselemente während periodischer Temperaturschwankungen nicht abgeschliffen wurden.Another advantage of using a silicon-free or pure aluminum electrode 101 It can be seen from the fact that it was found that the hard silicon grains or clumps were no longer formed in the interface with the oxide sidewalls or Seietnwand spacers, so that these spacers were not abraded during periodic temperature fluctuations.

Claims (6)

Halbleiterbauteil mit MOS-Gatesteuerung, mit einer Kontaktstruktur für einen Kontakt an die aktive Oberfläche des Bauteils, wobei die aktive Oberfläche ein Übergangsmuster vom DMOS-Typ in der oberen Oberfläche eines Silizium-Halbleiterplättchens aufweist, und das DMOS-Übergangsmuster aus Isoliermaterial bestehende Seitenwand-Abstandselemente zur Isolation eines Polysilizium-Gates von der Kontaktstruktur aufweist, wobei die Seitenwand-Abstandselemente eine Dicke von ungefähr 0,5 μm an den Seitenkanten der Polysiliziumschicht aufweisen, wobei die Kontaktstruktur eine dünne, metallische, leitende Trennschicht (100), die direkt auf die freiliegenden Oberflächen der Seitenwand-Abstandselemente (63–67) aufgebracht ist, sowie eine relativ dickere aus reinem Aluminium bestehende Aluminium-Schicht (101) aufweist, die über der gesamten aktiven Oberfläche und über der dünnen, metallischen, leitenden Trennschicht aufgebracht ist und mit dieser in Kontakt steht.A MOS gate-type semiconductor device having a contact structure for contact with the active surface of the device, the active surface having a DMOS-type junction pattern in the upper surface of a silicon wafer, and the DMOS transition pattern of insulating sidewall spacers for isolating a polysilicon gate from the contact structure, the sidewall spacers having a thickness of approximately 0.5 μm at the side edges of the polysilicon layer, the contact structure comprising a thin, metallic, conductive separation layer ( 100 ) directly on the exposed surfaces of the sidewall spacers ( 63 - 67 ) is applied, and a relatively thicker made of pure aluminum aluminum layer ( 101 ) which is applied over and in contact with the entire active surface and over the thin metallic conductive separation layer. Halbleiterbauteil nach Anspruch 1, dadurch gekennzeichnet, dass die dünne, metallische, leitende Trennschicht (100) aus TiW besteht.Semiconductor component according to Claim 1, characterized in that the thin, metallic, conductive separating layer ( 100 ) consists of TiW. Halbleiterbauteil nach Anspruch 2, dadurch gekennzeichnet, dass die TiW-Schicht (100) eine Dicke von ungefähr 0,2 μm aufweist, und dass die Aluminiumschicht (101) zumindest zehnmal dicker als die TiW-Schicht ist.Semiconductor component according to claim 2, characterized in that the TiW layer ( 100 ) has a thickness of approximately 0.2 μm, and that the aluminum layer ( 101 ) at least ten times thicker than the TiW layer is. Halbleiterbauteil nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass es weiterhin zumindest einen leitenden Anschlussdraht (110) aufweist, der durch Ultraschall mit der Oberseite der Aluminiumschicht (101) verbunden ist.Semiconductor component according to one of claims 1 to 3, characterized in that it further comprises at least one conductive connecting wire ( 110 ), which is ultrasonically bonded to the top of the aluminum layer ( 101 ) connected is. Halbleiterbauteil nach Anspruch 4, dadurch gekennzeichnet, dass der leitende Anschlussdraht (110) aus Kupfer besteht.Semiconductor component according to claim 4, characterized in that the conductive connecting wire ( 110 ) consists of copper. Verfahren zur Herstellung eines Halbleiterbauteils mit einer Kontaktstruktur für einen Kontakt an die aktive Oberfläche des Bauteils mit MOS-Gatesteuerung, wobei die aktive Oberfläche ein Übergangsmuster vom DMOS-Typ in der oberen Oberfläche eines Silizium-Halbleiterplättchens aufweist, und das DMOS-Übergangsmuster aus Isoliermaterial bestehende Seitenwand-Abstandselemente zur Isolation eines Polysilizium-Gates von der Kontaktstruktur aufweist, wobei die Seitenwand-Abstandselemente eine Dicke von ungefähr 0,5 μm an den Seitenkanten der Polysiliziumschicht aufweisen, wobei eine dünne, metallische, leitende Trennschicht (100) der Kontaktstruktur direkt auf die freiliegenden Oberflächen der Seitenwand-Abstandselemente (60–62, 63–67) aufgebracht wird, und wobei eine relativ dickere aus reinem Aluminium bestehende Aluminium-Schicht (101) über der gesamten aktiven Oberfläche und über der dünnen metallischen, leitenden Trennschicht (100) aufgebracht wird und mit dieser in Kontakt steht.A method of fabricating a semiconductor device having a contact structure for contact with the active surface of the MOS gate-controlled device, the active surface having a DMOS-type junction pattern in the upper surface of a silicon wafer, and the DMOS transition pattern of insulating material Sidewall spacers for isolating a polysilicon gate from the contact structure, the sidewall spacers having a thickness of approximately 0.5 μm at the side edges of the polysilicon layer, wherein a thin metallic conductive barrier layer (US Pat. 100 ) of the contact structure directly onto the exposed surfaces of the sidewall spacers ( 60 - 62 . 63 - 67 ), and wherein a relatively thick pure aluminum aluminum layer ( 101 ) over the entire active surface and over the thin metallic conductive separation layer ( 100 ) is applied and in contact with this.
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