DE10084066D2 - Circuit arrangement and method for providing clock signals - Google Patents

Circuit arrangement and method for providing clock signals

Info

Publication number
DE10084066D2
DE10084066D2 DE10084066T DE10084066T DE10084066D2 DE 10084066 D2 DE10084066 D2 DE 10084066D2 DE 10084066 T DE10084066 T DE 10084066T DE 10084066 T DE10084066 T DE 10084066T DE 10084066 D2 DE10084066 D2 DE 10084066D2
Authority
DE
Germany
Prior art keywords
clock signals
circuit arrangement
providing clock
providing
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10084066T
Other languages
German (de)
Inventor
Imre Hipp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE10084066T priority Critical patent/DE10084066D2/en
Application granted granted Critical
Publication of DE10084066D2 publication Critical patent/DE10084066D2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Information Transfer Systems (AREA)
DE10084066T 1999-12-22 2000-11-10 Circuit arrangement and method for providing clock signals Expired - Fee Related DE10084066D2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10084066T DE10084066D2 (en) 1999-12-22 2000-11-10 Circuit arrangement and method for providing clock signals

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19962217 1999-12-22
PCT/DE2000/003938 WO2001047160A2 (en) 1999-12-22 2000-11-10 Circuit arrangement and method for clock signal generation
DE10084066T DE10084066D2 (en) 1999-12-22 2000-11-10 Circuit arrangement and method for providing clock signals

Publications (1)

Publication Number Publication Date
DE10084066D2 true DE10084066D2 (en) 2003-01-30

Family

ID=7933939

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10084066T Expired - Fee Related DE10084066D2 (en) 1999-12-22 2000-11-10 Circuit arrangement and method for providing clock signals

Country Status (3)

Country Link
CN (1) CN1435021A (en)
DE (1) DE10084066D2 (en)
WO (1) WO2001047160A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10329116B3 (en) * 2003-06-27 2004-12-09 Siemens Ag Time provision method for data processing unit in industrial automation process has redundant clock signals provided by digital counters which count in opposite directions
CN112769518B (en) * 2021-01-22 2022-09-13 上海宽域工业网络设备有限公司 Serial port time sending system and method with second punctual edge

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
AU677832B2 (en) * 1993-06-07 1997-05-08 Alcatel N.V. Hitless switch arrangement
US5666330A (en) * 1994-07-21 1997-09-09 Telecom Solutions, Inc. Disciplined time scale generator for primary reference clocks
US6078595A (en) * 1997-08-28 2000-06-20 Ascend Communications, Inc. Timing synchronization and switchover in a network switch
CA2217840C (en) * 1997-10-09 2005-05-03 Northern Telecom Limited Synchronization system multiple modes of operation

Also Published As

Publication number Publication date
WO2001047160A3 (en) 2002-02-07
CN1435021A (en) 2003-08-06
WO2001047160A2 (en) 2001-06-28

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee