DE10058966A1 - Charging memory cells involves selecting memory cells and carrying out refresh process only for selected memory cells; memory cells can be selected by area of memory - Google Patents

Abstract

The method involves supplying the memory cells (14) with electrical charge at defined time intervals during a refresh process. Memory cells are selected and the refresh process is only carried out for the selected memory cells. The memory (15) is divided into defined areas of memory cells, an area is selected and a refresh process carried out only for the cells in this area. Independent claims are also included for the following: a memory component with a memory field.

Description

The invention relates to a method for refreshing Spei cher cells of a memory according to the preamble of the patent claims 1. Furthermore, the invention relates to a memory Building block with memory cells according to the preamble of the patent claim 4.

Dynamic memory modules have the advantage that for the formation of the memory cells require less storage space than with the non-dynamic memory chips. However, there is a disadvantage to dynamic memory chips in that the memory cells regularly with electrical Charge must be supplied so that the information contained in the memory cells is stored, is not lost. so with is a relatively large power requirement when operating dy Named memory modules required. This is in particular This is disadvantageous when using mobile phones because the Power supply to the mobile phone is limited amount of the product.

The object of the invention is to provide a method for Operating memory cells and a memory module with To provide memory cells in which the power requirement for Operating the memory chip or for charging the memory cell is reduced.

The object of the invention is characterized by the features of the claim 1 or solved by the features of claim 4.  

A major advantage of the invention is that only a part of the memory cells in a refresh process Charge is supplied. In this way, use of the Memory module guaranteed and still electricity saved that not all memory cells are supplied with power only selected memory cells. So that is ge ensures that, for example, when using the memory building blocks in a mobile radio telephone reduces the power requirement a dynamic memory module is still used can be.

Further advantageous embodiments of the invention are in the dependent claims. Preferably is a Memory module divided into predetermined areas and it only selected areas of the memory Subjected to refresh process. By using areas is the addressing of the memory to be powered cells simplified.

The memory cells are preferably refreshed Word lines of selected areas of a memory arrangement read out and again with the read out information wrote In this way a simple procedure for Charging the memory cells provided.

In a preferred embodiment of the memory chip is a charging circuit with a charging clock generator see, the charging clock generator ver with a bit decoder is bound and supplies the bit decoder with a charging cycle. from depending on the charging cycle, the bit decoder connects the corresponding ones Bit lines with a voltage source. That way provided a simple embodiment with which one  specified selection of bit lines supplied with voltage becomes.

It is also advantageous to use the charging clock generator via ei to control a counter, depending on an output signal of the counter of the charging clock generator to the bit decoder Charging cycle feeds. The use of a counter allows a simple embodiment to get predetermined addresses from Bit lines for loading the corresponding memory cells to choose.

In a preferred embodiment, the bit decoder connects the bit lines in a predetermined order one after the other the in a given period of time with the voltage source, if at the beginning of the period a charging signal from the charging generator is applied. In this way, a simple device for selective charging of memory cells provided.

In a further advantageous embodiment, the toughness ler connected to a register, the counter only then outputs a charging signal to the charging clock generator if that Register has a predetermined value. So is through simple programming of the register a selection of addresses possible for which a charging cycle is given.

The invention is explained in more detail below with reference to the figures purifies. Show it

Fig. 1 shows a section of a dynamic memory device,

Fig. 2 is a signal sequence of the counter,

Fig. 3 shows a signal sequence of the charge clock signal, and

Fig. 4 is a schematic representation of a memory field in which only the first two bit lines are charged with a charge.

Fig. 1 shows schematically a part of a dynamic memory chip 15 , which has a memory array 11 with memory cells 14 . For permanent storage of information, the memory cells 14 must be regularly rewritten with the information stored in the respective memory cell. The information is read out via the word lines of the memory cells and rewritten via the word lines. This process is called a refresh process. The charging of the memory cells 14 is carried out by a corresponding voltage supply of rows 12 and column lines 13th The memory field 11 is constructed in the form of a matrix-shaped memory which has a large number of memory cells 14 . Row lines 12 and column lines 13 are provided for reading in and reading out data from the memory cells 14 . The row lines 12 and column lines 13 are each arranged at right angles to one another and a storage cell 14 is formed at the intersection between a row line and a column line. The row lines 12 are connected to a row decoder 6 and the column lines 13 are connected to a column decoder 7 . The reading in and reading out of data from the memory cells 14 is not the subject of the invention and is therefore not explained in more detail. Corresponding switching elements and components for reading in and reading out the data are also not shown for reasons of clarity.

The memory module 15 has a control unit 1 , which is connected via a first control line 16 to a charging clock generator 2 , a second control line 17 to a first oscillator 3 , a third control line 18 to a register 5 and a fourth control line 19 to the column decoder 7 is. The charging generator 2 has a connection 20 via which the charging clock generator 2 is supplied with a voltage supply. In addition, the charging clock generator 2 is connected via a fifth control line 21 and a sixth control line 22 to the first oscillator 3 and a counter 4 . The first oscillator 3 is connected via a clock line 23 to a clock input of the counter 4 . The counter 4 has a clock output, the device via a second Taktlei 24 to a clock input 25 of the charging clock generator 2 is closed. In addition, the counter 4 is connected via a query input to a signal line 26 , which is led to the re register 5 .

The charging clock generator 2 has a charging clock output 27 , which is fed with a third clock line 28 to a second clock input 31 of the row decoder 6 . The row decoder 6 is connected to a first voltage source 9 and to a second oscillator 10 . The column decoder 7 is connected to a second voltage source 8 .

The charging of the memory cells 14 at predetermined times is explained in more detail below with reference to FIG. 1. The memory cells 14 are written at predetermined times with the information that is already stored in the memory cells. For this purpose, the date is first queried via the row line of a memory cell and then the date is written to the memory cell again via the row line. The writing is carried out by supplying the memory cell with an electrical charge so that the information stored in the memory cells 14 , which is stored in the form of charge, is not lost. The regular description of the memory cells 14 is necessary because the charge stored in the memory cells is lost due to leakage currents after a predetermined period of time. For this reason, the control unit 1 sends a start signal to the charging clock generator 2 via the first control line 16 at predetermined times. After receiving the start signal, the charging clock generator 2 gives a start signal to the first oscillator 3 . The first oscillator 3 then outputs clock signals with fixed time intervals to the counter 4 . Simultaneously with the start signal, the charging clock generator 2 also outputs a start signal to the counter 4 . The counter 4 counts up a predetermined number of addresses according to the frequency of the clock signals provided by the first oscillator 3 . The number of addresses depends on the number of bit lines that are to be supplied with power. In example, five clock frequencies of the first oscillator 1 are counted before the counter 4 increases its counter reading by one. Each time the counter is increased, the counter 4 issues a load signal to the clock input 25 of the load clock generator 2 if the register 5 is assigned the value one. If the register 5 is assigned the value zero, the counter 4 does not give a charging signal to the charging clock generator 2 .

The charging clock generator 2 gives a charging clock signal via the third clock line 28 to a two-th clock input 29 of the row decoder 6 on receipt of a charging signal. The row decoder 6 is connected to the control unit 1 via a seventh control line 29 . When a charging process is started, the control unit 1 also sends a start signal to the row decoder 6 . The row decoder 6 then begins a charging process in which the row decoder 6 runs the individual row lines 12 one after the other in a predetermined sequence, reads the information from all the memory cells of a row line and writes the same information back into the memory cells. To write the information, the row line is connected to the first voltage source 9 for a given period of time when a charging clock signal is simultaneously supplied by the charging clock generator. The speed at which the individual row lines 12 are traversed is determined on the basis of the time base provided by the second oscillator 10 . When reading out and rewriting the read information, all column lines are activated.

For a further understanding, the functioning of the charging process is explained in more detail using the signal sequence in FIG. 2. In Fig. 2, the counting behavior of the counter 4 is shown in the characteristic curve A. The counter 4 counts up to a predetermined maximum number and then jumps back to the value zero and sets an internal count value by the value +1. For example, the counter 4 starts counting at the point in time t0 until a predetermined maximum value is reached at the point in time t1 and the value jumps back to zero. The internal count value is increased again by +1. Subsequently, the counter 4 starts counting from zero again at the time t1 and repeats the process until it jumps back to the value zero at the time t2. Each time the maximum number changes to zero, counter 4 checks which value is stored in register 5 . The value of register 5 is shown in characteristic curve B in FIG. 2. At time t1, for example, the register 5 has the value +1. If the counter 4 recognizes that the register 5 has the value +1, a clock signal is emitted to the charging clock generator 2 at the time t3. The clock signals are shown in the characteristic curve C of FIG. 2a. The charging clock generator 2 outputs a charging clock signal, which is shown in FIG. 2a in the characteristic curve D, to the row decoder 6 . In the exemplary embodiment described, the charging clock generator 2, after receiving the clock signal shortly after the time t3, outputs a charging clock signal to the row decoder 6 at the time t4.

The counter 4 checks accordingly at time t2 when changing from the maximum number to the value zero, which value is stored in register 5 . At time t2, register 5 has the value -1 (characteristic curve B). As a result, the counter 4 does not output a clock signal to the charging clock generator 2 . Since the charging clock generator 2 does not receive a clock signal, the charging clock generator 2 does not give a charging clock signal to the row decoder 6 at the time t2.

Counter 4 starts up again and changes back to zero at time t5. At the same time, counter 4 checks at time t5 which value register 5 has. At time t5, the register has the value +1, so that the counter 4 shortly after the time t5 at the time t6, a clock signal (characteristic curve C) to the charging clock generator 2 . After receiving the clock signal shortly after the time t6, the charging clock generator 2 outputs a charging clock signal (characteristic curve D) to the row decoder 6 at the time t7. After reaching a maximum internal count value, which corresponds to the number of row lines, the counter 4 switches off.

FIG. 3 shows the dependency between the charging clock signal (characteristic curve D) and the charging process that the row decoder 6 carries out. After the start signal for performing a charging process, the row decoder 6 travels a predetermined number of row lines and reads out the information from the memory cells connected to the row line and writes the information back into the memory cells by the corresponding row line with the is connected to the first voltage source 9 when a charging clock signal is applied to the second clock input 31 . In the characteristic curve E in FIG. 3, the time periods are shown in which the row decoder 6 are checked for a number line 12, the signal at the second clock input 31. The addresses 30 of the row lines 12 are shown over the periods. For example, the row decoder 6 checks between the times t1 and t2 for the row line 12 with the address 1 the second clock input. Under the characteristic curve E, the characteristic curve D represents the charge cycle signal of the charge cycle generator 2 . In the exemplary embodiment described, the row decoder 6 receives a charging clock signal in the period t1 and t2, so that the row decoder 6 carries out the read-out process and rewrites the information into the memory cells of the row line by the row line 12 with the address 1 for a defined period T with the first voltage source 9 connects. The time periods T are also shown in a characteristic curve F in FIG. 3. The row decoder 6 thus carries out a refresh operation for the row line 12 with the address 1 at the time t3 up to the time t4.

The row decoder 6 then checks in the period from t5 to t6 for the row line 12 with the address 2 whether a charging clock signal is present at the second clock input 31 . This is the case so that the row decoder 6 for the row line 12 with the address 2 carries out a refresh process from the period t7 to t8.

In this way, a predetermined number of row lines 12 are checked in a defined sequence and possibly subjected to a refresh process. The number of series lines 12 and the order of the series line 12 is preferably determined by the control unit 1 .

For example, the row line 12 with the address 3 is not subjected to a refresh process and is not connected to the first voltage source, since in the period from t9 to t10 in which the row decoder 6 checks the second clock input 31 for a charging clock signal, no charging clock generator 2 produces any Charge clock signal is supplied. The same applies to row line 12 with address 5 . The row lines with the addresses 4 and 6, however, are again subjected to a refresh process and connected to the first voltage source, and therefore the information which is stored in the memory cells 14 connected to the row lines is still stored.

The counting frequency of the counter 4 is matched to the monitoring times in which the row decoder 6 monitors the second clock input 31 for a given column line 12 , so that a correct refresh operation of the memory cells 14 can be carried out.

FIG. 4 schematically shows the definition of an area of the memory field 11 which is charged when refreshing, ie when the memory cells 14 are being charged. In FIG. 4, the memory array 11 is shown schematically, wherein the memory array is subdivided into individual address ranges. The value of an assigned register determines whether the corresponding address area is loaded or not during the loading process. The row decoder 6 is shown schematically on the right side of the memory field 11 . Opposite, on the left side of the memory field 11, the address registers 32 are shown schematically, via which a selection of the areas to be loaded can be made. Over the memory field 11 , the column registers 33 for addressing the column lines 13 are shown schematically. However, the column lines 13 are all activated during the charging process, that is to say connected to a voltage of a predetermined value, so that the column registers 3 are not changed for the selection of the areas. The memory field 11 represents a 64 megabit memory block, a transverse row having a memory space of 4 megabits. In the example shown, the memory field 11 is divided into an upper and a lower area. Due to the corresponding assignment of the address register 32 , only the two top rows of the upper and the lower memory field are supplied with charge during a refresh process. In this way, electricity is saved, whereby it is accepted that the areas of the storage field which are not supplied with power lose their charge and thus their information.

However, the control unit 1 can also select any other areas of the memory field 11 that are not to be subjected to a refresh process. In an extreme case, individual selected memory cells 14 can also be specified which are only to be subjected to a refresh process individually. Usually, the areas that are accessed first when reading in and reading out data are selected. These areas are usually the first rows of an upper or lower half of a memory array 11 .

The essential idea of the invention is to carry out a refresh process with only one part of a memory array 11 . This saves electricity and ensures an emergency function of the memory array 11 . In particular, use of the method according to the invention and the device according to the invention in devices which have only a limited charge stock is advantageous. These are, for example, mobile phones and mobile computers. For example, it can also be provided that the state of charge of the battery or the rechargeable battery is checked and, after detection of a drop in the voltage, switched to an emergency mode in which only selected areas of the storage field 11 are supplied with current. This function can be used in any electrical device that has a memory field 11 , the memory cells of which must be supplied with charge in order to hold the information.

LIST OF REFERENCE NUMBERS

1

control unit

2

Load clock generator

3

first oscillator

4

counter

5

register

6

row decoder

7

column decoder

8th

second voltage source

9

first voltage source

10

second oscillator

11

storage box

12

row lines

13

column lines

14

memory cell

15

Dynamic memory block

16

first control line

17

second control line

18

third control line

19

fourth control line

20

connection

21

fifth control line

22

sixth control line

23

clock line

24

second clock line

25

clock input

26

signal line

27

Load clock output

28

third clock line

29

seventh control line

30

address

31

second clock input

32

address register

33

column register

Claims (8)

1. A method for performing a refresh process of memory cells ( 14 ) of a memory, wherein the memory cells ( 14 ) are supplied with an electrical charge during a refresh process, characterized in that
that memory cells ( 14 ) are selected, and
that only a refresh process is carried out on the selected memory cells ( 14 ). 2. The method according to claim 1, characterized in that the memory ( 15 ) is divided into predetermined areas of memory cells ( 14 ), that an area is selected, and that a refresh operation is carried out only on the memory cells of the area. 3. The method according to any one of claims 1 or 2, characterized in that during the refresh process all column lines ( 13 ) of a memory arrangement are supplied with voltage, that only from row lines ( 12 ) of the selected areas or from selected memory cells ( 14 ) in the Information stored in memory cells is read out and rewritten by supplying a voltage. 4. Memory module with a memory field ( 11 ), the memory cells ( 14 ), with a charging circuit ( 2 , 4 , 5 , 6 , 9 ), which is connected to the memory cells ( 14 ), and the information at predetermined intervals reads the memory cells ( 14 ) and writes the same information back into the memory cells by applying voltage, characterized in that
that a control unit ( 1 , 5 , 4 ) is provided,
that the control unit ( 1 , 5 , 4 ) selects memory cells ( 14 ), and
that the charging circuit ( 2 , 4 , 5 , 6 , 9 ) only reads the information stored in the selected memory cells ( 14 ) from the selected memory cells ( 14 ) and writes them back into the selected memory cells ( 14 ). 5. Memory device according to claim 4, characterized in that a memory cell ( 14 ) is connected to a row and column line ( 12 , 13 ), with a date in the connected via the row and column line ( 12 , 13 ) memory cell (14) inscribed on or off which is in closed storage cell (14) can be read out, being supplied via the row and column line (12, 13) the SpeI cherzelle (14) to charge to a row decoder (6) and a Column decoders ( 7 ) that control access to the row or column lines ( 12 , 13 ), that the charging circuit has a charging clock generator ( 2 ), that the charging clock generator ( 2 ) is connected to the row decoder ( 6 ) and the row decoder ( 6 ) feeds a charging cycle that the row decoder is connected to a voltage source ( 9 ) and performs a refresh process on the row lines depending on the charging cycle. 6. Memory block according to claim 5, characterized in that the charging clock generator ( 2 ) with a counter ( 4 ) is connected, that the counter ( 4 ) is connected to the control unit ( 1 ), and that the charging clock generator ( 2 ) predefined times outputs an output signal when the counter ( 4 ) outputs a load signal to the charge clock generator ( 2 ). 7. The memory chip as claimed in claim 6, characterized in that the row decoder ( 6 ) for the row lines ( 12 ) carries out a refresh operation in a predetermined sequence one after the other in each case in a predetermined period of time when a charging cycle of the charge generator ( 2 ) is present. 8. Memory block according to one of claims 6 or 7, characterized in that the counter ( 4 ) is connected to a register ( 5 ), that the register ( 5 ) is connected to the control unit ( 1 ), and that the counter ( 4 ) a charging signal to the charging clock generator ( 2 ) when the register ( 5 ) has a predetermined value at the time of delivery.