DE10054339A1 - Switching regulator has first switch for connecting inductive storage element to input terminals and second switch for short circuiting capacitive element in series with inductive element - Google Patents

Abstract

The device has input terminals EK1,EK2) for applying an input voltage, output terminals (AK1,AK2) for providing an output voltage to a load (RL), an inductive storage element (L) and a capacitive element (C2) in series with it, a first switch (S1) for connecting the storage element to the input terminals and a second switch (S2) for short circuiting the capacitive element. Independent claims are also included for the following: a method of converting an input voltage to an output voltage.

Description

The present invention relates to a switching regulator.

The job of a switching regulator is to make a uniform one output voltage into a uniform output voltage for ver supply of a load. The output voltage should be there regardless of changes in input voltage and / or Load changes kept at least approximately constant become.

A distinction is made between so-called "buck Converter "that are able to from the input voltage to generate an output voltage whose amplitude is smaller than that of the input voltage, and so-called "Boost Con verter ", which turns the input voltage into an output voltage generate with greater amplitude.

The basic structure of a buck converter is in Stengl / Tihanyi: "Power MOS FET Practice", Pflaum Verlag, 1992, page 176, Figure 8.19.7, the buck converter has input clamps for applying the input voltage and Output terminals at which the output voltage can be tapped is on. Between the input terminals is a MOSFET trained switch, a coil and a capacitor in Series connected. The output voltage is above that Capacitor on. A parallel to the series connection from Spu le and capacitor switched diode serves as a freewheel ment for the coil current with the switch open.

The switch is clocked in accordance with an animation signal opened and closed, with the output voltage across the Clock frequency and / or the duty cycle can be set can.  

Figure 8.19.8 of the publication mentioned shows a boost Converter, which is also an input terminal for connecting the on output voltage and output terminals to provide the off has output voltage. There is one on the input terminals Series connection of a coil and one designed as a MOSFET ten switch connected, being parallel to the switch a diode and a coil are connected in series. The out output voltage is also above that with the boost converter Capacitor can be tapped.

There is a need for switching regulators that are capable are a desired output voltage from both a small input voltage as well as from a larger input To be able to generate voltage to the switching regulator as possible versatile to use for various input voltages can.

It was proposed to use a buck converter and a Bo ost converter to combine, the boost converter for Input voltages up to a predetermined first amplitude the value of the input voltage generates the output voltage and the buck converter starting from a predetermined second ampli the output voltage generates the output voltage. In order to operate the boost converter and the Avoiding buck converters is the second amplitude value, from which the buck converter starts, larger than the first Amplitude value from which the boost converter stops. For intermediate values of the input voltage form the Input voltage directly the output voltage. The exit however, voltage cannot be kept constant by this the.

The aim of the present invention is to provide a switching regulator to make available, which is able to a given generate the same output voltage from an input voltage, which are greater, less than or equal to the output voltage can.  

This goal is achieved by a switching regulator according to the characteristics of claim 1 solved.

Advantageous embodiments of the invention are the subject of subclaims.

The switching regulator according to the invention has input terminals for Apply an input voltage, output terminals ready set an output voltage for a load, an inductive Storage element and a capacitance connected in series ves memory element, a first switch for connection of the inductive storage element to one of the input terminals and a second switch for short-circuiting the capacitive Storage element.

The switching regulator according to the invention can be a buck converter be driven when the second switch is continuously open and the first switch clocked closed and opened becomes. And the switching regulator according to the invention can be used as a boost Converter operated when the first switch is on is closed and the second switch is opened and clocked is closed.

However, the switching regulator is preferably operated in such a way that that with each shift, both the first and the second switches are closed, the output span on the ratio of the duty cycles of the first and second switch is regulated.

According to one embodiment of the invention, a first is control circuit for providing a first control signal nals for the first switch and a second control scarf device for providing a second control signal for the second switch provided. The first and second control circuit is preferably a from the output voltage dependent output voltage signal and one from a current  through the coil dependent current signal to provide the Control signals supplied.

The first and second control circuits have one Embodiment of the invention each a Regelver stronger to compare the output voltage signal with a first or second reference signal and ready setting a first or second control signal. The first and second control signals are preferably with the current signal or one dependent on the current signal gene signal compared to a drive signal for a Form flip-flop, being at the output of the first and drive circuit existing first flip-flop first control signal and at the output of the second Drive circuit existing second flip-flop second control signal is available. Preferably the flip-flops will follow at regular intervals Provided a clock signal and depending on Ver same of the first and second control signal with the Current signal reset.

With such a switching regulator, with the flip-flops in the control circuits in accordance with a clock signal are set, both switches start simultaneously conduct. The rule formed in the control circuits signals, according to which the flip-flops are reset and so that the switches are locked, so open otherwise matched that the second switch timed always locks in front of the first switch.

When the first switch is closed, the current rises the coil linearly, the slope of the current is dependent on the input voltage. The stream signal thus contains information about the value the input voltage, the duty cycle of the first th and second switch of the current signal and thus depends on the input voltage. The reinforcement  of the first control amplifier is preferably greater than that of the second control amplifier, whereby the first Re gel signal is always greater than the second control signal. The first and second switches are activated such that the switches after switching on for so long remain closed until the current signal the respective Control signal exceeds, it is ensured that the first switch always longer than the second switch ge is closed. In such a switching regulator "domi "Buck operation.

The present invention is hereinafter described tion examples explained in more detail with reference to figures. It shows:

Fig. 1 block diagram of a first embodiment of a switching regulator according to the invention;

Fig. 2 switching regulator of Figure 1 with a detailed th representation of control circuits for Be provision of control signals for the switch.

FIG. 3 is time profiles of some in Fig. 3 recorded signals,

Fig. 4 course of the duty cycle of the first and second switches ( Fig. 4a) compared to the input voltage ( Fig. 4b);

Fig. 5 switching regulator according to another embodiment of the invention.

In the figures, unless otherwise stated ben, same reference numerals, same parts with the same Importance.  

Fig. 1 shows a first embodiment of an inventive switching regulator for converting an input voltage Uin into an output voltage Uout. The switching regulator has input terminals EK1, EK2 for applying the input voltage Uin and output terminals AK1, AK2 for providing the output voltage Uout. A load, which is shown in the exemplary embodiment as an ohmic resistor R _L , can be connected to the output terminals AK1, AK2 for supply with the output voltage Uout. The switching regulator further has an inductive storage element L, in the present case a choke, which is connected in series with a first switch S1, via which the choke L can be connected to the first input terminal EK1. In series with the inductor L, a capacitive storage element C2, in the present case, a capacitor, is also connected, via which the output voltage Uout can be tapped. A diode D3 is also connected between the inductor L and the capacitor C2, a second switch S2 being connected in parallel with the series connection of this diode D3 and the capacitor C2. The diode D3 prevents the capacitor C2 from being discharged via the switch S2 when the second switch S2 is closed. In parallel to the series connection of the inductor L and the second switch S2, a further diode D2 is also connected, which serves as a freewheeling diode for the inductor L.

At the input terminals EK1, EK2 there is still an equal judge arrangement consisting of a series connection of a Diode D1 and a capacitor C1 switched, the task it is short-term fluctuations in the input voltage Uin compensate. This rectifier arrangement D1, C1 can to be dispensed with if an ideal DC voltage as an output voltage Uin is available. In the present case there is a DC voltage across the capacitor C1, which the Input voltage Uin minus the forward voltage of the Dio de corresponds to D1.  

The switching regulator shown can be operated as a buck converter ben when the second switch S2 is permanently open and the first switch S1 is clocked open and closed will. Take the inductor L and the storage capacitor C2 as long as power on, as long as the first switch S1 is closed sen, the throttle L when subsequently open Switch at least part of the energy stored in it relays to the storage capacitor C2. The initial chip voltage Uout is lower than the On for a Buck converter output voltage Uin. The diode D2 closes when the ers th switch S1 the circuit between the inductor L, the Diode D3 and capacitor C2.

The switching regulator shown can also be used as a boost converter be operated when the first switch S1 is continuously ge is closed and the second switch S2 is closed clocked and is opened. The throttle L takes when closed second switch S2 energy and gives at least one Part of the absorbed energy when opened second switch S2 via the diode D3 on the storage probes sator C2. The output voltage Uout is in operation of the switching regulator as a boost converter larger than the on output voltage Uin.

Although the switching regulator according to the invention due to its on build exclusively as a buck converter or exclusively can be operated as a boost converter, be the first and second switches S1, S2 are preferably controlled in such a way that with each switching operation both switches S1, S2 are closed be, the ratio of the duty cycles of the first and second switch S1, S2 depending on the input span voltage Uin varies and the duty cycle of the second Switch S2 always less than the duty cycle of the first Switch S1 is. In this way, by means of the invent The switching regulator according to the invention has a constant output voltage Uout are generated from an input voltage Uin, the  Input voltage Uin greater, less than or equal to the off output voltage Uout can be.

The switching regulator according to the invention has a first control circuit AN1 for providing a first control signal AS1 for the first switch S1 and a second control scarf device AN2 for providing a second control signal AS2 for the second switch S2. The control circuits AN1, AN2 is a function of the output voltage Uout Output voltage signal US supplied, the drive circuits AN1, AN2 the control signals AS1, AS2 dependent from the output voltage signal US to produce at a change of the output voltage Uout by changing the switch-on the first and second switches S1, S2 take up the energy took the switching regulator and thus the output voltage Uout readjust. To provide the output voltage signal US is a measuring arrangement MA1 between the output terminals AK1, AK2 switched, which in the exemplary embodiment a Rei Connection of two resistors R1, R2, the Output voltage signal US as voltage on one of the two Resistors R1, R2 common taps can be tapped.

The control circuits AN1, AN2 is still a current signal nal IS supplied, which flows from one in the switching regulator current Iin is dependent. The current signal IS is through a current measuring arrangement MA2 is provided, which the in the Switching regulator measures current Iin flowing.

The first and second switches S1, S2 are switched on Control signals AS1, AS2 preferably controlled such that they close at the same time and that the second switch S2 opens before the first switch S1, with the Ratio of the duty cycle of the first switch S1 to that Duty cycle of the second switch S2 the output voltage Uout can be set depending on the input voltage Uin can. If the second switch S2 is not closed at all, then if the switching regulator works as a buck converter, it remains  second switch S2 as long as the first switch S1 turned on switches, the switching regulator works as a boost Converter. If the switching regulator is operated such that the turn on both switches S1, S2 simultaneously and that the second switch S2 opens before the first switch S1, see right it results in a kind of "mixed-mode" that makes it possible approximately constant output voltage Uout from a to form larger or smaller input voltage Uin.

Fig. 2 shows the switching regulator according to FIG. 1, the construction of the control circuits AN1, AN2 being shown in greater detail.

Each drive circuit AN1, AN2 in the embodiment play a control amplifier RV1, RV2, which each Output voltage signal US is supplied. The control amplifier RV1, RV2 are designed as integrating control amplifiers and compare the output voltage signal US with each a reference signal Vref1, Vref2, with each Re gel amplifier RV1, RV2 a control signal RS1, RS2 is present, which is the time average of the difference between the respective reference signal Vref1, Vref2 and the output span voltage signal US corresponds.

The control amplifiers RV1, RV2 each have a comparator K1, K2 downstream, the Mi nus input of the comparator K1, K2 at the output of each current control amplifier RV1, RV2 applied control signal RS1, RS2 is fed. At the plus inputs of comparators K1, K2 is provided by the second measuring arrangement MA2 te current signal IS.

The comparators K1, K2 are each followed by a memory circuit RSF1, RSF2, which in the exemplary embodiment shown in FIG. 2 are designed as RS flip-flops. A comparator output signal KS1 of the comparator K1 is a reset input of the RS flip-flop RSF1 in the first control circuit AN1 and a comparator output signal KS2 of the comparator K2 is a reset input of the RS flip-flop RSF2 in the control circuit AN2 fed. There is also a clock generator TG which provides a clock signal TS which is fed to set inputs of the RS flip-flops RSF1, RSF2. At an output Q of the RS flip-flop RSF1 of the first control circuit AN1, the first control signal AS1 stands for the first switch S1 and at an output Q of the RS flip-flop RSF2 of the second control circuit AN2, the second control signal AS2 stands for the second switch S2 available.

The circuit arrangement according to FIG. 2 is explained below using the signal curves shown in FIG. 3. Fig. 3a shows a temporal section from the course of the current signal IS, and the first and second control signals RS1, RS2. FIG. 3b shows a cut-chen zeitli the course of the first drive signal AS1. Fig. 3c shows a time segment of the course of the second drive signal AS2 and Fig. 3d shows a cut-chen zeitli the course of the clock signal TS.

If the first and second flip-flop RSF1, RSF2 are set at the time t0 at the start of a pulse of the clock signal TS, the control signals AS1, AS2 assume a high level and the two switches S1, S2 are closed. In this regard, it should be noted that it is assumed for the following description that the two switches S1, S2 each conduct at a high level of the control signal AS1, AS2 and block at a low level. Such switches are, for example, n-type MOS-FETs, the drive signals AS1, AS2 being applied to the gate electrodes of these components when using such MOS-FETs. Of course, the switching regulator according to the invention can also be implemented with switches S1, S2, which conduct at a low level and block at a high level. The control signals AS1, AS2 shown in FIG. 3 are to be vertically deflected in a known manner when using such switches.

If the first and second switches S1, S2 are controlled by the control signals AS1, AS2 from time t0, approximately the entire input voltage Uin is present across the inductor L. In the representation of the course of the current signal IS in Fig. 3a it is assumed that the switches S1, S2 were temporarily closed before the time t0, so that the inductor L could absorb current. It is assumed that this current is not yet completely commutated at time t0, so that the current Iin flowing in the switching regulator, or the inductor L, or the current signal IS does not start at zero at time t0 but at a value which corresponds to that Coil current I _L corresponds shortly before the time t0. Before the first switch S1 closes, this coil current I _{L is} taken over by the freewheeling diode D2.

Starting from the initial value at time t0, the input current Iin, which corresponds to the coil current I _L when the first switch S1 is closed, increases linearly over time, the slope of the coil current I _L , and thus of the current signal IS, being proportional to that via the inductor L applied voltage, and thus neglecting the diode D1 is proportional to the input voltage Uin. If the current signal IS reaches the value of the second control signal RS2 at a time t1, the output signal KS2 of the second comparator K2 assumes a high level, which resets the second RS flip-flop RSF2, as a result of which the second control signal AS2 is one Assumes low level and blocks the second switch S2. When switch S2 is open, the voltage across the Dros sel L is reduced, so that the coil current I _L increases more slowly than before from the time t1.

The current signal IS reaches the value at a time t3 of the first control signal RS1, the output signal KS1  of the first comparator K1 to a high level, which is the first Flip-Flop RSF1 resets, so that the first drive signal AS1 assumes a low level and the first switch S1 blocks. The current supply from the input terminals EK1, EK2 interrupted to the choke L1 and the current signal IS drops to zero.

The switch-on times at which the first and second switches ter S1, S2 are switched on simultaneously are fixed in the switching regulator according to FIG. 2 by the clock signal TS. The period of this clock signal TS is Tt. The duty cycle Ta1 of the first control signal AS1 is dependent on the current signal IS and the first control signal RS1. The duty cycle Ta2 of the second drive signal AS2 depends on the current signal IS and the second control signal RS2. If the output voltage Uout drops as a result of a load increase or a decrease in the input voltage Uin, then the voltage signal US also drops and the difference between the first reference signal Vref1 and the output voltage signal US and the difference between the second reference signal Vref2 and the output voltage signal US increases , The integrating control amplifier RV1 thereby increases the control signal RS1 and, due to the integrating regulating amplifier RV2, the second control signal RS2 thereby increases. If the output voltage Uout increases due to a load drop or an increase in the input voltage Uin, the control signals RS1, RS2 decrease. An increasing first control signal RS1 causes the time period Ta1, up to which the current signal IS reaches the first control signal RS1, whereby the switch S1 remains closed for a longer time. An increasing second control signal RS2 has the effect that the time period Ta2 until which the current signal IS reaches the second control signal RS2 is extended, as a result of which the second switch S2 remains closed for a longer time. The longer the first switch S1 remains closed, the more energy the inductor L can absorb and give to the storage capacitor C2, whereby the output voltage Uout and the output voltage signal US rise until the output voltage Uout adjusts itself again to the desired value Has.

The current signal IS influences the duty cycles Ta1, Ta2 of the first and second switches S1, S2 in that the Current signal IS stronger with a large input voltage Uin than increases with a small input voltage Uin. Je steep ler the current signal IS rises, the sooner it reaches that Current signal IS the value of the first and second control signals RS1, RS2 and all the earlier become the first and second scarf ter S1, S2 switched off again after switching on.

The first and second control amplifiers RV1, RV2 are of this type coordinated that the first control signal RS1 always is greater than the second control signal RS2 to prevent that the duty cycle Ta1 of the first switch S1 is shorter than is the duty cycle Ta2 of the second switch S2. Is to the gain of the first control amplifier RV1, preferably by a factor of 3, greater than the gain of the second re gel amplifier RV2. In addition, the second reference voltage Vref2 less than the first reference voltage Vref1. The latter causes the second control signal RS2 when falling off output voltage Uout only after the first control signal RS1 increases.

The period of a switching operation in the switching regulator shown is determined by the period Tt of the clock signal TS. The ratio of duty cycle and period is referred to as the duty cycle of the respective switch. The ratio DC1 = Ta1 / Tt denotes the duty cycle of the first switch S1 and the ratio DC2 = Ta2 / Tt denotes the duty cycle of the second switch S2. FIG. 4a shows the time course of the first and second duty-cycles DC1, DC2 for an input voltage Uin, the zeitli cher curve is shown together with the output voltage Uout including in Fig. 4b.

At a maximum value Uin _{max of} the input voltage Uin, the first and second duty cycles DC1, DC2 each assume a minimum value, ie the first and second switches S1, S2 must remain relatively short-circuited to ensure sufficient energy consumption by the inductor L to provide the off to ensure output voltage Uout at the output terminals. If the output voltage Uin falls below the maximum value Uin _max , the duty cycle DC1 of the first switch S1 begins to rise, while the duty cycle DC2 of the second switch S2 does not increase or only increases very slowly. The duty cycle DC2 of the second switch S2 rises more sharply after the duty cycle DC1 of the first switch S1 has reached a maximum value above which this no longer rises. This maximum value is preferably slightly less than 1. The duty cycle DC1 of the first switch S1 in the exemplary embodiment according to FIG. 4 only reaches its maximum value when the input voltage Uin has already dropped below the value of the output voltage Uout. The duty cycle DC2 of the second switch S2 reaches its maximum value when the input voltage Uin reaches a minimum value Uin _min .

As can be seen from the course of the duty cycles DC1, DC2 as a function of the input voltage Uin in FIG. 4, the first and second switches S1, S2 in the switching regulator according to the invention are preferably controlled in such a way that both switches are switched on for a specific period of time per switching operation are switched, the duty cycles of the individual switches S1, S2 and the ratio of the duty cycles depends on the input voltage Uin. The second switch S2 (boost switch) is switched on for a particularly long time when the input voltage Uin drops below the value of the output voltage Uout and thus a voltage amplification by the switching regulator is required.

The course of the input voltage Uin is reflected in the switching regulator according to the invention both in the current signal IS and in the output voltage signal US. If the input voltage Uin drops, the output voltage Uout and the output voltage signal US also initially decrease, as a result of which the control signals RS1, RS2 increase. Conversely, the control signals RS1, RS2 decrease when the input voltage Uin increases. The behavior shown in Fig. 4, according to which the duty cycle DC2 of the second switch S2 set by the second control signal RS2 only increases when a certain value of the input voltage Uin falls below, can be generated by a suitable dimensioning of the control amplifier RV2, for example because of the fact that the gain of the second control amplifier RV2 is smaller than the control gain of the first control amplifier RV1 and that the second reference signal Vref2 is smaller than the first reference signal Vref1. The last-mentioned measure causes an "offset" of the second control amplifier RV2 compared to the first control amplifier RV1, where the duty cycle DC2 of the second switch S2 only begins to rise at a lower output voltage Uout than the duty cycle DC1 of the first switch S1. To limit the duty cycle DC1 of the first switch S1, a limiting circuit (not shown in detail) for the first control signal RS1 is preferably provided in order to limit the first control signal RS1 to a maximum upper value and in this way to ensure that the current signal IS is the first Control signal RS1 reached before the end of the period Tt is reached.

Fig. 5 shows a further embodiment of a switching regulator according to the invention, in which an AND gate AND is provided, which links the first control signal AS1 and the second control signal AS2, an output signal of the AND gate AND being used to control the second switch S2. The AND element AND ensures that the second switch S2 does not start to conduct before the first switch S1.

LIST OF REFERENCE NUMBERS

EK1, EK2 input terminals
AN1, AN2 control circuits
Uin input voltage
C1 capacitor
D1 diode
S1 first switch
Iin input current
I _L

coil current
L throttle
D2 diode
MA2 second measurement arrangement
IS current signal
S2 second switch
D3 diode
MA1 first measuring arrangement
R1, R2 resistors
C2 capacitor
AK1, AK2 output terminals
Uout output voltage
R _L

resistance
RV1 first control amplifier
RV2 second control amplifier
US voltage signal
Vref1 first reference signal
Vref2 second reference signal
C11, C21 capacitors
R11, R21 resistors
OV1, OV2 operational amplifier
RS1 first control signal
RS2 second control signal
K1 first comparator
K2 second comparator
RSF1 first RS flip-flop
RSF2 second RS flip-flop
AS1 first control signal
AS2 second control signal
TS clock signal
TG clock generator
DC1 duty cycle of the first switch
DC2 duty cycle of the second switch
Uin _max

maximum input voltage
Uin _min

minimum input voltage

Claims (12)

1. Switching regulator which has the following features:

• - input terminals (EK1, EK2) for applying an input voltage (Uin),
• - output terminals (AK1, AK2) for providing an output voltage (Uout) for a load (R _L ),
• an inductive storage element (L) and a capacitive storage element (C) connected in series with it,
• - a first switch (S1) for connecting the inductive storage element to one of the input terminals (EK1),
• - A second switch (S2) for short-circuiting the capacitive storage element (C).

2. Switching regulator according to claim 1, which is a first control circuit (AN1) for providing a first control signal nals (AS1) for the first switch (S1) and a second on control circuit (AN2) for providing a second An Control signal (AS2) for the second switch (S2). 3. Switching regulator according to claim 2, wherein the first and two th control circuit (AN1, AN2) on from the output voltage (Uout) dependent output voltage signal (US) is supplied. 4. The switching regulator of claim 1 or 2, wherein the first and second drive circuit is supplied to a dependent on the current (I _L) through the inductive storage element current signal (IS). 5. Switching regulator according to one of the preceding claims, in which the first and second drive circuits (AN1, AN2) a control amplifier (RV1, RV2) to compare the  Output voltage signal (US) with a reference signal (Vref1, Vref2) and to provide a control signal (RS1, RS2). 6. Switching regulator according to claim 5, wherein the gain of the second control amplifier (RV2) smaller than the Ver strengthening of the first control amplifier (RV1). 7. Switching regulator according to claim 5 or 6, in which the second reference signal (Vref2) smaller than the first Re reference signal (Vref1). 8. Switching regulator according to one of the preceding claims, in which the first and second drive circuits (AN1, AN2) a comparator (K1, K2) for comparing the rule signals (RS1, RS2) with one of the current signal (IS) dependent signal. 9. Switching regulator according to one of the preceding claims, in which the first and second drive circuits (AN1, AN2) have a flip-flop, which is dependent on one Clock signal (TS) set and dependent on a Kompara gate output signal (KS1, KS2) is reset. 10. Switching regulator according to one of the preceding claims, in which the first control signal (AS1) directly to the An control of the first switch is used and at which the first and second control signal an AND gate are supplied, the output signal for control of the second switch (S2) is used. 11. Method for converting an input voltage (Uin) into an output voltage, which has the following features:
Providing a switching regulator with input terminals (EK1, EK2) for applying the input voltage (Uin), output terminals (AK1, AK2) for providing the output voltage (U out), an inductive storage element (L) and a capacitive storage element (C) connected in series. , a first switch (S1) for connecting the inductive storage element to one of the input terminals (EK1), and with a second switch (S2) for short-circuiting the capacitive storage element (C),
Closing the first and second switches in accordance with a clock signal (TS), the switch-on times (Ta1, Ta2) of the first and second switches (S1, S2) being dependent on the input voltage (Uin). 12. The method of claim 9, wherein the first and second Switches (S1, S2) are closed at the same time and at the the first switch (S1) longer than the second switch (S2) remains closed.