DE10043955A1 - Semiconductor chip with a protective cover and associated manufacturing process - Google Patents
Semiconductor chip with a protective cover and associated manufacturing processInfo
- Publication number
- DE10043955A1 DE10043955A1 DE10043955A DE10043955A DE10043955A1 DE 10043955 A1 DE10043955 A1 DE 10043955A1 DE 10043955 A DE10043955 A DE 10043955A DE 10043955 A DE10043955 A DE 10043955A DE 10043955 A1 DE10043955 A1 DE 10043955A1
- Authority
- DE
- Germany
- Prior art keywords
- wafer
- resistant
- protective layer
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
Bei dem Halbleiterchip ist auf einer Oberseite eine Schutzschicht (6, 8) aus einem schleiffesten und/oder ätzresistenten Material aufgebracht. Das Material kann z. B. schleiffeste Körner enthalten. Eine bevorzugte Ausgestaltung sieht vor, dass der Halbleiterkörper (1) auf eine Dicke von weniger als 50 mum reduziert ist, so dass der Chip bei einem Versuch, die harte Schutzschicht abzuschleifen, unweigerlich bricht. Der Wafer wird von der Vorderseite her vorgesägt, damit die Chips leichter vereinzelt werden können, auf der Vorderseite mit der Schutzschicht (6) versehen und dann von der Rückseite her gedünnt.A protective layer (6, 8) made of a grinding-resistant and / or etching-resistant material is applied to the top of the semiconductor chip. The material can e.g. B. contain grinding-resistant grains. A preferred embodiment provides that the semiconductor body (1) is reduced to a thickness of less than 50 μm, so that the chip inevitably breaks when an attempt is made to grind off the hard protective layer. The wafer is sawn from the front so that the chips can be separated more easily, provided with the protective layer (6) on the front and then thinned from the back.
Description
Die vorliegende Erfindung betrifft einen Halbleiterchip mit einer Abdeckung zum Schutz gegen eine nicht autorisierte Strukturanalyse und ein zugehöriges Herstellungsverfahren.The present invention relates to a semiconductor chip a cover to protect against an unauthorized Structural analysis and an associated manufacturing process.
Bei Halbleiterchips, die eine sicherheitsrelevante Informati on enthalten, insbesondere Halbleiterchips mit einer für Chipkarten vorgesehenen integrierten Schaltung, ist es erfor derlich, Schutzmaßnahmen vorzusehen, die verhindern, dass die Inhalte der integrierten Schaltung ausspioniert werden. Her kömmliche Gehäuse oder Abdeckungen für Halbleiterchips bieten keinen ausreichenden Schutz, wenn die Gehäuse entfernt werden können oder eine Schutzabdeckung abgeschliffen oder abgeätzt werden kann.In the case of semiconductor chips that contain safety-related information on contain, in particular semiconductor chips with a for Chip card provided integrated circuit, it is required It is necessary to provide protective measures that prevent the Contents of the integrated circuit can be spied on. here offer conventional housings or covers for semiconductor chips insufficient protection when the housing is removed can or a protective cover ground or etched can be.
Aufgabe der vorliegenden Erfindung ist es, einen Halbleiter chip anzugeben, der gegen ein Ausspionieren der in dem Chip gespeicherten Daten ausreichend geschützt ist. Außerdem soll ein zugehöriges Herstellungsverfahren für einen derartigen Halbleiterchip angegeben werden.The object of the present invention is a semiconductor specify chip against spying in the chip stored data is adequately protected. In addition, should an associated manufacturing process for such Semiconductor chip can be specified.
Diese Aufgabe wird mit dem Halbleiterchip mit der Schutzab deckung mit den Merkmalen des Anspruches 1 bzw. mit dem Ver fahren zur Herstellung von Halbleiterchips mit einer Schutz abdeckung mit den Merkmalen des Anspruches 4 gelöst. Ausge staltungen ergeben sich aus den abhängigen Ansprüchen.This task is done with the semiconductor chip with the protection cover with the features of claim 1 or with the Ver drive to manufacture semiconductor chips with a protection Cover with the features of claim 4 solved. out Events result from the dependent claims.
Bei dem erfindungsgemäßen Halbleiterchip ist auf einer Ober seite eine Schutzschicht aus einem schleiffesten und/oder ätzresistenten Material aufgebracht. Das Material kann z. B. schleiffeste Körner enthalten. Eine bevorzugte Ausgestaltung sieht vor, dass der Halbleiterkörper auf eine Dicke von weni ger als 50 µm reduziert ist, so dass der Chip bei einem Versuch, die harte Schutzschicht abzuschleifen, unweigerlich bricht. Der Informationsgehalt oder die Struktur der Schal tung sind damit so weitgehend zerstört, dass eine Analyse nicht mehr möglich ist. Eine harte Schutzschicht aus schleif festem und/oder ätzresistentem Material lässt daher keine Möglichkeit, die in dem Chip integrierte Schaltung freizule gen, ohne die Schaltung so weitgehend zu zerstören, dass eine Analyse ihrer Struktur nicht mehr möglich ist.In the semiconductor chip according to the invention is on an upper a protective layer made of a grinding-resistant and / or etching-resistant material applied. The material can e.g. B. Grinding-resistant grains included. A preferred embodiment provides that the semiconductor body to a thickness of a few is reduced less than 50 µm, so that the chip when trying inevitably sanding down the hard protective layer breaks. The information content or the structure of the scarf device are so largely destroyed that an analysis is no longer possible. A hard protective layer made of sanding solid and / or caustic resistant material therefore leaves no Possibility to free the circuit integrated in the chip gene without destroying the circuit so much that a Analysis of their structure is no longer possible.
Es folgt eine Beschreibung eines bevorzugten Ausführungsbei spiels des erfindungsgemäßen Halbleiterchips anhand eines be sonders geeigneten Herstellungsverfahrens, das anhand der Fig. 1 bis 5 erläutert wird, die jeweils Zwischenprodukte im Querschnitt zeigen.The following is a description of a preferred embodiment of the semiconductor chip according to the invention using a particularly suitable production method, which is explained with reference to FIGS. 1 to 5, each of which shows intermediate products in cross section.
In Fig. 1 ist ein Wafer 1 dargestellt, in dem Bauelemente, die die integrierten Schaltungen der Chips bilden, im Wesent lichen fertig gestellt sind. Zwischen den Anteilen des Wa fers, die für die einzelnen Halbleiterchips 10 vorgesehen sind, werden Einschnitte 4 hergestellt. Diese Einschnitte 4 können im einfachsten Fall Einkerbungen sein. Es ist auch möglich, die Einschnitte durch ein Vorsägen des Wafers von der prozessierten Oberseite her bis in eine Tiefe von typisch etwa 30 µm bis 70 µm herzustellen. Auf der Oberseite des Wa fers befinden sich Anschlusskontaktflächen 2, z. B. aus Me tall oder leitfähig dotiertem Polysilizium, die dem elektri schen Anschluss der integrierten Schaltungen nach außen die nen und die eine Passivierung 3 der Oberfläche, die z. B. ein Nitrid sein kann, unterbrechen.In Fig. 1, a wafer 1 is shown in which components which form the integrated circuits of the chips are essentially finished. Incisions 4 are made between the portions of the wafer that are provided for the individual semiconductor chips 10 . In the simplest case, these incisions 4 can be notches. It is also possible to make the incisions by pre-sawing the wafer from the processed upper side to a depth of typically about 30 μm to 70 μm. On the top of the wa fers there are connection contact surfaces 2 , z. B. from tall or conductive doped polysilicon, the electrical rule's connection of the integrated circuits to the outside and the one passivation 3 of the surface, the z. B. can be a nitride, interrupt.
In einem nachfolgenden Verfahrensschritt wird eine Maske 5, vorzugsweise ein Fotolack, in die Einschnitte 4 und auf die Anschlusskontaktflächen 2 in einer für die nachfolgenden Schritte ausreichenden Höhe eingebracht bzw. aufgebracht. Diese Maske 5 überragt insbesondere die Passivierung 3. Es wird dann die vorgesehene Schutzschicht 6 hergestellt, so dass sie entsprechend Fig. 2 ganzflächig aufgebracht und ausreichend hart auf einem schleiffesten und/oder ätzresis tenten Material ausgebildet ist.In a subsequent method step, a mask 5 , preferably a photoresist, is introduced or applied into the incisions 4 and onto the connection contact surfaces 2 at a height sufficient for the subsequent steps. This mask 5 projects above the passivation 3 in particular. The intended protective layer 6 is then produced, so that it is applied over the entire area according to FIG. 2 and is sufficiently hard on a grinding-resistant and / or etch-resistant material.
Wie in Fig. 3 dargestellt, wird dann die Oberseite durch Rückschleifen planarisiert. Da der Wafer in diesem Verfah rensschritt noch eine für eine ausreichende mechanische Sta bilität erforderliche Dicke aufweist, kann die harte Schutz schicht 6 so weit abgetragen werden, dass das Material der Maske 5 freigelegt ist. Auf die dadurch zumindest weitgehend planarisierte Oberfläche wird vorzugsweise eine abschließend planarisierende Deckschicht 7, z. B. aus einem Kunststoff material, aufgebracht.As shown in Fig. 3, the top is then planarized by grinding back. Since the wafer in this procedural step still has a thickness required for sufficient mechanical stability, the hard protective layer 6 can be removed to such an extent that the material of the mask 5 is exposed. A finally planarizing top layer 7 , e.g. B. made of a plastic material.
Dann wird der Wafer von der Rückseite her gedünnt. Das ist in Fig. 3 durch die nach oben gerichteten Pfeile angedeutet. Dieses Dünnen kann vorzugsweise mittels CMP (chemical mechan ical polishing) geschehen. Der Halbleiterkörper des Wafers 1 wird so weit gedünnt, dass der wesentliche Anteil des Mate riales, in dem Beispiel der Fig. 3 bis zu der gestrichelt eingetragenen Grenze 11, entfernt wird. Vorzugsweise wird da bei erreicht, dass die Halbleiterchips 10 jetzt nicht mehr über das Halbleitermaterial, sondern nur noch über das Mate rial der in die Einschnitte 4 eingebrachten Maske 5 miteinan der verbunden sind. Dadurch wird das Vereinzeln der Halblei terchips erleichtert.Then the wafer is thinned from the back. This is indicated in Fig. 3 by the arrows pointing upwards. This thinning can preferably be done by means of CMP (chemical mechanical ical polishing). The semiconductor body of the wafer 1 is thinned to such an extent that the essential portion of the material, in the example of FIG. 3, is removed up to the limit 11 shown in broken lines. It is preferably achieved that the semiconductor chips 10 are no longer connected to one another via the semiconductor material, but only via the material of the mask 5 introduced into the incisions 4 . This makes it easier to separate the semiconductor terchips.
Fig. 4 zeigt den gedünnten Wafer im Querschnitt. Der Halb leiterkörper des Wafers besitzt nach diesem Verfahrensschritt vorzugsweise eine Dicke von weniger als 50 µm. Es wird dann noch bei einer bevorzugten Ausführungsform des Verfahrens auf die Rückseite des Wafer, d. h. auf diejenige Seite des Wa fers, von der bei dem Verfahrensschritt des Dünnens das Mate rial abgetragen wurde, eine weitere Schutzschicht 8 aufge bracht, die vorzugsweise ebenfalls aus dem schleiffesten und/oder ätzresistenten Material der oberen Schutzschicht 6 ausgebildet wird. Es kann dann noch eine Deckschicht 9 auf dieser Seite, z. B. ebenfalls aus einem Kunststoffmaterial, aufgebracht werden. Die Halbleiterchips werden aus dem ge dünnten Wafer in einer an sich bekannten Weise vereinzelt, was ohne Schwierigkeiten geschehen kann, da die Halbleiter chips im Wesentlichen nur noch durch das Material der Maske 5 miteinander verbunden sind. Die Halbleiterchips sind jetzt so dünn, dass ein Versuch, die Schutzschicht 6 zu entfernen, zum Bruch der Halbleiterchips führt. Restliche Anteile 15 der Maske, die noch auf den Anschlusskontaktflächen 2 vorhanden sind, können zusammen mit der darauf aufgebrachten Deck schicht 7 entfernt werden, um so den Anschluss von Bonddräh ten oder dergleichen zu ermöglichen. Fig. 4 shows the thinned wafer in cross section. The semiconductor body of the wafer preferably has a thickness of less than 50 μm after this process step. It is then in a preferred embodiment of the method on the back of the wafer, ie on that side of the wafer, from which the material was removed in the thinning step, a further protective layer 8 is applied, which is preferably also made of the grinding-resistant and / or etch-resistant material of the upper protective layer 6 is formed. There can then be a cover layer 9 on this side, e.g. B. also be applied from a plastic material. The semiconductor chips are separated from the thinned wafer in a manner known per se, which can be done without difficulty since the semiconductor chips are essentially only connected to one another by the material of the mask 5 . The semiconductor chips are now so thin that an attempt to remove the protective layer 6 leads to the breakage of the semiconductor chips. Remaining portions 15 of the mask, which are still present on the connection contact surfaces 2 , can be removed together with the cover layer 7 applied thereon, so as to enable the connection of bonding wires or the like.
Fig. 5 zeigt im Querschnitt ein Beispiel für einen vollstän dig montierten (gehäusten) Halbleiterchip, der mit Bonddräh ten 12 auf den Anschlusskontaktflächen 2 versehen und auf ei nem Leadframe 14 oder einem Chipkartenkörper oder dergleichen aufgebracht und mit einer Vergussmasse 13 (globe top) bedeckt ist. Fig. 5 shows in cross section an example of a fully assembled (packaged) semiconductor chip, which is provided with bonding wires 12 on the connection contact surfaces 2 and applied to a lead frame 14 or a chip card body or the like and covered with a sealing compound 13 (globe top) is.
Claims (7)
in einem ersten Schritt Einschnitte (4) zwischen den für Halbleiterchips (10) vorgesehenen Anteilen des Wafers (1) hergestellt werden, in einem zweiten Schritt diese Einschnitte (4) und Anschluss kontaktflächen (2) mit einer Maske (5) aufgefüllt bzw. be deckt werden,
in einem dritten Schritt eine Schutzschicht (6) aus einem Ma terial, das schleiffest und/oder ätzresistent ist, ganzflä chig aufgebracht wird,
in einem vierten Schritt die mit dieser Schutzschicht (6) be deckte Fläche planarisiert wird,
in einem fünften Schritt der Wafer von der der Schutzschicht (6) gegenüberliegenden Seite her gedünnt wird und in einem sechsten Schritt die Halbleiterchips (10) aus dem Wafer vereinzelt werden.4. Process for the production of semiconductor chips with a protective cover, in which, starting from a wafer with finished components,
in a first step, incisions ( 4 ) are made between the portions of the wafer ( 1 ) provided for semiconductor chips ( 10 ), in a second step these incisions ( 4 ) and connection contact surfaces ( 2 ) are filled or filled with a mask ( 5 ) be covered
in a third step, a protective layer ( 6 ) made of a material that is resistant to grinding and / or etching is applied over the entire surface,
in a fourth step, the surface covered with this protective layer ( 6 ) is planarized,
in a fifth step the wafer is thinned from the side opposite the protective layer ( 6 ) and in a sixth step the semiconductor chips ( 10 ) are separated from the wafer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10043955A DE10043955A1 (en) | 2000-09-06 | 2000-09-06 | Semiconductor chip with a protective cover and associated manufacturing process |
| PCT/DE2001/003308 WO2002021596A2 (en) | 2000-09-06 | 2001-08-30 | Semiconductor chip with a protective covering and associated production method |
| TW090121963A TW516196B (en) | 2000-09-06 | 2001-09-05 | Semiconductor chip with a protection cover and the manufacture method of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10043955A DE10043955A1 (en) | 2000-09-06 | 2000-09-06 | Semiconductor chip with a protective cover and associated manufacturing process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE10043955A1 true DE10043955A1 (en) | 2002-04-04 |
Family
ID=7655207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10043955A Ceased DE10043955A1 (en) | 2000-09-06 | 2000-09-06 | Semiconductor chip with a protective cover and associated manufacturing process |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE10043955A1 (en) |
| TW (1) | TW516196B (en) |
| WO (1) | WO2002021596A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10324751A1 (en) * | 2003-05-30 | 2005-01-05 | Infineon Technologies Ag | Semiconductor structure has stabilizing coating of metal and/or passivation material applied to applied/stamped metal/semiconducting/insulation layer structure on upper side of substrate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10337256A1 (en) * | 2002-11-21 | 2004-06-09 | Giesecke & Devrient Gmbh | Integrated circuit and production process especially for chip cards has active circuit on substrate surface and deep doped layer to protect against rear interrogation |
| DE102004007690B3 (en) | 2004-02-16 | 2005-10-13 | Infineon Technologies Ag | Integrated circuit arrangement |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4247031A (en) * | 1979-04-10 | 1981-01-27 | Rca Corporation | Method for cracking and separating pellets formed on a wafer |
| US5258334A (en) * | 1993-01-15 | 1993-11-02 | The U.S. Government As Represented By The Director, National Security Agency | Process of preventing visual access to a semiconductor device by applying an opaque ceramic coating to integrated circuit devices |
| US5458912A (en) * | 1993-03-08 | 1995-10-17 | Dow Corning Corporation | Tamper-proof electronic coatings |
| EP0834914A2 (en) * | 1996-10-04 | 1998-04-08 | Dow Corning Corporation | Electronic coatings |
| DE19853703A1 (en) * | 1998-11-20 | 2000-05-25 | Giesecke & Devrient Gmbh | Chip production, especially for a chip card, comprises applying metallization onto a thinned finished chip wafer, bonded to a handling wafer, for connection by vias to the chip metallization and/or circuit structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999016131A1 (en) * | 1997-09-19 | 1999-04-01 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for wiring semi-conductor components in order to prevent product piracy and manipulation, semi-conductor component made according to this method and use of said semi-conductor component in a chip card |
-
2000
- 2000-09-06 DE DE10043955A patent/DE10043955A1/en not_active Ceased
-
2001
- 2001-08-30 WO PCT/DE2001/003308 patent/WO2002021596A2/en active Application Filing
- 2001-09-05 TW TW090121963A patent/TW516196B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4247031A (en) * | 1979-04-10 | 1981-01-27 | Rca Corporation | Method for cracking and separating pellets formed on a wafer |
| US5258334A (en) * | 1993-01-15 | 1993-11-02 | The U.S. Government As Represented By The Director, National Security Agency | Process of preventing visual access to a semiconductor device by applying an opaque ceramic coating to integrated circuit devices |
| US5458912A (en) * | 1993-03-08 | 1995-10-17 | Dow Corning Corporation | Tamper-proof electronic coatings |
| EP0834914A2 (en) * | 1996-10-04 | 1998-04-08 | Dow Corning Corporation | Electronic coatings |
| DE19853703A1 (en) * | 1998-11-20 | 2000-05-25 | Giesecke & Devrient Gmbh | Chip production, especially for a chip card, comprises applying metallization onto a thinned finished chip wafer, bonded to a handling wafer, for connection by vias to the chip metallization and/or circuit structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10324751A1 (en) * | 2003-05-30 | 2005-01-05 | Infineon Technologies Ag | Semiconductor structure has stabilizing coating of metal and/or passivation material applied to applied/stamped metal/semiconducting/insulation layer structure on upper side of substrate |
| US7253471B2 (en) | 2003-05-30 | 2007-08-07 | Infineon Technologies Ag | Semiconductor structure having thick stabilization layer |
| DE10324751B4 (en) * | 2003-05-30 | 2009-01-22 | Infineon Technologies Ag | Method for producing a semiconductor structure with a semiconductor substrate and semiconductor structure produced by this method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002021596A2 (en) | 2002-03-14 |
| WO2002021596A3 (en) | 2003-03-06 |
| TW516196B (en) | 2003-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE10202881B4 (en) | Method for producing semiconductor chips with a chip edge protection layer, in particular for wafer level packaging chips | |
| DE4434230C2 (en) | Chemical-mechanical polishing process for leveling insulating layers | |
| DE10253938B4 (en) | A method for simultaneously producing a bonding pad structure and a stacked capacitor in a semiconductor device | |
| DE102013101327B4 (en) | Method of manufacturing a semiconductor device and semiconductor device | |
| DE69721411T2 (en) | Semiconductor device and manufacturing method therefor | |
| DE4310954C2 (en) | Semiconductor processing method for producing an isolation trench in a substrate | |
| DE4310955C2 (en) | Process for processing a semiconductor wafer | |
| DE112005002899B4 (en) | Semiconductor device with a chip, which is arranged between a cup-shaped printed circuit board and a circuit board with mesas and valleys, and method for its preparation | |
| DE19834917A1 (en) | Forming self-aligned vias in a semiconductor device | |
| DE2153103A1 (en) | Integrated circuit arrangement and method of making the same | |
| DE10101037A1 (en) | Semiconductor device has multilayer wiring structure buried in insulating layer, and at least one pad electrode connected to multilayer wiring and covered with protective layer | |
| DE10236682A1 (en) | Semiconductor device | |
| DE10351761A1 (en) | Dynamic value sensor, e.g. semiconductor acceleration sensor, has a switching circuit board that is arranged over the sensor moving element and is sealed to the sensor circuit board, thus also acting as a protection cap | |
| DE102004052921A1 (en) | Process for the production of semiconductor devices with external contacts | |
| DE102019106603A1 (en) | Structure and method for preventing silicide contamination during the manufacture of microprocessors with embedded flash memory | |
| DE112020005737T5 (en) | Method of manufacturing a functional chip capable of being assembled with wire elements | |
| DE112019005745T5 (en) | Semiconductor component | |
| DE4314906A1 (en) | Semiconductor component with power connections for high integration density | |
| WO2000042657A1 (en) | Electronic component and use of a protective structure contained therein | |
| EP1118122B1 (en) | Integrated circuit and method for producing the same | |
| DE19716791B4 (en) | Method for producing contact openings in a multilayer semiconductor structure | |
| DE102013109590A1 (en) | A method of processing a wafer and a method of dicing a wafer | |
| DE10344273B4 (en) | Improved contact for memory cells | |
| DE10043955A1 (en) | Semiconductor chip with a protective cover and associated manufacturing process | |
| DE3000121A1 (en) | METHOD FOR PRODUCING A MOS SEMICONDUCTOR DEVICE WITH SELF-ADJUSTED CONNECTIONS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| 8131 | Rejection |