DE10025746A1 - Production of a solid body substrate used in the silicon switching circuits comprises a cylindrical solid body and cutting out substrate plates in the direction of the cylinder axis, and laterally joining several substrate plates - Google Patents

Abstract

Production of a solid body substrate comprises preparing a cylindrical solid body and cutting out substrate plates (1, 2) in the direction of the cylinder axis; and laterally joining several substrate plates. An Independent claim is also included for a process for the production of a crystalline solid body layer comprising forming a solid body substrate as above; producing a crystalline solid body layer on the surface of the substrate; removing the crystalline solid body layer from the substrate; and carrying out the previous two steps. Preferred Features: The substrate is a silicon substrate and has crystallographic (100)-orientation.

Description

The invention relates to a method for producing a Solid state substrate and a method for producing a crystalline solid layer by epitaxial growth on the solid substrate. The invention relates in particular on the production of large-scale semi-lead ter substrates such as silicon substrates, which act as mother substrates can be used to epitaxially on them Growth process to deposit crystalline silicon layers and separate after the deposition and if necessary to bond other solid substrates.

Today's silicon circuits are relatively thick single-crystal disc manufactured. This is for the Circuits just a thin, a few microns thick layer used electronically near the surface. The rest che thickness of the single-crystal silicon wafer is used only for mechanical reasons. This is often the case volume of the silicon wafer can even be regarded as a hindrance see. For example, SOI (Silicon on Insula tors) technology an insulator layer between electronic active layer and mechanically necessary silicon carrier. In this way, either the radiation resistance of the elec tronic active layer increased or disruptive capacitive Effects of the silicon carrier in the functioning of scarf efforts are reduced.

The production of silicon crystals takes place with the so-called bulk crystal growing. It usually consists of four steps:

• 1. Manufacture of metallurgical silicon;
• 2. Siemens process (hydrochlorination, fractionated distillation) → trichlorosilane, SiHCl ₃ ;
• 3. Manufacture polycrystalline silicon;  
• 4. Manufacture of the single crystals by pulling them out of the melt (Czochralski method, CZ) or zone pulling (float zone, FZ)

The growth of bulk crystals is currently at a maximum of 12 Inches limited. As a result, there are also discs from Sili zium cut from such sticks in their Diameter limited to 12 inches. The circular shape of the disc is determined by the shape of the rod. Often done after the production of the circular discs still more epi taxi steps before a circuit on the silicon wafer will be produced.

In the semiconductor technology is the diameter of the disks and staffs have grown more and more in the past. The before Part of larger panes is that larger ones Diameter in one process step more components can be put. Larger areas therefore cost money benefits. Therefore, also with the conventional technology the manufacture of single-crystalline semiconductor wafers size will continue to increase in the future.

However, the conventional methods for producing semiconductor bulk crystals are very complex, energy-intensive and cost-intensive because the metallurgical silicon in the initial state in step 2 above. is first converted into the gas phase (trichlorosilane, SiHCl ₃ ), then in step 3 . solidified again to polycrystalline silicon, finally in step 4 . to be melted and pulled out of the melt as a single crystal.

In addition, the material ver need extremely high, because a large part of the thickness of the half lead only serves for stability purposes and for elec tronic components can not be used.

Various methods have therefore been developed to single or polycrystalline with little use of material, thin, component-capable semiconductor layers on a substrate  to grow up and through a transfer process to an to transfer their substrate.

For example, EP 0 797 258 describes the so-called ELTRAN Process (epitaxial layer TRANsfer) described in which porous silicon material is used. With this ver First we drive in the surface of a first silicon wafers creates a porous layer by anodic etching. By thermal healing is then in the porous Silicon layer by growing together of pores in a be certain depth creates a separation or gap layer. Soon the surface of the porous silicon layer becomes recurrent installed so that on this a crystalline silicon layer can be grown epitaxially. On this epi tactical layer can then, for example, a second sili Ziumwafer are bonded to the interface of the po red silicon can be separated.

While in the aforementioned process the porous silicon EP 0 993 029 describes the layer used as the sacrificial layer a method in which the porous layer before or after detaching them from the mother substrate at least in part is recrystallized and even as a component capable Layer can be used.

In the so-called smart cut process, such as be written in U.S. Patent No. 5,714,395, are in a half lead Terwafer ions implanted in such a way that in a certain th, the depth of the predetermined by the implantation parameters Form semiconductor wafers micro-inclusions. Then one second semiconductor wafer on the surface of the first half conductor wafers bonded. By subsequent thermal off heal the micro-inclusions grow in the first semiconductor wafers to form a separation or gap surface. At this The separating surface can then be the second semiconductor wafer and the bonded layer of the first semiconductor wafer slightly abge be separated.

With these methods, the semiconductor used in each case Starting substrate, the so-called mother substrate, multiple times  used to wake up a variety of epitaxially monocrystalline semiconductor layers to a small extent to generate material. Have these known methods however, all have the disadvantage that the area dimension of their Carried out substrates not used by one The type of manufacture of the substrates depends on the size. One is, for example, when using silicon substrate on the 12 inch wafer diameters already mentioned limits, while essential in III-V semiconductors such as GaAs smaller wafer diameters can be achieved.

The present invention is therefore based on the object to disclose a method of manufacturing a solid substrate give which one - compared to the conventional one Volume crystal production - larger area of the solid persubstrats is reachable. Another task of the present The present invention is such a manufactured t solid substrate as a mother substrate for repeated Production and separation of an epitaxially grown festival to use body layers.

These tasks are characterized by the characteristics of the independent Pa claims resolved. Advantageous further developments are in specified in the subclaims.

In a first aspect, the present invention thus describes two processes which are in principle independent of one another and which allow large-area solid-state, in particular semiconductor, crystals to be produced which are no longer limited in their extent by the physical / technological limits in the production of single-crystal, defect-free rods. These two processes are:

• A) Providing a cylindrical solid-state single crystal and sawing out at least one substrate plate in the direction the cylinder axis;
• B) Lateral joining of several solid-state substrate plates ten, optionally by method step A. were put.

Both methods alone and / or their combination lead there to that in the result large-area solid substrates before which have a larger surface area than those which previously possible by using conventional bulk crystals were.

According to the first aspect of the invention there are fundamental principles three different process variants are available.

On the one hand, method A. can be used alone, in the z. B. from a drawn by the Czochralski process Silicon single crystal in the growth direction a rectangular Substrate plate is sawn out. This already shows a size larger area than that usually across the growth direction sawn-out slices, so that the process A. the above task is solved alone.

However, method A. can also be combined with method B. be binated by, for example, the one drawn Silicon bar sawed out rectangular substrate plates la terally joined together, or by combining different pulled silicon rods laterally sawn out substrate plates be joined together.

Finally, method B can also be used alone come by other than by sawing from egg Substrate plates made with a rod are laterally juxtaposed be added. For example, you can start with several circles round silicon wafers manufactured in a conventional manner and then be prepared so that they are lateral can be joined together.

With regard to process step B., different types of latera len assembly of the substrate plates with different technological effort are conceivable depending on the requirements for defect-free. In the simplest case, two substrate plates to be joined can be placed against one another at their straight edges and melted together by the action of heat, for example an oven, a halogen lamp or a laser beam. A somewhat more complex method, on the other hand, provides to arrange the substrate plates at a short distance from one another and to epitaxially apply further substrate plate material into the gap between them by means of a growth process, so that a connection with the lowest possible offset density arises between the substrate plates. Furthermore, provision can additionally be made to prepare the edges of the substrate plates in a suitable manner, for example in order to create suitable crystallographic growth conditions for subsequent epitaxial growth. The edges can e.g. B. beveled who, so that the beveled flanks have a ( 111 ) orientation, which are favorable for subsequent epitaxial growth.

If an epitaxial coalescence of individual substrates plates by growing further substrate plate material or other material is provided, can be used for this conventional and inexpensive process such as LPE (Flüs sigphase epitaxy) or CVD (chemical vapor deposition) be applied.

The solid substrates produced according to the first aspect of the invention can even be used for the production of electronic components. However, it can also be provided according to a second aspect of the invention to use the solid substrates as mother substrates for single or multiple production of crystalline solid layers. In this case, the solid substrate produced as described above is used to produce at least one crystalline solid layer using the following process steps:

• a) Manufacture of a solid mother substrate with the Ver drive A. and / or B. as described;
• b) creating a crystalline solid layer on the top area of the mother substrate;
• c) separating the crystalline solid layer from the courage ter substrate;
• d) if necessary, performing the process steps again b. and c.

This second aspect thus contains different ones in itself State of the art essentially known layer generation, Transfer and transfer procedures and / or epitaxial techni that can serve to solidify these solid layers multiply, multiply or divide.

With these multiplication techniques, the originally solid sub produced with the methods A. and / or B. strate serve as reusable mother substrates. This one Mother substrates compared to conventional semiconductor wafers have relatively large areas can correspond to them accordingly large crystalline semiconductor layers are produced.

Every method known in the prior art is for this purpose Principle applicable. It can be layer material with a wax growing up epitaxially. This is ever but not absolutely necessary. For example, it can also that already mentioned in the introduction to the description, in the Methods described in EP 0 993 029 are used in which the porous layer before or after its removal from the mother substrate is at least partially recrystallized and can even be used as a component-capable layer can. Accordingly, this procedure is followed in the procedure Step b. a po on the surface of the mother substrate generated rous layer, this porous layer of two There are layers of different porosity, of which the lower layer has the higher porosity, and in the process Step b. a heat treatment is also carried out, through which the upper porous layer at least partially re is crystallized and the upper porous layer at least is partially converted into a separation layer, and on closing the recrystallized solid layer, given if necessary, after bonding another solid-state substrate the solid layer, in process step c. at the parting layer, possibly with further heat, from the mother substrate is detached.

It can also ge in the introduction to the description called ELTRAN method described in EP 0 797 258  are used, in which also porous silicon material material is used. In this method, Ver step b. the surface of the mother substrate in such a way prepares that he has a porous layer on its surface is produced, then a crystalline solid layer epitaxially grown on the porous layer, and then the crystalline solid layer is added if necessary, after bonding another solid-state substrate the solid layer, in process step c. by dissolving the porous layer, optionally under the influence of temperature kung, detached from the mother substrate.

This process can also be modified to the extent that the mother substrate has a defined crystallographic orientation and in process step b. the surface of the mother substrate is further prepared in such a way that a texturing is generated in it before the porous layer is generated and in process step c. a wafer-shaped crystalline solid layer produced in this way is separated from the mother substrate. If the mother substrate is a silicon substrate, then a crystallographic ( 100 ) orientation is preferably set. This method is known as the Ψ process and in the publication by Brendel et al. in Appl. Phys. A 67, 151 ( 1998 ).

As a further conceivable method, that described in US Pat. No. 5, 714,395 described smart cut method can be used in which in process step b. the surface of courage substrate is prepared in such a way that a near-surface Layer with ions is implanted on the implanted courage another solid-state substrate is bonded and through a temperature treatment step near the surface implanted layer is separated from the mother substrate. For example, when using a silicon substrate Hydrogen ions are implanted.

Finally, the so-called epi-lift method can be used, which is described in the publication by KJ Weber et al. in proc. 26 ^th IEEE Photovoltaic Specialists Conf. (IEEE, Picataway, 1997), p. 107. In this process, the mother substrate has a defined crystallographic orientation and a cover layer, in particular an oxide layer, is applied to its surface and in process step b. the surface is prepared by removing the cover layer along predetermined lines, in particular in the form of a network structure, so that during the subsequent epitaxial growth, the crystalline semiconductor layer preferably grows in the cover layer-free areas on the exposed solid surface of the mother substrate. If a silicon substrate is used as the mother substrate, this preferably has the crystallographic orientation ( 100 ).

According to one of the aforementioned methods or according to one their process produced and separated crystalline solid Body layers can be done after performing the procedure step c. depending on the application to any festival body substrate, for example on a (high temperature) Glass substrate, a (high temperature) ceramic substrate or ge suitable plastic substrates are applied. In case of Crystalline silicon layers can also be advantageous on polycrystalline silicon substrates be brought, since here is the risk of contamination tens of the substrate is very low and the thermal properties the crystalline silicon layer and the substrate are best coordinated.

The principle of the invention is universal and principally based on all types of solids can be used, but is suitable especially for semiconductors, and of course in particular for silicon or III-V semiconductors such as GaAs, GaN or InP. It However, applications with non-semiconductors are also conceivable, especially with (high temperature) superconductors or others ceramic materials with a crystalline structure. On too Diamond, the invention could be used to advantage.

In summary, the most important advantages of the method according to the invention are:

• - There are large solid, especially semiconductors discs and layers can be produced;
• - avoid bulk crystal growing;
• - The solid substrates produced are not on one Limited circular shape;
• - The thin crystalline solid layers can with egg any known method (Eitran, SIMOX, porous Si, quasi-monocrystalline Si in the case of silicon as a solid body material) are peeled off;
• - Bypassing polycrystalline Si and melting conventional Si production
• - Disc-shaped Si produced directly by epitaxy crystalline silicon surface.

In the following, exemplary embodiments of the invention are described in Connection with the drawing figures explained in more detail. It shows gene:

Fig. 1a conventional sawing of a grown semiconductor rod;

FIG. 1b inventive cutting a grown semiconducting terstabes in the growth direction of the crystal;

Fig. 2a substrate plates before assembling a size ren plate;

Fig. 2b plates assembled after epitaxial growth;

Fig. 3a substrate plates with chamfered edges (( 111 ) -orientation);

FIG. 3b plates by epitaxial growth bonded substrate;

Fig. 3c assembled substrate plates after planarization.

In FIGS. 1a and 1b, a cylindrical half is shown single crystal respectively. This rod is usually sawn across the direction of growth, i.e. the cylinder axis. As shown in Fig. 1a, circular wafers are obtained in this way, the maximum diameter of which is currently limited to 12 inches by silicon due to the physical and technological limits in the manufacture of the rods. When manufacturing GaAs and other semiconductors, the maximum achievable diameter is considerably lower.

The circular shape of the semiconductor wafers stems from the fact that they are cut from equally circular rods which are produced either by the Czochralski (CZ) or the float zone (FZ) process. As a result, the maximum diameter of each disc is limited to the diameter of the rod. If, in contrast to the previous method, the rod is no longer cut transversely to the direction of growth but, as shown in FIG. than it corresponds to the diameter of the rod. This edge is limited only by the length of the bar. The semiconductor plates cut in the longitudinal direction of the rod can either be used directly for the production of components, connected laterally by the method B. to form even larger substrate plates and / or by the method steps a. to d. layers are used for the multiple generation of crystalline semiconductor.

Such a method for lateral joining is shown in an exemplary manner with reference to FIGS . 2a-2c. In FIG. 2a, two substrate plates 1 and 2 separated by a gap 4 are arranged on a carrier 3 serving as a base. The substrate plates 1 and 2 are to be connected to a larger substrate plate. For this purpose, the gap 4 is filled, for example by lateral epitaxy or else by fusing (for example with the aid of a halogen lamp or a laser) of the substrate plates 1 and 2 . In the case of epitaxy, the substrate plates 1 and 2 can be prepared on the surface such that epitaxy takes place predominantly in the gap, as will be explained below by way of example. In the case of epitaxy, the substrate plates 1 and 2 then finally grow together. Epitaxial bonding can take place using the same or different material as the substrate plates 1 and 2 .

FIG. 2b shows the ideal case of perfect by filling the gap 4 assembled parts 1 and 2. Section 5 has taken the place of gap 4 . In the case of joining by lateral epitaxy, the section 5 can consist of the same material as the substrate plates 1 and 2 . In this case, a continuous sub stratplatte 6 is obtained , consisting of the smaller substrate plates 1 , 2 and section 5 , which has a larger surface area than the individual substrate plates 1 and 2 . In particular, such a process can be used to produce large-area substrates of semiconductors (for example silicon).

In FIGS. 3a-3c a further variant of the lateral joining is shown, in which - the substrate plates are sequentially numbered so präpa at their edges, that the epitaxy takes place predominantly in the gap 4 - as indicated above. There are first two silicon substrate plates 1 and 2 , as shown in Fig. 2a, chamfered at their opposite edges to be joined, so that the chamfered edges have a crystallographic orientation ( 111 ). Then the substrate plates 1 and 2 are placed together on a suitable carrier 3 , so that a gap 4 is formed between the beveled edges. In this gap 4 is then selectively grown on the edges by liquid phase epitaxy or CVD silicon ( Fig. 3b). In a last process step, the resulting structure is polished back or planarized, for example, by means of chemical mechanical polishing.

Claims (19)

1. A method for producing a solid substrate with the following process steps, which are carried out individually or in combi nation

• A) providing a cylindrical solid-state single crystal and sawing out at least one substrate plate in the direction of the cylinder axis;
• B) Lateral joining of several solid substrate plates, which were optionally produced by process step A.

2. A process for producing at least one crystalline solid layer with the following process steps.

• a) producing a solid mother substrate according to claim 1;
• b) producing a crystalline solid layer on the upper surface of the mother substrate;
• c) separating the crystalline solid layer from the mother substrate;
• d) if necessary, performing the process steps again b. and c.

3. The method according to any one of claims 1 or 2, characterized in that
in process step B. two edge sections of two solid substrate plates are prepared and / or positioned relative to one another, and
then a material connecting the edge sections is applied. 4. The method according to claim 3, characterized in that
the edge sections are prepared and / or positioned relative to one another such that there is a gap between them ( 4 ), and
the material connecting the edge sections is introduced into the gap ( 4 ). 5. The method according to claim 3 or 4, characterized in that a solid material, in particular the solid material rial of the substrate and / or that of the epitaxially grown crystalline solid layer te on the Randabschnit te and / or the gap between them ( 4 ) possibly epitaxially grown becomes. 6. The method according to claim 4, characterized in that
the edge sections are prepared by chamfering them to form crystallographically favorable growth conditions, whereby
the gap ( 4 ) is formed by the space between the opposite beveled surfaces. 7. The method according to claim 6, characterized in that the solid material is silicon and the beveled surface has the crystallographic orientation ( 111 ). 8. The method according to any one of claims 1 or 2, characterized in that
two solid-state substrate plates ( 1 , 2 ) are joined together in that they are placed directly or at a distance at two edge sections or edges, and
the edge sections are melted together by the action of heat. 9. The method according to claim 2, characterized in that
in process step b. a porous layer is produced on the surface of the mother substrate, wherein
the porous layer consists of two layers of different porosity, of which the lower layer has the higher porosity, and
in process step b. a heat treatment is also carried out, through which the upper porous layer is at least partially recrystallized and the upper porous layer is at least partially converted into a separation layer, and
then the recrystallized solid layer, ge optionally after bonding a further solid substrate to the solid layer, in process step c. on the separating layer, possibly under further heat, is detached from the mother substrate. 10. The method according to claim 2, characterized in that
in process step b. the surface of the mother substrate is prepared such that a porous layer is produced on its surface,
then a crystalline solid layer is epitaxially grown on the porous layer, and
then the crystalline solid layer, optionally after bonding a further solid substrate to the solid layer, in process step c. by dissolving the porous layer, possibly under the action of temperature, is detached from the mother substrate. 11. The method according to claim 10, characterized in that
the mother substrate has a defined crystallographic orientation, and
in process step b. the surface of the mother substrate is further prepared in such a way that texturing is produced in it before the porous layer is produced, and
in step c. a waffle-shaped crystalline solid layer is separated from the mother substrate. 12. The method according to claim 11, characterized in that the mother substrate is a silicon substrate and has a crystallographic ( 100 ) orientation. 13. The method according to claim 2, characterized in that
in process step b. the surface of the mother substrate is prepared in such a way that a layer close to the surface is implanted with ions,
another solid-state substrate is bonded onto the implanted mother substrate, and
the surface-implanted layer is separated from the mother substrate by a temperature treatment step. 14. The method according to claim 2, characterized in that
the mother substrate has a defined crystallographic orientation and a cover layer, in particular an oxide layer, is applied to its surface, and
in process step b. the surface is prepared by removing the cover layer along predetermined lines, in particular in the form of a network structure, so that during the subsequent epitaxial growth, the crystalline semiconductor layer preferably grows in the cover layer-free areas on the exposed solid surface of the mother substrate. 15. The method according to claim 14, characterized in that the mother substrate is a silicon substrate with crystallographic ( 100 ) orientation. 16. The method according to claim 2, characterized in that the crystalline solid layer, in particular a sili zium layer, after process step c. on a solid substrate, especially on a polycrystalline silicon Solid-state substrate is applied. 17. The method according to one or more of the preceding An claims, characterized in that the solid substrate and / or the solid single crystal and / or the solid substrate plates and / or the crystalline  Solid layer made of a semiconductor material, in particular from silicon or a III-V semiconductor mat rial such as GaAs, GaN or InP are made. 18. The method according to one or more of the preceding An claims, characterized in that the solid substrate and / or the solid single crystal and / or the solid-state substrate plates and / or the kri stalline solid layer made of a superconducting mate are made. 19. The method according to one or more of the preceding An claims, characterized in that the solid substrate and / or the solid single crystal and / or the solid-state substrate plates and / or the kri stalline solid layer are made of diamond.