DE10022765C2 - Content addressable memory - Google Patents

Description

The invention relates to a content-addressable memory (CAM = content addressable memory) with a memory field consisting of a memory matrix with n rows and m columns from k-bit deep memory elements, a control logic for Reading of addresses to be translated with a maximum word length of m * k bit in a register and a decoder logic for Reading out the data corresponding to the addresses. Wei the invention also relates to a method for selection an address from a variety of addresses, including those under different content are assigned, with the help of a addressable memory (CAM) by specifying a given content.

Similar CAM memories are for example from the US 5,818,786 A, US 5,978,246 A and US 5,999,434 A known. In particular, from the latter No. 5,999,434 A, the basic structure of a CAM is taken become.

CAM are used, for example, in public exchanges used to due to a given connection identifier the associated valid extension numbers with high speed to spend.

With such a content addressable memory (CAM), the Also called associative memory is a multitude of identifiers, e.g. B. connection identifiers, with an assoc numbered number, e.g. B. an extension number, in a memory matrix filed. Now the number should be based on an identifier are searched for, the identifier is simultaneously via the entered identifiers "placed" (= simultaneously with all n Words of the array), the answer being the one or several associated numbers are output.

In terms of hardware, this can be done by different logical Circuit structures can be achieved.

A structure where the match and the answer are very The NOR structure, in which all bit comparisons are carried out quickly  in parallel and the respective comparison line is reloaded from valid (precharge value) to invalid if only one of the bit comparisons is invalid. Such NOR Structures generate relatively high power losses through a correspondingly high cooling effort must be compensated sen.

As an alternative to the NOR structure, a NAND structure can be used become. Here is the comparison between the searched Identifier and the existing identifiers quasi-serial, whereby all comparisons must be fulfilled in order to at the exit of Ver to achieve the answer "valid". By this quasi-serial processing is the response time This NAND structure is much slower, but the ver pleasure output much lower than with a NOR structure, since only the few "hits" to reload the lines to lead.

A detailed description of the functioning of such storage systems can be found in the article "Fully Parallel Integrated CAM / RAM Using Preclassification to Enable Large Capacities" from IEEE Journal on Solid-State Circuits, Vol. 31, No. S. May 1996 , the disclosure content of which is hereby fully adopted with regard to the structure and mode of operation of CAMs.

There is a major disadvantage of these known CAMs in the case of a NOR organization of the memory fields in their high power dissipation combined with advantageous high Ge speed and in the case of a NAND organization the Spei fields in their low speed at the same time advantageously reduced power loss.

Specifically, this means in practice that in the case of "ATM switching fabrics 2 × 2.4 Gbit / s" an address treatment is required every approx. 80 ns. There are also changes to the actual CAM entry, such as deleting or updating entries. The CAM design therefore requires elaborate custom designs or hard macros to meet the requirements.

In previous circuit proposals for the structure of a CAM Feldes is always a one-step implementation of the required dynamic XOR. For high Word widths (128 bits) are used for this function, even under Using BiCMOS technology, approx. 32 ns required. inclu sive of the necessary priority decoder are total about 50-70 ns needed.

It is therefore an object of the invention, a content addressable to find their memory, on the one hand, the high reaction speed of a memory with NOR organization and others on the other hand, similarly low power losses as a storage with NAND organization.

The inventor recognized that by introducing one too additional pipeline stage it also with a dynamic NOR Structure is possible, significantly higher clock rates (approx. 10 ns) to achieve than before and the data throughput significantly ge can be increased. It is advantageous here that the proposed design of the CAM structure easily in be standing CAM fields can be integrated.

Since the dynamic requirements are reduced at the same time, complex "custom design" methods can be dispensed with and the matchline read amplifiers in the CAMs can be replaced by simple structures (e.g. C ² MOS).

Since the matchline is split into m-parts, and in invent Appropriate approach the precharge phases of the following Matchline lines can also be suppressed Power loss can be significantly reduced.  

In a special application, in the area of mediation represent public ATM networks (ATM = asychronous transfer mode) that needs fast address resolution is not the absolute latency of the critical parameters because the ATM Cell usually pass through at least one output buffer fen must, and is therefore already cached. Important rather, all searches are with a maximum Throughput of searches can be answered.

The inventor therefore proposes specifically, the known in addressable memory (CAM = content addressable memory) with a memory field consisting of a memory matrix with n rows and m columns of k-bit deep memory elements, a control logic for reading in addresses to be translated with a maximum word length of m * k bit in a register and a decoder logic for reading out the data corresponding to the addresses, to further develop such that the memory matrix (4.nm) in at least two sub-matrices (4.1.1-4.20.X - 1 and 4.1.X + 1 to 4.20.X + 15) with n rows, a pipeline column ( 7 ) with intermediate storage elements (4.1.X... 4.20.X) is provided between these submatrices and is constructed in a dynamic NOR structure ,

This makes it possible to search for the addresses in Split partial addresses, matches with this part to search for addresses in a manner known per se and the further Search only with the matches found put. So it becomes a combination of parallel and se rial search performed, taking advantage of each Search types such as high speed and low loss tion, used and the disadvantages largely avoided the.

An advantageous embodiment of the memory-addressable memory (CAM) according to the invention consists in that a further pipeline column with intermediate storage elements is provided on the output side. This pipeline structure has the effect that the actual determination of a hit 1 from n and the transfer in the usual binary log ₂ (n) format are decoupled in time.

Since the processing of a line is now in m successive Sections are done, it is necessary to create the ad also eat through corresponding input pipelines adapt ne registers accordingly.

A special form of designing the content addressable ren memory (CAM) also provides that the decoder logic is constructed according to a NAND structure. Advantageous can continue to use the memory elements of the memory array 9 transistors and / or the buffer elements from FIG. 8 Transistors can be constructed in a manner known per se.

The storage mat can be used to achieve a regular structure rix can be divided into sub-matrices of the same size.

In accordance with the basic idea of the invention the inventor also proposed the method of selecting one Address from a variety of addresses, which differ Chen contents are assigned with the help of a content address sable memory (CAM) by specifying a predefined Content to further develop in such a way that the given Content and the multitude of different contents each be divided into at least two parts and iteratively first matches of the partial contents are sought, which is followed by another search on the matching In hold and addresses limited.

An improved embodiment of this method provides that the matching addresses or contents be marked with the help of a buffer and in egg In the next search step, only the marked content be searched.

A content-addressable memory can also be advantageous (CAM = content addressable memory) can be used with the  a memory field consisting of a memory matrix with n Rows and m columns from k-bit deep storage elements, ei Control logic for reading in addresses to be translated with a maximum word length of m * k bit in a register and ei ner decoder logic for reading out the correspon to the addresses data is provided, with the matrix in at least at least two submatrices with n rows are divided and two a column with intermediate storage for these submatrices elements is arranged.

To improve the timing behavior, it is also suggested conditions that a temporary storage of the minimum at least one result of the search takes place.

Furthermore, a pipeline register and / or a multimatch logic can be used on the output side in which the input and / or output data is cached that can.

The matches can correspond to an assumed number of hits to search and the existing content in approximately the same large parts are divided.

Further features of the invention result from the Unteran say and the following description of the execution examples with reference to the drawings.

The invention will be described in more detail below with reference to the drawings described. They show in detail:

Fig. 1 structure of a known content addressable SpeI chers (prior art);

Fig. 2 Inventive content addressable memory;

Fig. 3 detailed representation of the memory elements including Lich pipeline stage as C ² MOS;

Fig. 4 detail view of modified and extended memory elements of Figure 3 including pipeline stage with Pulluptransistoren.

Fig. 5 Modified and extended memory elements from Fig. 4.

Fig. 1 shows schematically the structure of a conventional len, known CAM field with the data inflows 1 (Compare & Data) for the specified data and the data to be compared, the memory 2 for the input data - which is responsible for the physical control of the column matrix is -, the row decoder 3 , the matrix field 4 with the individual matrix cells 4 .nm (n stands for the number of the row and m for the number of the column), the so-called matchlines 4 .n with the priority -Encoder 5 are connected, via which the corresponding address 6 is output in the event of a match between the specified data and the search term.

The Matchline 4 .n and the priority encoder 5 are run through asynchronously without synchronization. The total runtime is therefore determined by the runtime from creation of the Compare & Data Tc, the turnaround time by the line Tz and the turnaround time by the priority encoder Te. Thus, the total throughput time T = Tc + Tz + Te and the maximum system frequency determined by 1 / (Tc + Tz + Te).

FIG. 2 shows a CAM modified according to the invention with additional pipeline stages, consisting of a pipeline register 9 on the input side, a pipeline column 7 in the CAM field 4 , a further pipeline column 8 immediately before the priority encoder 5 and finally one Multimatch logic 10 behind the priority encoder 5 for post-processing.

The multimatch logic 10 either outputs a signal when required, which indicates that not only exactly one hit, but several hits have been found, as a result of which the address output may not be valid or there is an error in the initialization. Alternatively, the priority encoder can also output the lowest or largest address if there are several addresses found.

This structure of the CAM according to the invention now results in a maximum system frequency from the minimum of the values [1 / (Tc + Tz / 2); 1 / (Tz / 2)], which thus turns out to be significantly higher than in a conventional CAM structure from FIG. 1 and at the same time, however, only has an insignificantly higher power loss.

The structure of such pipeline stages is detailed in "Distri buted Logic Memory DLM ", T. Kohonen, Content Addressable Memo Ries, 1987, described by Springer-Verlag. This revelation the content is hereby fully described in the description accepted.

It should also be mentioned that only the precharge or match lines are shown in FIGS . 1 and 2 as connecting lines of the individual memory elements, since only the principle of the CAM is to be shown. In Fig. 1, the match line in contrast to Fig. 2 is shown continuously, while after the insertion of the pipeline stage according to the invention, this line is shown broken down into two sections. Column 7 also represents a simple register bank which effects a column-wise sampling of signal A (applied bit of the comparison word) from top to bottom. Column 8 can also consist of a register and line-by-line clocking of the match_ * signal from right to left.

Fig. 3 shows a section of a line from the CAM matrix with three matrix elements X - 2, X - 1, X + 1 and the intermediate between X - 1 and X + 1 matrix element X of a pipeline stage in a possible realization as C ² MOS.

Here only the precharge phase Φ1N in the column X (gray background) has to be wired, whereby the phase Φ1 is fed line by line. While Φ1 = low, the prechar is executed (transistors A9... And C1, C2 closed); with Φ1 → 1 MATCH_p <+0 <is optionally discharged / evaluated via A9 and the value is transferred to the first latch level "level 1 " of register C; with the next Φ1 → 0, depending on this takeover, a pre-charge to MATCH_p <+1 <is carried out again, if MATCH_p <+0 <= 1 and thus Sc1 = 0. The conditions MATCH = high and Mismatch = Low apply. If there was no match in the previous cycle, the subsequent stage precharges to 0 = mismatch and all other subsequent segments will also report mismatch in terms of their function.

The additional column X according to the invention consists of 8- Transistor elements, in contrast to the 9-transistor CAM Element. A realization is therefore in the same cell grid possible and does not require a fundamental redesign the cell structure of the CAM.

A normal mat - not part of the pipeline structure rix element itself consists of a usual 6-transistor Memory cell with the write transistors A5 and A6, as well the feedback holding inverters I1 and I2. The Transisto ren A7, A8 and A9 form a dynamic NOR.

The individual phases in a search run are as follows:

• - precharge. Φ1 = 0; Match_p <+0 <= 1; Transistor C1 and C2 locked.
• - Rating columns X - 2. , , X - 1 Φ1 = 1; Transistors C1 and C2 opened. The value of Match_p <+0 <can be via C0 and C3 are transferred to the internal node Sc1.
• - Precharge 2 : The SC1 value is passed to the Match_p <+1 <node via the transistors C5 and C6 that are now open.

Figs. 4 also shows a section of a line from the CAM array with three matrix elements X - 2 X - 1, X + 1 and between X - lying 1 and X + 1 matrix element X pelinestufe a Pi, however for the design with pullup transistors. That means, following the flip-flop, its output controls a switchable pullup / pulldown.

Each cell can use the paths A0 / A1 or A2 / A3 to matchel Optionally pull the device to "0". Is the saved value correct? Sa1 does not match the search value A, so at z. B. Sa1 = 1 and A = 0 the transistors A3 and A2 opened. Thus, over the path A2 / A3 pulled the Match_p <+0 <to "0". In this As is usual with N-Mos Logic, the trap becomes permanent loss power generated.

The function of column X is comparable to column X from FIG. 3. Here, the pull-up function is only generated via transistors C8 and C9 if in the previous section Match_p <+0 <to "1" and thus the Output of inverter I3 is at "0 '. If no match was found in the previous segment, the subsequent match line is automatically kept at" 0 "(= mismatch) via transistor C10. The existing power loss is thus reduced.

FIG. 5 shows a modification to FIG. 4, in which the matchline can be kept "high" (= match) if (from left to right) at least one segment had a match. The element I4 can disable the "mismatch" stages (= "pulldown" stages) of the subsequent segment line and thus z. B. realize a 1k × 2 × 64-CAM field instead of a 1k × 128-CAM field. The paths D0 / D1 or D2 / D3 can be switched through, but since the control line Sd2 can be kept at "1" by I4 under certain circumstances, pulling the match line to "0" can be avoided. I4 can also be switched as a NAND.

With the method and device according to the invention on the one hand a high reaction speed of the memory with NOR organization and on the other hand similarly low ver like a store with NAND organization enough.

It is understood that the above features of Invention not only in the specified combination, but also in other combinations or alone can be used without departing from the scope of the invention.  

LIST OF REFERENCE NUMBERS

1

data flows

2

Storage

3

Row decoder

4

Matrix pad / CAM field
4.nm storage elements
4.n Matchline

5

Priority Encoder

6

issued address

7

Pipeline column

8th

Pipeline column

9

Pipeline register

10

Multi-Match Logic
n row of storage elements
m column of storage elements
I1. , , I4 inverter
A created bit of the comparison word
ON inverted bit of the comparison word
A0. , , A9 transistors
C0. , , C10 transistors
D0. , , D4 transistors
Φ1 phase
Φ1N precharge phase
Tc runtime from creation of Compare & Data
Te throughput time through the priority encoder
Tz lead time through a line

Claims (8)

1. Content-addressable memory (CAM) with a memory field ( 4 ) consisting of a memory matrix (4.nm) with n rows and m columns of k-bit deep memory elements, a control logic for reading in addresses to be translated with a Maximum word length of m * k bit in a register and a decoder logic for reading out the data corresponding to the addresses, characterized in that the memory matrix (4.nm) in at least two sub-matrices (4.1.1-4.20.X - 1 and 4.1. X + 1 to 4.20.X + 15) divided with n rows, a pipe line column ( 7 ) with intermediate storage elements (4.1.X... 4.20.X) is provided between these submatrices and is constructed in a dynamic NOR structure , 2. Content-addressable memory (CAM) according to the preceding claim 1, characterized in that a further pipeline column ( 8 ) with intermediate storage elements is provided on the output side. 3. Content-addressable memory (CAM) according to one of the preceding claims 1 to 2, characterized in that a pipeline register ( 9 ) and / or a multimatch logic ( 10 ) is provided on the input side. 4. Content-addressable memory (CAM) according to one of the preceding claims 1 to 3, characterized in that the decoder logic ( 3 ) is constructed according to an XOR structure. 5. Content-addressable memory (CAM) according to one of the preceding claims 1 to 3, characterized in that the decoder logic ( 3 ) is constructed in accordance with a NAND structure. 6. Content Addressable Memory (CAM) according to one of the preceding claims 1 to 5, characterized records that the memory elements of the memory array are made up of 9 transistors. 7. Content Addressable Memory (CAM) according to one of the preceding claims 1 to 6, characterized records that the intermediate storage elements from 8 Transistors (C0-C7) are constructed. 8. Content Addressable Memory (CAM) according to one of the preceding claims 1 to 7, characterized records that the memory matrix in equal size Sub-matrices is divided.