DE10012107C2 - Test environment and method for examining the functionality of a clocked electronic circuit - Google Patents

Description

The invention relates to a test environment for examination electronic systems, with the test environment designed in this way is that they have values to study the electronic sy stems generated and then a reaction of the electronics system.

The invention further relates to a method for testing a electronic system, with values of internal register of the electronic system determined and in a test environment are saved, with commands for the elek tronic system are generated, which lead to change the values of individual registers.

The term "electronic system" is in its broadest Meaning meant and includes subsystems or individual Building blocks like ASICs.

It is known to have correct functionality from integrated Check circuits by simulation. The simulation thus serves to verify the integrated circuits, or other electronic systems.

In the simulation, the electronic systems with Hil fe of test signals, especially test vectors, on their Functionality checked.

To check the function of the electronic systems, especially the integrated electronic circuits, internal registers are checked and monitored.

For processors or microcontrollers, the finished  Circuit usually software verified. To do this the software compiles and runs on a processor brought. A special debugging interface can be used in of the software set breakpoints. Breakpoints are points at whom the program should be stopped, especially special depending on a special condition in the pro program code.

For field programmable gate arrays (FPGAs) or others programmable logic modules, the same procedure Ren can be used by a source code (usually a hardware description language) is "compiled" that means is synthesized and the resulting code an FPGA. Koch et. al., ACM Transactions on Design Automation of Electronic Systems (April 1998) Vol. 3, No. 2, p. 209-30, describe such source-level debugging, based on a hardware description language on behavior least level. The speed of verification increased by using hardware emulation. The break points are in the source code as well as in the circuit visible in order to recognize the breakpoint on the one hand Hardware level, on the other hand debugging at source code level to enable. Each breakpoint is encoded by an ID te that is different for different breakpoints, and with simple hardware means at full emulation speed can be recognized. From tracing the to The circuit can read the breakpoints be checked for errors at source code level.

EP 0 725 342 A1 describes a tracer system with a recording unit, the dynamic investigations central processor system. Doing so all consecutive code Compare addresses with each other and only those addresses  recorded, whose address difference is a predeterminable value exceeds. This means that the tracer only becomes the source and destination of size-adjustable jumps recorded so that the available trace buffer is better used.

It is known to register by means of so-called scan Chains or scan paths controllable and observable to ma chen. For this purpose, all registers become a long slide ghost connected. By clocking this shift register the content is visible to the outside via special output pins be made. Values are read in via special le input pins. However, this cannot be done at runtime the circuit happen. Instead, the circuit must be switched on will hold.

To the essential state of a circuit during the run time to watch, the interesting registers are over Pins led outwards. A Lo gikanalysator the pins and thus the states observed the.

Another known way is to use the values the interesting internal registers in an internal memory  store. But this leads to egg after a short time memory overflow.

The object of the invention is a test environment and a method to create internal registers of the subjects to be examined Check the electronic circuit quickly and reliably to be able to. This task is accomplished by the test circuit according to claim 1 and the method according to claim 5 solved. Advantageous configurations are the subject of the dependent Expectations.

According to the invention, the problem is solved in that a generic test environment is designed so that the Test environment contains a comparator that can determine whether a value stored in the register has changed.

Furthermore, the problem is solved in that a genus is carried out in such a way that it is established in which registers the values have changed, and that the changed values are saved.

A particularly simple and functional setup of the test environment exercise is characterized in that the comparator and the Registers have the same bit widths.

To increase the test speed, it is advisable that the test environment is designed so that the test environment is a Contains shift registers.

A further increase in speed with low con structural effort can be achieved in that the Shift register and the register have the same bit width.

An expedient embodiment of the test environment draws is characterized by the fact that it contains a counter.  

It is particularly advantageous that the counter has one bit has a width M, where M is any integer value can take.

Other advantages, special features and useful training provisions result from the sub-claims and the successor the presentation of a preferred embodiment hand of the figures.

Fig. 1 shows a schematic representation of state registers of an integrated electronic circuit to be tested, Fig. 2, the BR register a test environment as a state register of a vending machine.

The test environment is designed, or the test procedure is carried out in such a way that the interesting inter A register can only be saved if there is a change change results. The time is fed differentially chert. So you can externally check the state before a breakpoint and calculate the way to the breakpoint.

A preferred circuit consists of the following components:

• - A register BR to be observed
• - A comparator with the same bit width as the register BR
• - A shift register SRA of length N with one output for the first value out1, bit width like register BR
• - A shift register SRB of length N, bit width like that Counter (+1)
• - A counter (+1) of bit width M, that is, a counting range 0 to 2 ^M - 1.

The register BR is part of the normal functionality of the inte free circuit. For example, it is a state register art. The remaining components belong to the trace hardware. At the power-up, i.e. at the start, the trace hardware is initialized,  that means SRA, SRB and the counter become too Set to zero. The circuit is then active. The first value in the BR register with the first value in the SRA in the comparator (comp) compared with each new measure.

• - If the comparator finds unequal results, then the value of the register BR into the shift register SRA taken and the values contained in SRA are pushed to the left ben. The last value in the shift register is lost ren. At the same time the value of the counter in the shoot beregister SRB and the values contained in SRB pushed to the left. The last value in the shift register is lost. The counter is reset to zero puts.
• - If the comparator determines the same results, the counter is incremented by one. If the counter reaches the maximum value of 2 ^M - 1, it stops. A result of 2 ^M - 1 thus indicates a period of time greater than or equal to 2 ^M - 1 clock cycles of a change.

If a breakpoint is detected (with a suitable scarf Tung), SRA and SRB are made via the normal scan path read. By saving the previous values from Regi ster BR and the time steps between a change can Trace, i.e. the way to the breakpoint, can be reconstructed.

In this way, a test environment is created a method for testing the electronic system stems carried out so that not all occurring values for all clock cycles are saved. Instead, only Stored values that differ from their predecessor and, in addition, the number of clock cycles is saved where the value has not changed. Thereby storage space is saved considerably. By a maximum One can count the length of the shift registers SRB and Restrict SRA and thus space on the integrated scarf save.  

Such a trace circuit is particularly suitable for gates Arrays (FPGAs) or other programmable circuits. It is useful for interesting during the debugging phase Register to log the trace. In the final, well functional circuit, the trace circuit is before preferably omitted.

One or more trace circuits can also be directly on the Chip are integrated. Interesting registers can thus be found via a flexible interconnect (which is on the programmable ren circuit is present anyway) to the trace circuit connect.

Another option is to get prototypes too non-programmable hardware with the trace circuit too Mistake. After the circuit is debugged, the trace Circuit in the product-ready chips preferably omitted sen.

In Fig. 2, the register BR of the test environment is shown as a status register of a machine.

The automaton has a finite number of states, in the illustrated case 4, which are numbered 1 to 4. The machine starts with state 1 and runs through the states in the following order: 1 → 2; 2 → 2; 2 → 2; 2 → 2; 2 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 1; 1 → 2; 2 → 2; 2 → 2; 2 → 2; 2 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 3; 3 → 4. A breakpoint is detected in state 4.
0: Initialization: everything is set to zero.
0 → 1: since 1 in register BR is not equal to 0 from the first value of shift register SRA (out1), 1 is written in SRA and the count (0) in SRB; the counter is set to zero.
1 → 2: since 2 is not equal to 1, the 2 is written in SRA and the counter (0) is written in SRB; the counter is set to zero.
2 → 2: since 2 is 2, the counter is increased by one and has reached level 1.
2 → 2: since 2 is 2, the counter is increased by one and has reached level 2.
2 → 2: since 2 is 2, the counter is increased by one and has reached level 3.
2 → 3: since 3 is not equal to 2, the 3 is written in SRA and the counter (3) is written in SRB; the counter is then reset to zero.
3 → 3: since 3 is 3, the counter is increased by one and has reached level 1.
3 → 3: since 3 is 3, the counter is increased by one and has reached level 2.
3 → 3: since 3 is 3, the counter is increased by one and has reached level 3.
3 → 3: since 3 is 3, the counter is increased by one and has reached level 4.
3 → 3: since 3 is 3, the counter is increased by one and has reached level 5.
3 → 1: since 1 is not equal to 3, 1 is written in SRA and the counter (5) is written in SRB; the counter is then reset to zero.
3 → 4: The breakpoint in state 4 is detected. The counter reading indicates the number of clock cycles in which
state 3 remained before the change.

Values for the first shift register SRA and the second shift register SRB are shown in the table below.

The values of the registers shown are only examples elected to the possibility of selective storage to explain.

Of course, it is equally possible that instead of a register BR shown, several registers are used come, and that these are selectively modified according to the Values can be controlled.

Claims (8)

1. Test environment for examining the functionality of a clocked electronic circuit, in which a register (BR) of the electronic circuit is monitored with
a comparator (COMP) for detecting whether the value stored in the register (BR) has changed in the last clock cycle of the electronic circuit,
a counter (+1) for counting the number of clock cycles in which the value stored in the register (BR) has not changed,
a first memory register (SRA) for recording the value stored in the register (BR) when a change in the register value is detected, and
a second memory register (SRB) for recording the meter reading when a change in the register value is detected. 2. Test environment according to claim 1, wherein the first and second Storage registers formed by shift registers (SRA, SRB) are. 3. Test environment according to claim 1 or 2, wherein the counter (+1) stops when a maximum counter reading is reached. 4. Test environment according to one of the preceding claims, which also Means for reading out the first and second memory registers upon detection of a set breakpoint. 5. A method for examining the functionality of a clocked electronic circuit, in which a register of the electronic circuit is monitored,
in which the value stored in the register is compared with a last stored register content in each cycle, the number of cycles in which the register content has remained unchanged is counted, and
when the register content changes, the new register content and the number of clock cycles that the register content has remained unchanged are stored. 6. Examination method according to claim 5, in the counting the number of cycles at a specified maximum value remains. 7. examination method according to claim 5 or 6, wherein the new register content and the number of bars that the regi content remains unchanged, each in one shoot registers can be saved. 8. The examination method according to claim 7, wherein the shooting read register on detection of a breakpoint the order of the register values stored in the register before Er range to reconstruct the breakpoint.