DE10010456A1 - Reference voltage generation device for ferroelectric memory - Google Patents

Abstract

The reference voltage generation device uses reference cells (R1T,R2T ; R1C,R2C) within the ferroelectric memory provided with a logic "0" and a logic "1", at the ends of the word lines (WLT,WLC) along a reference bit line (BLTREF1, BLTREF2 ; BLCREF1,BLCREF2). The ferroelectric memory may be provided via a MOS technology, with a pulsed plate parallel to the bit line for providing a selective-read memory, with a reference or dummy cell at the end of each word line.

Description

The invention relates to a device for Reference voltage generation in ferroelectric memories.

In order to read out the stored information during storage and evaluate its information content, a reference voltage is required in addition to the actual signal. In the case of DRAM memory modules, the reference voltage automatically results from the bit line BL precharged to a center voltage VBLEQ. This fact is shown in the pulse diagrams of the accompanying FIGS. 1A and 1B for a logic "1" and a logic "0".

In the case of ferroelectric memories, on the other hand, both logical "0" as well as a logical "1" of the information signals an increase in the bit line voltage, so that Reference level for the difference ver must be generated more.

The pulse timing diagrams of the accompanying Figs. 2A and 2B respectively, the ver illustrative conditions for a logic "0" and a logical "1" on the bit line. The reference voltage U _{Ref to} be generated must be generated such that it lies approximately in the middle between the voltage levels for the logic "0" and the logic "1".

Known solutions are in "1999 Symposium on VLSI Circuits", Page 97, ff described, in which a) the reference voltage either fed via an external voltage source or b) via a pair of dummy cells at the end of the bit line is produced.  

The solutions proposed in the prior art have the following disadvantages:

• 1. 1.) A voltage generator behaves with technological Fluctuations other than memory cells and therefore cannot achieve the optimal tension.
• 2. 2.) Reference or dummy cells on the bit line can age differently than the actual memory cells due to a large number of accesses. In the worst case, it can happen that the reference or dummy cell 10 is accessed ¹⁵ times and then the reference voltage generated is compared with an unused memory cell.

It is therefore an object of the invention to provide a device for Reference voltage generation in ferroelectric memories to indicate, on the one hand, insensitive to technological Fluctuations and the other related to the memory cells in its aging conditions is balanced.

By the proposed solution, in which the reference cells to generate the reference voltage at the end of the word line are arranged along a reference bit line an equal number of accesses to the reference cells as realize on the actual memory cells and thus for the reference cells generating the reference voltage create the same aging conditions as for the rest ferroelectric memory.

In an advantageous embodiment are for one "selective read" memory, in which a "pulsed plate" paral lel is arranged to the bit line, and in which only 8 bits per active word line can be read, one each Reference cell for a logical "0" and a logical "1"  each on the true word line and the complementary Word line arranged. The proposed according to the invention However, the concept can also be used for VDD / 2 and "pulsed Use plate "parallel to the word line.

The essence of the present invention thus lies in the station wagon nation of measures, on the one hand reference cells for generation to use the reference voltage to technological swan to correctly map the results and furthermore this reference target len along the word line so that they are the same are often addressed like the actual memory cells.

The invention is based on the drawing he he purifies. Show it:

Fig. 1 is a pulse time chart for explaining the reference voltage generation DRAMs,

Fig. 2 is a pulse time chart for explaining the reference voltage level in ferroelectric memories,

Fig. 3 is a circuit diagram of an embodiment of an inventive device for generating reference voltage in ferroelectric memories and

Fig. 4A, B, C pulse timing diagrams for explaining the func tion of the circuit shown in Fig. 3.

The timing diagrams of FIGS. 1 and 2 have already been explained.

Fig. 3 shows an example of a circuit arrangement of a ferroelectric memory in MOS technology, in which a "pulsed plate" PL <disposed 0 <parallel to the bit line and a "selective read" memory form in which only 8 bits per active word line be read out. In Fig. 3 it is assumed as an example that a "1" is stored in the first cell on the far left. Reference or dummy cells R1T, R2T and R1C, R2C are arranged at the end of each word line WLT, WLC. These reference cells are each arranged along a reference bit line BLTREF1, BLTREF2, BLCREF1, BLCREF2. The reference cells R1T, R2T are short-circuited with the clock signal ϕ1 via a first MOS switch S1 and connected to the word line WLT. The reference cells R1C and R2C are short-circuited to each other via a second MOS switch S2 with the clock signal ϕ2. This connection creates the desired reference voltage on the bit line BL. The word line activates the memory cell, but is not connected to the bit line.

The pulse timing diagrams in Fig. 4A, B and C respectively show signals occurring defects in the embodiment shown in Fig. 3 circuit arrangement with the inventive reference voltage generation th. The process begins at the time t1 (Fig. 4B) with the leading edge of the word line signal WLT. After a certain time delay, MUX C goes low, then comes the leading edge of the clock signal ϕ1, which switches through the MOS switch S1, and thus connects the two reference cells R1T and R2T to one another through the dummy bit line.

The left part of FIG. 4C shows the information signal "1" on the true bit line BLT and the reference voltage generated with the aid of the reference cells R1T and R2T according to the invention during the time of the clock ϕ1.

Claims (3)

1. Device for generating reference voltage in ferro-electric memories, characterized in that reference cells (R1, R2) acted on with logic “0” and logic “1” are arranged at the end of the word line (WLT, WLC) along a reference bit line (BLT, BLC) are. 2. Device according to claim 1, characterized in that with a "selective read" memory, in which a "pulsed plate "(PPL) is arranged parallel to the bit line (BL), a reference cell (R1T, R2T and R1C and R2C) each for a logical "0" and a logical "1" with the real one Word line (WLT) and the complementary word line (WLC) are coupled. 3. Device according to claim 2, characterized in that the reference cell coupled to the true word line (WLT) len (R1T, R2T) with a first clock signal (ϕ1) with which the complementary bit line (BLC) is clocked, and with the complementary word line (WLC) connected reference cells (R1C, R2C) with a second clock signal (ϕ2) with which the true bit line (BLT) is clocked, via one MOS Switches (S1, S2) are short-circuited to one another.