DD294809A5 - CIRCUIT ARRANGEMENT FOR POTENTIALLY TRANSMITTED INFORMATION SIGNALS - Google Patents

Abstract

The invention relates to a circuit arrangement for the potential-separated transmission of information signals over two parallel separating capacitors with simultaneous suppression of common mode noise pulses. The pulse edges of the information signals are the information carriers. The information signals are transmitted via the separating capacitors, each with opposite phase. According to the invention, an inverter (2) is arranged in front of a first separator capacitor (3). The output of the first separator capacitor (3) is connected to a pulse-forming inverter (7) and the output of a second separator capacitor (4) to a non-inverting pulse shaper (8). The output of the pulse-forming inverter (7) and the output of the pulse shaper (8) is respectively connected to an input of an AND gate (9), which outputs the information signals freed from common mode noise pulses. Fig. 1 {circuit arrangement; isolated transmission; Information signals; Isolating capacitors; Gleichtaktstoerimpulse; opposite phase; inverter; Pulse shaper; AND gate}

Description

Field of application of the invention

The invention serves the potential-separated transmission of information signals while suppressing common-mode interference pulses. The invention is suitable for interrupting ground loops in data acquisition systems.

Characteristic of the known state of the art

A precise transmission of electrically analogue Informationssigna ever for further processing in digital systems requires in

general a potential separation. In this case, a fault-free transmission of the information signals via the potential separation point requires a signal preprocessing, in which the electrically analog information signals have been converted into pulse interval, pulse length or pulse code.

According to the state of the art, the potential separation is effected by magnetic isolating transformers or optocouplers.

Capacitive separating elements are known from DE-OS 3218153 for the special case of information transmission in shielded vessels.

In DE-OS 3623735 a capacitive coupling for internal information transmission in digital circuits is described.

A disadvantage of these solutions is that the capacitive separating arrangements do not distinguish between information signals and common-mode interference signals, and thus no suppression of the common-mode interference signals can take place. Therefore, the known solutions with capacitive separating elements are not suitable for use in measuring circuits.

Object of the invention

The aim of the invention is to minimize the production and energy costs for signal transmission via the potential separation point. At the same time a small penetration capacity and a high separation voltage should be achieved.

Explanation of the essence of the invention

The invention has for its object to achieve a fail-safe transmission of information signals via a potential separation point with two parallel separating capacitors with simultaneous suppression of common mode noise. The pulse edges of the information signals are the information carriers. As is known, the information signals are transmitted with respective opposite phase via the two separating capacitors.

According to the invention, the signal input of the circuit arrangement is connected via an inverter 2 to the first separation capacitor 3 and directly to the second separation capacitor 4. Furthermore, the first separation capacitor 3, a pulse-forming inverter 7 and the second separation capacitor 4, a non-inverting pulse shaper 8 downstream. The output of the pulse-forming inverter 7 and the output of the pulse shaper 8 are connected to the inputs of an AND gate 9, which outputs the freed from the interference information signals. According to the invention, the suppression of the common-mode interference signals results from their in-phase effect via both separating capacitors 3 and 4 with subsequent negation in one signal branch and subsequent AND connection of both signal branches.

embodiment

The invention will be explained in more detail with reference to the following embodiment.

1 shows an arrangement according to the invention for the potential-isolated transmission of information signals via two isolating capacitors

According to FIG. 1, the information signals 10 to be transmitted are at the input of the circuit arrangement Reference potential U _S si. Between the reference potential U ₃ si at the input of the circuit arrangement and the Reference potential U ₃₃₂ at the output is the Si5rimpulequelle 11, from which the common mode noise signals emanate. The information signals 10 are fed to the input of a pulse shaper 1. The output of the pulse shaper 1 is a

second isolating capacitor 4 and upper an inverter 2 connected to a first separator capacitor 3. This will be the

Information signals 10 in opposite phase over the two separating capacitors 3 and 4 transmitted. The first separator capacitor

is a pulse-forming inverter 7 and the second separation capacitor 4, a non-inverting pulse shaper 8 downstream.

By means of a high-impedance resistor 5 at the input of the pulse-forming inverter 7, this input is on a

positive potential. This produces at the output of the pulse-forming inverter 7 positive pulses when andessen input negative pulses.

By means of a high-impedance resistor β at the input of the pulse shaper 8, this input is held at zero potential,

so that positive pulses at the input of the pulse shaper 8 generate positive pulses again at the output.

The output of the pulse-forming inverter 7 and the pulse shaper 8 is * in each case to the input of an AND gate. 9

guided, so that the positive information signals on both inputs of the AND gate 9 in turn positive signals on

Output of the gate 9 result and the common mode noise signals are suppressed. The l'.iterpression of the common mode noise is achieved as follows. Since the glitch source 11 between the Reference potentials Ussi and Us »acts at the input and output of the circuit arrangement, the common mode noise signals are over

the separating capacitors 3 and 4 in phase. About the pulse-forming inverter 7 can only negative

Common mode noise pulses arrive as positive pulses at an input of the AND gate 9, while on the

non-inverting pulse shaper 8 only positive pulses as positive pulses to the other input of the AND gate 9gelangen. Thus, the common-mode interference pulses are faded out in a signal branch and are replaced by the following AND-

Linking of the two signal branches suppressed. For the separation capacitors 3 and 4, a capacitance in the range up to about 1OpF has proven to be advantageous, so problems dal

be avoided by long time constants on the subsequent elements of the circuit.

Claims (1)

Switching arrangement for the isolated transmission of information signals via two parallel separating capacitors with simultaneous suppression of Gleichtaktstörimpulsen, wherein the pulse edges of the information signals are the information carrier and the information signals are transmitted with opposite phase across the two isolating capacitors, characterized in that the signal input of the circuit via an inverter (2) is connected to the first separation capacitor (3) and directly to the second separation capacitor (4) that the first separation capacitor (3) a pulse-forming inverter (7) and the second separation capacitor (4) are arranged downstream of a non-inverting pulse shaper (8) and that the output of the pulse-forming inverter (7) and the output of the pulse shaper (8) are connected to the inputs of an AND gate (9). , For this 1 Soite drawing